VIPower® MO-7 Standard High-Side Drivers Manual Datasheet by STMicroelectronics

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July 2018 UM1922 Rev 2 1/196
1
UM1922
User manual
VIPower® M0-7 standard high-side drivers hardware design guide
Introduction
VIPower® parallel high-side drivers have reached the 7th generation of smart power drivers
(internally called M0-7). In this latest set of drivers all the experience and know-how from
existing features of the previous generations as well as new features have been
implemented.
The continuous increasing demanding requirements from automotive customers in terms of
quality, reliability, flexibility and cost effective system solutions represent the basic factor of
new protection feature concept (latch off in overload condition beside the already known
auto restart feature) and new diagnostic features like real time device case temperature and
battery terminal voltage sensing beside the already existing output current sensing available
to the microcontroller in a unique “MultiSense” pin.
Purpose of this user manual is to give a comprehensive “tool kit” for a better understanding
of the behavior of the M0-7 parallel High Side Drivers (abbreviation HSDs) in their
application usage context and thus allowing the design engineer an easier design in.
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Contents UM1922
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Contents
1 General items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 Overview about M0-7 standard high-side drivers . . . . . . . . . . . . . . . . . . . .11
1.2 Application schematics – monolithic devices . . . . . . . . . . . . . . . . . . . . . . 12
1.3 Application schematics – hybrid devices . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 Application schematics – description of external components . . . . . . . . . 13
2 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Reverse battery protection of monolithic HSDs . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Schottky diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.2 Diode + resistor in GND line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.3 N-channel MOSFET in GND line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.4 P-channel MOSFET in the VCC line . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.5 Dedicated ST Reverse FET solution . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3 Protection against battery transients . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.1 Introduction on automotive electrical hazards . . . . . . . . . . . . . . . . . . . . . 34
3.2 Source of hazard on automotive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.1 Conducted hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3 Propagation of electrical hazards on the supply rail . . . . . . . . . . . . . . . . . 35
3.4 Standard for the protection of automotive electronics . . . . . . . . . . . . . . . 36
3.5 Basic application schematic to protect a M0-7 standard monolithic high-side
driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5.1 Components dimensioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.6 Component dimensioning for hybrid devices . . . . . . . . . . . . . . . . . . . . . . 41
3.6.1 Dimensioning of the series resistors on I/O line . . . . . . . . . . . . . . . . . . 43
3.6.2 Dimensioning of the GND network to pass the ISO n.1 and 2a level IV
(2011 edition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4 Usage/handling of fault reset and standby . . . . . . . . . . . . . . . . . . . . . 48
4.1 Latch-off functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3 Flexible blanking time (fault reset management) . . . . . . . . . . . . . . . . . . . 52
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5 Usage and handling of MultiSense SEL pin . . . . . . . . . . . . . . . . . . . . 57
5.1 Classification of M0-7 HSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.2 SEL pins truth table (device dependant) . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3 Connection of SEL pins with control logic (Microcontroller) . . . . . . . . . . . 59
6 Load compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.1 Bulbs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2 Power loss calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.2.1 Conduction losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.2.2 Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3.1 Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3.2 Turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.3 Calculation of dissipated energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.4 Selection criterion with reference to I-L plot . . . . . . . . . . . . . . . . . . . . . . 99
6.3.5 External clamping protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3.6 Loss of VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7 MultiSense - analogue current sense . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
7.2 Principle of MultiSense signal generation . . . . . . . . . . . . . . . . . . . . . . . .118
7.2.1 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.2.2 Normal operation (channel ON, no fault, SEn active) . . . . . . . . . . . . . 119
7.2.3 Current monitoring range of linear operation . . . . . . . . . . . . . . . . . . . . 119
7.2.4 Impact of the output voltage to the MultiSense output . . . . . . . . . . . . . 122
7.2.5 Failure flag indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.2.6 Considerations on MultiSense resistor choice for current monitor . . . 124
7.2.7 Usage when multiplexing several devices . . . . . . . . . . . . . . . . . . . . . . 127
7.2.8 LED diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.2.9 Diagnostic with paralleled loads / partial load detection . . . . . . . . . . . 130
7.2.10 K factor calibration method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.2.11 Open load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.2.12 MultiSense diagnostic evaluation with SPC560Bxx . . . . . . . . . . . . . . . 142
7.2.13 MultiSense low pass filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.3 TCASE, VCC (device dependent) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.3.1 VCC monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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7.3.2 Case temperature monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.3.3 Example on evaluation of VCC, TCASE and diagnostic with SPC560Bxx
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
8 Paralleling of devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
8.1 Paralleling of logic input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
8.1.1 Monolithic HSDs supplied from different supply lines . . . . . . . . . . . . . 153
8.1.2 Hybrid HSDs supplied from different supply lines . . . . . . . . . . . . . . . . 155
8.1.3 Mix of monolithic and hybrid HSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
8.2 Paralleling of MultiSense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
8.2.1 Monolithic HSDs supplied from different supply lines . . . . . . . . . . . . . 158
8.2.2 Hybrid HSDs supplied from different supply lines . . . . . . . . . . . . . . . . 159
8.2.3 Mix of monolithic and hybrid HSDs supplied from different supply lines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
8.3 Paralleling of GND protection network . . . . . . . . . . . . . . . . . . . . . . . . . . 162
8.4 Paralleling of outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
8.4.1 Current balancing with resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . 163
8.4.2 Overload behavior with resistive loads . . . . . . . . . . . . . . . . . . . . . . . . 165
8.4.3 Driving inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
9 Inverse output current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
9.2 Device capability versus inverse current . . . . . . . . . . . . . . . . . . . . . . . . 173
9.2.1 Device in steady state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
9.2.2 Device driven in PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
9.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
10 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
10.1 EMC requirements for ESD at module level . . . . . . . . . . . . . . . . . . . . . . 180
10.2 EMC Requirements for ESD at device level . . . . . . . . . . . . . . . . . . . . . . 183
10.3 Design and layout basic suggestions to increase ESD failure point level 184
11 Usage in “H-Bridge” configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 185
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
11.2 M0-7 high-side drivers in “H-Bridges”: specific considerations . . . . . . . 186
11.2.1 Short circuit event to ground and to battery . . . . . . . . . . . . . . . . . . . . . 186
11.2.2 Cross current events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
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11.2.3 Usage of MultiSense TCHIP in H-Bridges . . . . . . . . . . . . . . . . . . . . . . 191
11.2.4 Freewheeling current of inductive loads . . . . . . . . . . . . . . . . . . . . . . . 191
Appendix A References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
List of tables UM1922
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List of tables
Table 1. Reverse battery protection concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2. Reverse battery-voltages on pins (VND7040AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. Static reverse battery - voltages on pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4. Static reverse battery - voltages on pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. ISO 7637-2: 2004 (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 6. ISO 7637-2: 2011 (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7. ISO 7637-2 2004 and 2011 tests and results on monolithic HSDs. . . . . . . . . . . . . . . . . . . 41
Table 8. GND network proposals for Hybrids HSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 9. ISO 7637-2 levels and results for Hybrid HSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 10. M0-7 HSD devices not featuring latch-off functionality and FaultRST pin . . . . . . . . . . . . . 48
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 12. MultiSense multiplexer addressing for a dual channel device . . . . . . . . . . . . . . . . . . . . . . 49
Table 13. Classification of M0-7 HSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 14. Full logic implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 15. Reduced logic implementation (only current sense signal, no TCHIP, no VCC) . . . . . . . . 59
Table 16. Truth table for monolithic devices, separate MultiSense . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 17. Truth table for monolithic devices, common MultiSense. . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 18. Truth table monolithic + hybrid, separate MultiSense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 19. Truth table hybrid devices separate supply rails, common MultiSense . . . . . . . . . . . . . . . 64
Table 20. Typical bulb loads for given M0-7 RON class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 21. VND7040AJ measurement of switching losses versus L in steady state . . . . . . . . . . . . . . 90
Table 22. VND7040AJ measurement of switching losses versus L in PWM mode (with external
freewheeling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 23. Maximum capacitance on the HSD output (no power limitation triggered - Tjstart ~ 25 °C) 93
Table 24. Paralleling bulbs – overview on the example of VND7020AJ . . . . . . . . . . . . . . . . . . . . . . 130
Table 25. VSENSE measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 26. MultiSense pin levels in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 27. Diagnostics - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 28. SPC560Bxx example signals mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 29. Example of channels configuration on a dual channels HSD . . . . . . . . . . . . . . . . . . . . . . 174
Table 30. Inverse current threshold experimental values according to channels status (Ch0 is the
channel under test, Ch0 = ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 31. Inverse current threshold experimental values according to channels status (Ch0 is the
channel under test, Ch0 = OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 32. M0-7 HSDs ESD results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 33. Maximum switching slopes which do not cause cross current due to MOSFETs capacitances
(measurements on a sample on each component) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 34. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
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UM1922 List of figures
10
List of figures
Figure 1. Typical application schematics – monolithic devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Typical application schematics – hybrid devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. Voltage levels during reverse battery (diode + resistor protection). . . . . . . . . . . . . . . . . . . 18
Figure 4. Negative GND shift (TDEMAG > tD_STBY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5. GND resistor requirements (inductive load)–test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6. Measurement example (tDEMAG > tD_STBY) without GND resistor . . . . . . . . . . . . . . . . . . . 22
Figure 7. Measurement example (tDEMAG > tD_STBY) with 4.7 k GND resistor . . . . . . . . . . . . . 23
Figure 8. Generic schematic and test setup with N-channel MOSFET in GND line . . . . . . . . . . . . . 26
Figure 9. MOSFET solution in GND – experiment VND7020AJ, ISOpulse 1 (-150V, 90 ) . . . . . . . 27
Figure 10. Reverse battery test VN7016AJ (13.5 V -4 V, 82 m, R2 = 15 k) as per LV 124:
2009-10 standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. Generic schematic and test setup with P-channel MOSFET in VCC line . . . . . . . . . . . . . . 29
Figure 12. MOSFET solution in VCC – experiment VND7020AJ, ISOpulse 1 (-100 V, 90 ) . . . . . . . 30
Figure 13. Reverse battery test according to LV 124:2009-10: VN7016AJ (13.5 V at -4 V, 82 m,
R2 = 1k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14. Reverse polarity protection – reverse FET protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. Maximum current versus duration time of VN5R003H-E . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 16. Conducted hazards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. Radiated hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. Various surges occurring in the supply rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. Internal structures involved during application of ISO 7637-2 pulse 1 in a monolithic HSD
and indication of pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. Basic test setup for ISO 7637-2 pulses applied to VND7020AJ . . . . . . . . . . . . . . . . . . . . . 40
Figure 21. Internal structures involved during application of ISO 7637-2 (2004) pulse 1 in Hybrid HSD
and indication of pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 22. Internal structures involved during application of ISO 7637-2 (2011) pulse 1 in Hybrid HSD
and indication of pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. Basic test setup for ISO 7637-2 (2004) pulses applied to VN7004AH-E . . . . . . . . . . . . . . 44
Figure 24. Recommended GND network for ISO 7637-2 (2011) level IV . . . . . . . . . . . . . . . . . . . . . . 45
Figure 25. Basic Test setup for ISO 7637-2 (2011) pulses applied to VN7004AH-E. . . . . . . . . . . . . . 46
Figure 26. Latch functionality - behavior in hard short circuit condition (Tjunction << TTSD). . . . . . . . .50
Figure 27. Latch functionality - behavior in hard short circuit condition (TR < Tjunction < TTSD) . . . . 50
Figure 28. Latch functionality - behavior in hard short circuit condition (autorestart mode and latch-off)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 29. Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 30. Standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 31. FR handling example - bulb inrush blanking (VNQ7140AJ) . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 32. Common FaultRST pin handling example – basic schematic (without decoupling
components) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 33. FaultRST pin handling concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 34. FaultRST pin handling example - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 35. FaultRST pin handling example – detail of diagnostic period . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 36. FaultRST pin handling example – detail of unlatch pulse (Ch. 2). . . . . . . . . . . . . . . . . . . . 56
Figure 37. Monolithic devices, common power supply rails, separate MultiSense . . . . . . . . . . . . . . . 60
Figure 38. Monolithic devices, common power supply rails, common MultiSense . . . . . . . . . . . . . . . 61
Figure 39. Monolithic devices, separate power supply rails, common MultiSense . . . . . . . . . . . . . . . 62
Figure 40. Monolithic and hybrid device, separate power supply rails, separate MultiSense . . . . . . . 63
Figure 41. Hybrid devices, separate power supply rails, common MultiSense . . . . . . . . . . . . . . . . . . 64
List of figures UM1922
8/196 UM1922 Rev 2
Figure 42. Principle of the setup used for the simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 43. Simulation result–normal condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 44. Simulation result–cold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 45. Simulation result–hot condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 46. Control stage current consumption in ON state, all channels on driving nominal load -
datasheet value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 47. Steady state condition, datasheet values IOUT = 3 A, RON at 150 ºC = 44 m . . . . . . . . . 70
Figure 48. RON dependency on temperature (measured on a VND7140AJ sample) . . . . . . . . . . . . . 71
Figure 49. RON dependency on VCC (measured on a VND7140AJ sample). . . . . . . . . . . . . . . . . . . 71
Figure 50. RON dependency on IOUT (measured on a VND7140AJ sample) . . . . . . . . . . . . . . . . . . 72
Figure 51. Switching and conduction losses (resistive loads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 52. Example of switching losses on VND7040AJ with 4.5 resistive load . . . . . . . . . . . . . . . . 76
Figure 53. Example of switching losses on VNQ7040AY with 5.2 resistive load . . . . . . . . . . . . . . . 77
Figure 54. LED cluster example 1–LED test board (6 x 3 LEDs OSRAM LA E67-4) . . . . . . . . . . . . . 77
Figure 55. LED cluster example 2–tail & brake light (VW Passat B6) . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 56. Slew rate and switching losses (VND7140AJ, LED test board) . . . . . . . . . . . . . . . . . . . . . 79
Figure 57. Slew rate and switching losses (VND7140AJ, VW Passat B6–tail & brake). . . . . . . . . . . . 80
Figure 58. Switching losses with low inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 59. Low inductance (TDEMAG << tWOFF) – measurement example . . . . . . . . . . . . . . . . . . . . 82
Figure 60. Switching losses with high inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 61. High inductance (TDEMAG >> tWOFF) – measurement example . . . . . . . . . . . . . . . . . . . 84
Figure 62. Switching losses with high inductance and external freewheeling (single event) . . . . . . . 85
Figure 63. Switching losses – high inductance + ext. freewheeling (PWM operation). . . . . . . . . . . . . 86
Figure 64. High inductance (TDEMAG > tWOFF): measurement example 1 . . . . . . . . . . . . . . . . . . . . 87
Figure 65. Figure 62: High inductance (TDEMAG > tWOFF) – measurement example 2 . . . . . . . . . . . . 87
Figure 66. High inductance (TDEMAG > TPWM_OFF) – measurement example. . . . . . . . . . . . . . . . . . . 88
Figure 67. High inductance (TDEMAG > TPWM_OFF) – measurement example 4 . . . . . . . . . . . . . . . . . 89
Figure 68. A typical example of HSD combined with capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 69. Measurement example - VND7040AJ on 320µF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 70. Xenon load - slew rate, switching losses (VN7016AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 71. HSD turn-on phase with inductive load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 72. Turn-on example: VND7140AJ with inductive load (L = 260 mH, R = 81 ) . . . . . . . . . . . 96
Figure 73. Inductive load–HSD turn-off phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 74. Inductive load: turn-off example: VND7040AJ, L = 260 mH, R = 81 . . . . . . . . . . . . . . . . 99
Figure 75. Maximum turn-off current versus inductance – VND7020AJ datasheet . . . . . . . . . . . . . . 101
Figure 76. Inductive load – turn-off: VND7020AJ, L = 2.2 mH, R = 4 . . . . . . . . . . . . . . . . . . . . . . 102
Figure 77. Example of external clamping circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 78. Test setup-verification of new external clamp proposal . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 79. PWM 50% at 100 Hz, 2 mH / 5.5 (VND7040AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 80. PWM 80 % at 400 Hz, 2 mH / 5.5 (VND7040AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 81. ISO pulse 1 (-100 V, 10 ), 2 mH at 5.5 (VND7040AJ) . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 82. Loss of VCC, 2 mH / 5.5 (VND7040AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 83. Loss of VCC with inductive load (monolithic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 84. Test setup – loss of VCC (monolithic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 85. Loss of VCC (VND7020AJ, 1 mH/ 3.5 , 100 nF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 86. Loss of VCC (VND7020AJ, 1 mH/ 3.5 , 100 nF + 2.2 µF). . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 87. Loss of VCC (VND7020AJ, 1 mH/ 3.5 , 100 nF + 100 µF) . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 88. M0-7 driver with analogue current sense – block diagram . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 89. Structure of MultiSense signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 90. VSENSE saturation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 91. Plotted VSENSE with increasing IOUT versus time with RSENSE = 220 (left) and
RSENSE = 470 (right) for VND7040AJ and corresponding XY plot (VCC = 14 V) . . . . 121
UM1922 Rev 2 9/196
UM1922 List of figures
10
Figure 92. Behavior of VSENSE_SAT vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 93. Behavior of ISENSE_SAT vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 94. Failure flag indication-example 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 95. MultiSense operation of VND7040AJ in current monitoring with increasing overload and
consequent device’s latch off due to thermal protection intervention . . . . . . . . . . . . . . . . 124
Figure 96. MultiSense in TCHIP mode behavior versus RSENSE for VND7140AJ at VCC = 14 V and
TC = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 97. MultiSense in VCC mode behavior versus RSENSE for VND7140AJ at VCC = 14 V and
TC = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 98. Bulb / LED diagnostic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 99. Minimum ON time for correct VSENSE sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 100. Switched current sense resistor–example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 101. Example of single point calibration at low current for VND7020AJ. . . . . . . . . . . . . . . . . . 133
Figure 102. VSENSE vs IOUT measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 103. RPU calculation with no load connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 104. RPU calculation with load connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 105. Analogue HSD – open load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 106. Open load / short to VCC detection in OFF state - delay after IN is set from low to high . 138
Figure 107. Open load/short to VCC detection in OFF state - delay after SEn is set from low to high . 139
Figure 108. Open-load without pull-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 109. Open-load with pull-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 110. Short circuit to VBATT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 111. Power limitation or overtemperature waveforms (in autorestart mode) . . . . . . . . . . . . . . 142
Figure 112. Power limitation or overtemperature waveforms (in lacth mode) . . . . . . . . . . . . . . . . . . . 142
Figure 113. eMIOS PWM generation mode principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 114. SPC extended ADC channels block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 115. CSENSE diagnostic approach principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 116. Example of connection of multiple HSDs to SPC using external ADC MUX control. . . . . 145
Figure 117. SPC560Bxx example MultiSense trigger points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 118. Low pass filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 119. GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 120. VCC monitor transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 121. Example MultiSense reading on multiple HSDs with GND shift compensation . . . . . . . . 151
Figure 122. GND shift measurement position example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 123. Direct connection of SEn pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 124. Proper connection of SEn pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 125. Direct connection of SEn pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 126. Direct connection of SEn pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 127. Direct connection of SEn pins (not recommended) during loss of GND . . . . . . . . . . . . . 157
Figure 128. Paralleling of inputs summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 129. Direct connection of MultiSense pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 130. Safe solution for paralleling MultiSense pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 131. Direct connection of MultiSense pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 132. Direct connection of MultiSense pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 133. Paralleling of MultiSense summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 134. Common GND network with different supply lines (not recommended) . . . . . . . . . . . . . . 162
Figure 135. Test setup – paralleling of outputs (load current sharing). . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 136. Sharing of load current, VON regulation (VND7020AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 137. Current sense behavior at low current (VND7020AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 138. Sharing of load current, VON regulation (VND7140AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 139. Current sense behavior at low current (VND7140AJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 140. Behavior during overload condition (VND7040AJ, Ch.0 + Ch.1) . . . . . . . . . . . . . . . . . . . 166
List of figures UM1922
10/196 UM1922 Rev 2
Figure 141. Test setup–paralleling of outputs (inductive loads). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 142. Bulb with 10 µH (VND7040AJ, Ch.0 + Ch.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 143. 2 mH / 2.8 (VND7040AJ, Ch.0 + Ch.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 144. 2mH / 2.8 with external freewheeling (VND7040AJ, Ch.0 + Ch.1) . . . . . . . . . . . . . . . . 168
Figure 145. Test setup – inductive short circuit test with paralleled outputs . . . . . . . . . . . . . . . . . . . . 169
Figure 146. Inductive short – 5 µH/50 m (VND7020AJ, Ch0 and Ch1 in parallel, Latch mode) . . . . 170
Figure 147. Inverse current injected by a capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 148. Inverse Current injected by an inductive load in the high-side driver of an H-Bridge . . . . 173
Figure 149. Inverse current Injected by a short circuit to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 150. Current Injection test set-up and concerning a double channel HSD . . . . . . . . . . . . . . . . 177
Figure 151. Waveforms related to the inverse injection on a channel driven in PMW . . . . . . . . . . . . . 178
Figure 152. ESD current pulses according to different standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 153. ESD test application scheme for HSD placed on a powered module . . . . . . . . . . . . . . . . 182
Figure 154. ESD charge device model test scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 155. Equivalent circuit for ESD protection dimensioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 156. H-Bridge scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Figure 157. Example of automobile multi-motor driving connection . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 158. VND7040AJ cross conduction with different OMNIFET delay times . . . . . . . . . . . . . . . . 187
Figure 159. VND7140AJ cross conduction with different OMNIFET delay times . . . . . . . . . . . . . . . . 188
Figure 160. VND7012AY cross conduction with different OMNIFET delay times . . . . . . . . . . . . . . . . 189
Figure 161. PowerMOS capacitance effect during high dVDS/dt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 162. Test set up for H-Bridge cross current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 163. H-Bridge formed by one VND7140AJ and two OMNIFETs II showing the high-side
freewheeling phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 164. H-Bridge formed by one VND7140AJ and two OMNIFETs II showing the high-side
freewheeling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
Figure 165. H-Bridge formed by one VND7012AY and two OMNIFETs II showing the freewheeling via
HSD body diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
UM1922 Rev 2 11/196
UM1922 General items
195
1 General items
1.1 Overview about M0-7 standard high-side drivers
The M0-7 standard high-side drivers are manufactured using STMicroelectronics®
proprietary VIPower® technology. The devices are designed to drive 12 V automotive
resistive as well as inductive and capacitive loads connected to ground. A 3.3 V and 5 V
CMOS-compatible interface to a microcontroller unit is provided. The products feature a
very low quiescent current to preserve battery charge during standby mode. Undervoltage
shutdown acts below 4 V in order to ensure the loads are driven when charge pump can
deliver sufficient power. Overvoltage clamp structure protects the devices effectively from
“ISO 7637-2:2004(E)” pulses (with the exception of load dump pulses, unclamped or
clamped above 40 V). At loss of ground the outputs are safely turned-off, current injected
into the outputs is less than 2 mA. At loss of VCC the outputs are also safely turned-off, but
special care must be taken when inductive loads are driven, since additional external
protection is required to absorb the demagnetization energy (refer to Chapter 6: Load
compatibility).
Reverse battery protection is provided in conjunction with external components for
monolithic standard high-side drivers, whilst hybrid high-side drivers are reverse battery
protected by self turn-on of output channels without the need of external components (refer
to Chapter 2: Reverse battery protection). Note that no protection features are operating
under reverse battery conditions.
M0-7 standard high-side drivers integrate advanced protective functions such as load
current limitation, overload active management by power limitation and overtemperature
shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or
disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin
delivers sophisticated diagnostic functions including:
Proportional load current sense
Supply voltage feedback
Chip temperature sense
Detection of overload
Short circuit to ground
Short to VCC and
Off-state open-load
A SenseEnable pin allows off-state diagnosis to be disabled when it is needed to send the
module in low power mode. Moreover, thanks to the sense enable functionality, it is possible
to share one common external sense resistor among several devices and so to manage a
MultiSense diagnostic bus.
a j r: x J” E H: M %
General items UM1922
12/196 UM1922 Rev 2
1.2 Application schematics – monolithic devices
Figure 1. Typical application schematics – monolithic devices
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UM1922 Rev 2 13/196
UM1922 General items
195
1.3 Application schematics – hybrid devices
Figure 2. Typical application schematics – hybrid devices
1.4 Application schematics description of external
components
Pull-up: this resistor is optional and is needed when open-load in off state diagnostic is
required. It has to be dimensioned to pull up the output above the maximum open-load
in off state detection voltage (VOL max) and make sure that the output voltage stays
below the minimum open-load in off state detection voltage (VOL min) in case the load is
connected (for details refer to Section 7.2.11: Open load detection in off-state).
R5//CEXT
: a low pass-filter, as an RC filter, can be placed across the RSENSE resistor to
suppress HF noise. The time constant of this filter (= RC) should be long enough to
effectively suppress the noise and short enough to allow MultiSense signal stabilization
taking into account multiplexer delay and settling times. C2 should be placed close to
the MCU's A/D input. Also, the ground connection for C2 should be at the same
potential as the ground of the A/D reference. The filter resistor R5 is also used to limit
the A/D's input pin current (for details refer to Section 7.2.13: MultiSense low pass
filtering).
R6//CEXT
: this low pass-filter and ADC input connection is optional and is
recommended for monolithic devices, when a precise chip temperature or supply
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14/196 UM1922 Rev 2
voltage feedback reading is required. For dimensioning the same recommendations
apply as for R5//C2.
C4: it is recommended to place a ceramic capacitor on each output to dissipate energy
of high frequency, high voltage transients, in particular ESD transient pulses. A 100 V
ceramic capacitor generally has sufficient voltage capability. The device ESD
robustness of each pin is rated in Absolute Maximum Rating chapter of the datasheet
(for details refer to Chapter 11: Usage in “H-Bridge” configurations).
C5: C5 capacitor helps to suppress voltage transients that originate from other
actuators connected in parallel and sharing the same battery line. This capacitor will be
capable to suppress only low energetic short transient pulses. The device itself is rated
to sustain ISO 7637-2:2004(E) transient test pulses 1-4 up to test level IV according to
class C. Other methods are needed to protect the module from higher energy
transients, such as load dump.
Moreover C5 capacitor helps to suppress HF noise at the VCC pin that is generated by
the high-side driver device itself. The noise can originate from the charge pump
circuitry or from the switching slopes of PWMed outputs.
Using a 100 nF low ESR ceramic capacitor mounted close to device VCC and GND
terminals the devices meet CISPR25 Class 5 requirements measured in conducted
emission voltage method in DC, as well as in PWM, operation.
Finally, during a loss of VCC condition, the C5 capacitor supplies load current for the
demagnetization of inductive loads.
RSENSE: RSENSE resistor will convert the MultiSense output current, which is a copy
proportional to the load current, into a voltage which can be read by the A/D Converter
of the Microcontroller. The RSENSE should be dimensioned to ensure proper resolution
range and granularity to monitor nominal current as well as detecting open load or
overload events. Typical values of RSENSE are in the range from 1 k to 2.7 k, in
order to generate typically 1 V – 2 V sense voltage at nominal load current. RSENSE
selection must also take into account maximum power dissipation and maximum
current injection during reverse battery conditions and ISO 7637-2:2004(E) and ISO
7637-2:2011(E) pulse 1 transients. Refer to Section 7.2.6: Considerations on
MultiSense resistor choice for current monitorfor details on RSENSE dimensioning rules.
R1-R5: R1-R5 serial resistors are needed on digital inputs in order to limit the current in
the input structures as well as in the microcontroller output structures to a safe value
during transient and reverse battery conditions. A proper value for such resistors is
15 k.
No low ohmic impedance paths to GND such as pull down transistors or capacitors
shall be connected directly to the digital inputs. In such conditions, device ground shift
may trigger intrinsic parasitic structures and an unlimited, destructive current path from
VCC to the digital input will be formed.
RGND//DGND: a reverse polarity protection network between device ground and module
ground is needed for monolithic devices. The diode prevents unlimited destructive
current flow through the VCC - GND clamping structure in case of reverse polarity
connection. RGND paralleled to DGND avoids device ground dropping to negative
voltage during turn-off of inductive loads. Typical values range from 1 k to 4.7 k,
higher values reduce power dissipation under reverse battery condition (for details
refer to Chapter 2: Reverse battery protection).
Hybrid devices (for classification of Hybrid and Monolithic HSDs please refer to
Section 5.1: Classification of M0-7 HSDs) do not need GND network (please refer to
Figure 2) in case pulses belonging to ISO 7637-2:2004(E) standard are requested to
be passed. A resistive path in the GND connection of Hybrid devices with RGND > 300,
UM1922 Rev 2 15/196
UM1922 General items
195
would not properly activate the self-turn on of the Power MOS in case of reverse
battery (the load current would circulate into the Body Diode instead). RON in reverse
battery conditions with self-turn on is indicated in the Hybrid devices' datasheets. In
case ISO 7637-2:2011(E) is requested to be fulfilled the same schematic applies
except in case ISO pulses 1 level IV and 2a level IV are requested to be passed. In this
case a GND network must be implemented (for details, please refer to Section 3.6.2:
Dimensioning of the GND network to pass the ISO n.1 and 2a level IV (2011 edition)).
Reverse battery protection UM1922
16/196 UM1922 Rev 2
2 Reverse battery protection
2.1 Introduction
A universal problem in automotive environment is the threat of damage when an end user
inverts the battery polarity.
Users of battery powered equipment expect safeguards to prevent damage to the internal
electronics in the event of reverse battery installation. These safeguards can be either
mechanical (use of special connectors) or electronic. In that case battery powered
equipment designers and manufacturers must ensure that any reverse current flow and
reverse bias voltage is low enough to prevent damage to the equipment’s internal
electronics. To provide these electronic safeguards, different concepts applying passive or
active reverse polarity protection are possible and described in this chapter.
Depending on the type of device (monolithic or hybrid, for classification please refer to
Section 5.1: Classification of M0-7 HSDs), a specific protection must be implemented in
order not to exceed the device’s reverse capability:
Monolithic HSDs: the reverse battery protection needs to be inserted according to the
instructions suggested in this chapter. In particular, if the reverse polarity protection is
installed on device GND connection, the device will conduct through the body diode of
the power MOSFET with the current limited by the external load. Since no device
intrinsic protection schemes are active in reverse condition, special care must be taken
on total Power Dissipation.
Hybrid HSDs: in contrast to monolithic devices, all hybrids VIPower HSD do not need
any external components to protect the internal logic in case of a reverse battery
condition. The protection is provided by internal structure. Moreover, due to the fact
that the output MOSFET turns on even in reverse battery mode and thus providing the
same low ohmic path as in regular operation condition, no additional power dissipation
has to be considered. Even more: if e.g. a diode without any parallel resistor is
connected to GND of a hybrid HSD the output MOSFET is unable to turn on and thus
the unique feature of the driver is disabled.
2.2 Reverse battery protection of monolithic HSDs
Reverse battery protection schemes basically can be grouped in the following categories:
Active or passive reverse polarity protection
Reverse polarity protection on supply line (VCC terminal) or on GND line (GND
terminal)
Table 1. Reverse battery protection concepts
Reverse battery
protection concept Chapter Active/passive VCC terminal/
GND terminal
Conduction through
output stage
Schottky Diode 2.2.1 Passive VCC No
Diode || Resistor 2.2.2 Passive GND Yes
N-channel MOSEFT 2.2.3 Active GND Yes
UM1922 Rev 2 17/196
UM1922 Reverse battery protection
195
2.2.1 Schottky diode
When the battery is installed backwards, the Schottky diode is reverse–biased and only the
rated leakage current IR flows. With respect to a standard diode, the Schottky diode has the
advantage of a very low voltage drop in forward direction, hence power dissipation is
reduced. However, the disadvantage of using a Schottky diode is, that it is typically more
expensive than a standard diode.
Below reported, there is the suggested procedure to choose properly the right device. The
following parameters will constitute the selection criteria:
The average current used by the device, electronic module, load to be reverse battery
protected. Failure scenarios, such as an output shorted to GND (load short circuit)
have to be considered as well.
The maximum repetitive peak reverses voltage VRRM
The maximum ambient temperature Tamb
The following inequality must apply in all cases:
where:
IF(AV) = maximum average forward current
IF(RMS) = RMS forward current
Rth = thermal resistance (Junction to ambient) for the device and mounting in use
rd = small signal diode resistance
VTO are depending on the special characteristics of the diode.
One important thing to take into account is the peak reverse voltage limit of the Schottky
diode: VRRM = 100 V seems a good compromise with respect to the “ISO 7637-2:2004(E)”
pulse 1 Test levels IV. In case compliance with “ISO 7637-2:2011(E)” pulse 1 Test level IV is
required, VRRM must be 150 V. The main drawback of this method is the power dissipation
in the Schottky diode in forward direction. Depending on the type of package, the Rth and
the ambient temperature, the maximum affordable power dissipation in the Schottky diode is
typically in the range of 1 W. In consequence the maximum average forward current is
limited to the range of 1 A – 2 A.
The direct diode reverse battery protection can also be replaced with a simple fuse.
However, upon battery inversion this fuse will blow and the module will need to be replaced
or repaired.
p-channel MOSFET 2.2.4 Active VCC No
Reverse FET 2.2.5 Active VCC No
Table 1. Reverse battery protection concepts (continued)
Reverse battery
protection concept Chapter Active/passive VCC terminal/
GND terminal
Conduction through
output stage
Tamb Rth P+TjMAX
PV
TO IFAV
rd I2FRMS
+=
Reverse battery protection UM1922
18/196 UM1922 Rev 2
2.2.2 Diode + resistor in GND line
The reverse battery protection is applied to the GND terminal of the driver. This kind of
protection leaves the output power stage in reverse battery condition conductive through its
body diode. The current is limited by the external load. Since no thermal protection works in
reverse condition, special attention must be paid to the total power dissipation in the device.
During the reverse battery event, the peak junction temperature shall remain safely below
the maximum allowed junction temperature (TTSD_max). Considering a voltage drop on the
internal body diode of VF_max = 0.7 V, the resulting power dissipation in the high-side driver
per output channel is PD = 0.7 V * ILOAD. Zthj-a diagrams reported in HSD datasheets
support the user to calculate the maximum affordable load current for a given PCB layout.
Note that the intrinsic diode between MultiSense pin and VCC pin will be forward biased in
reverse battery condition. The current is limited by the external sense resistor. A 1 k sense
resistor will dissipate 250 mW about.
For what concerns the GND path of the device, the integrated VCC - GND clamping
protection, which circuit behaves like a Zener diode will be forward biased in reverse battery
condition. The power dissipation in the GND resistor therefore is determined by
PD = (-VBAT_rev - 0.3 V)² / RGND. A 1 k GND resistor will dissipate 250 mW about.
The following figure provides an overview about the resulting voltage levels on pins in a
typical application schematic during reverse battery condition.
Figure 3. Voltage levels during reverse battery (diode + resistor protection)
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UM1922 Reverse battery protection
195
GND voltage on device is dropping to the reverse battery voltage plus the forward voltage of
the integrated VCC to GND clamping circuit. Voltage on MultiSense pin is dropping to the
reverse battery voltage plus the forward voltage across the internal ESD protection diode.
The maximum allowed DC output current on MultiSense pin (ISENSE) in reverse battery
conditions is limited to 20 mA. Therefore the Sense Resistor RSENSE must be chosen
accordingly:
For generic RSENSE dimensioning rules, please refer to Chapter 7: MultiSense - analogue
current sense .
Due to the clamping voltage of the integrated ESD protection diodes on logic pins
(FaultRST, INx, SELx, SEn) the voltage on those pins is dropping to -10 V about. Therefore a
serial resistor is needed to limit the current and protect the I/O structure on microcontroller
port pins and the high-side driver´s logic pins.
Furthermore the ground network shall ensure the device will work properly when driving
inductive loads and/or is not being damaged when submitted to ISO 7637-2:2011(E) pulse 1
test level IV pulses.
The diode at the GND terminal blocks the current through the forward biased internal
substrate diode of the HSD during reverse battery condition.
A resistor connected in parallel to the diode is recommended in case the device drives a
high inductive load with a demagnetization time longer than tD_STBY (delay time for the
device to reach standby mode after the last logic pin (INx, FaultRST, SEn and SELx) is set
low). The purpose of this resistor is to suppress a negative voltage on the GND pin during
the standby mode if the demagnetization phase is still ongoing. Without this resistor, the low
supply current in standby mode (Isoff = 0.5 µA max at 85 °C) allows the GND pin to be pulled
negative by the demagnetization voltage on the output (~ (VCC - VCLAMP) ~
(13.5 V – 46 V) = -32.5 V) via an internal pull-down resistor (~90 k) on the output (see
Figure 4). If the negative ground shift exceeds the input high level threshold, the device
leaves the standby mode and tends to turn on. The GND pin is immediately pulled high
Table 2. Reverse battery-voltages on pins (VND7040AJ)
Pin voltages [V] VND7xxxAJ Pin voltages [V] microcontroller
VCC -16 VDD -0.4
VFR -9.7 VFR_µC -0.7
VIN0 -10 VIN0_µC -0.7
VIN1 -10 VIN1_µC -0.7
VSEn -10 VSEn_µC -0.7
VSEL0 -10 VSEL0_µC -0.7
VSEL1 -10 VSEL1_µC -0.7
VCS -15.3 VCS_µC -0.7
VOUT0 -15.3
VOUT1 -15.3
VGND -15.4
RSENSE VBAT_reverse 0.7V0.02A765=
Reverse battery protection UM1922
20/196 UM1922 Rev 2
(~ 600 mV) by the increased supply current ISON so that the standby mode will be activated
again after tD_STBY
. As a result, we could see short negative peaks on the GND pin with
period of tD_STBY during the whole demagnetization phase. These peaks are not long
enough to activate the HSD output, which means the device works safely even without the
GND resistor. However, this resistor is still needed in order to suppress the described
parasitic oscillations (if TDEMAG > tD_STBY).
The ground network can be safely shared amongst several different high-side drivers,
provided they are supplied from the same supply rail. Sharing the ground network is even
possible among different HSDs, when they are supplied from different supply rails. In this
case however, special precautionary measures must be applied (for details refer to
Section 8.3: Paralleling of GND protection network). The presence of the ground network
will produce a shift (~ 600 mV) in the input threshold. This shift will not vary, if more than one
HSD share the same diode/resistor. The diode at the GND terminal allows the high-side
driver to clamp positive ISO pulses above 46 V (the typical clamping voltage of the HSD).
Negative ISO pulses still pass GND and logic terminals. The diode should withstand
clamped ISO currents in case of positive ISO pulses and reverse voltages in case of
negative ISO pulses.
Dimensioning of the GND diode
The most severe positive “ISO 7637-2:2004(E)” pulse we have to consider is test pulse 2a
at level IV (50 V during 50 µs). This voltage is considered on top of the nominal supply
voltage of 13.5 V – so the total voltage is 63.5 V. The M0-7 HSDs have a clamping voltage
VCLAMP = 46 V typical. In case of a typical device the remaining voltage is
63.5 V - 46 V - 0.7 V = 16.8 V. The ISO pulse generator output impedance is 2 . With this
the resulting peak current through the diode is 8.4 A for duration of 50 µs.
The most severe negative “ISO 7637-2:2004(E)” pulse we have to consider is test pulse 1 at
level IV (-100 V at 1 ms). This pulse is directly transferred to the GND pin via the internal
clamping. So, the maximum peak reverse voltage of the diode should be at least 100 V. In
case “ISO 7637-2:2011(E)” pulse 1 test level IV compliance is required, the maximum peak
reverse voltage of the diode should be at least 150 V.
Note: The Diode will work in avalanche mode if the pulse level is above the rated reverse voltage.
Conclusion:
The dimensioning the GND diode must fulfill the following:
Maximum peak forward current: 8.4 A for 50 µs for ISO 7637-2:2004(E)
Maximum reverse voltage: -100 V for ISO 7637-2:2004(E) resp. -150 V
for ISO 7637-2:2011(E)
Note: As seen from above explanation, the HSD with a diode protection at the GND pin doesn’t
clamp negative ISO pulses on the supply line. Therefore an appropriate serial protection
resistor should be used between microcontroller and HSD (typically 15 k). The resistor
value should be calculated according to the maximum injected current to I/O pin of the used
microcontroller and to the maximum Input sink current of the HSD.
Diode parameters can be lower if an external clamping circuitry is used (e.g. HSD module is
supplied from a protected power supply line).
DEMAG D STBV ‘VDEMAG‘ ‘ '0 \V \
UM1922 Rev 2 21/196
UM1922 Reverse battery protection
195
Dimensioning of the GND resistor
The GND resistor is recommended in case of a high inductive load. To determine if the
resistor is needed or not, we need to know the demagnetization time (TDEMAG). The resistor
is recommended if TDEMAG is higher than the standby delay time (tD_STBY).
A typical tD_STBY value of 350 µs is considered in this comparison.
TDEMAG can be determined by either measurement (Figure 6, RGND = 4.7 k, Load: Relay
270 mH/ 90 alternatively Bulb on a typical wire harness with 6 µH stray inductance) or
calculation, using Equation 1 and Equation 2.
Figure 4. Negative GND shift (TDEMAG > tD_STBY)
Equation 1
Equation 2
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Reverse battery protection UM1922
22/196 UM1922 Rev 2
Figure 5. GND resistor requirements (inductive load)–test setup
Figure 6. Measurement example (tDEMAG > tD_STBY) without GND resistor
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UM1922 Rev 2 23/196
UM1922 Reverse battery protection
195
Figure 7. Measurement example (tDEMAG > tD_STBY) with 4.7 k GND resistor
The experimental trials have shown:
The operation with high inductivity load (TDEMAG > tD_STBY) is correct even without the
GND resistor (only the diode), knowing that the device GND pin oscillation with period
of tD_STBY may be present (see Figure 6)
In all cases, the 10 k resistor was enough to reduce the GND shift below the logic
input activation level (so eliminate the oscillations)
The 4.7 k appears to be the best compromise between the GND shift safety and
power dissipation during static reverse battery condition (~50 mW)
The value of the resistor should be low enough to be sure that the negative voltage at the
GND pin is suppressed as much as necessary to keep the device off. This means the VGND
should be kept above -1.3 V.
The minimum resistor value is determined by the maximum DC reverse ground pin current
of the HSD in reverse battery condition:
In order to keep the power dissipation on the resistor during reverse battery condition as low
as possible, it is recommended to select the resistor value close to the maximum value
(4.7 k).
RGND
VBAT reverse
IGND reversemax
------------------------------------------------16V
200mA
------------------- 80==
Reverse battery protection UM1922
24/196 UM1922 Rev 2
Summary – dimensioning of the resistor
Resistor recommended if: TDEMAG > tD_STBY
Resistance: 4.7 k (or lower)
Voltage capability: min. 150 V (ISO 7637:2-2011(E) pulse 1 at level IV)
min. 100 V (ISO 7637:2-2004(E) pulse 1 at level IV)
Power dissipation (reverse battery): min. 50 mW (4.7 k)
Example with relay coil:
In case of a relay coil connected supposing following conditions:
Load resistance: RLOAD = 90
Wiring inductances: L = 270 mH
Initial current I0: 0.14 A
Applying Equation 2, yields a TDEMAG = 1.0 ms > tD_STBY
Example with resistive load with long wire harness:
In case of a resistive load connected via long wires, supposing following conditions:
Load resistance: RLOAD = 5
Wiring inductances: L = 5µH (in case of very long cabling)
Initial current I0: 2.7 A
Applying Equation 2, yields a TDEMAG = 0.4 µs << tD_STBY_min
Example with short circuit with long wire harness:
In case of a resistive load connected via long wires, supposing following conditions:
Load resistance: RLOAD = 100
Wiring inductances: L = 5 µH (in case of very long cabling)
Initial current I0: 130 A (ILIMH_max - lowest ohmic monolithic HSD
VN7010AJ)
Applying Equation 2, yields a TDEMAG = 18 µs << tD_STBY_min
This demagnetization phase lasts very short time in comparison to the standby delay time
so, in case of not highly inductive loads, no GND resistor is needed in parallel to the GND
diode.
2.2.3 N-channel MOSFET in GND line
In comparison to the solutions described in the previous chapters, reverse polarity
protection with MOSFETs offer two main advantages: lower power losses and minimal
voltage drop. Generally the MOSFET´s body diode is oriented in the direction of normal
current flow. When the battery is installed incorrectly, the N-MOS (P-MOS) FET’s gate
voltage is low (high), preventing it from turning ON.
When the battery is properly installed and the portable equipment is powered, the N-MOS
(P-MOS) FET’s gate voltage is taken high (low) and its channel shorts out the diode.
UM1922 Rev 2 25/196
UM1922 Reverse battery protection
195
A voltage drop of RDS(on) × ISON is seen in the ground return path when using the N-MOS
FET. A voltage drop of RDS(on) × ILOAD is seen in the power path when using the PMOS
FET. In the past, the primary disadvantage of these circuits has been the high cost of low
RDS(on), low-threshold voltage FETs. However, advances in semiconductor processing have
resulted in FETs that provide minimal drops in small packages.
The N-channel MOSFET is connected in such a way, that its gate is driven directly by the
battery voltage and its drain is connected to ground. In normal condition it is ON whilst a
reverse battery event switches it OFF (because VGS 0) and protects the HSD.
In Figure 8 is reported a generic schematic with N-channel MOSFET configuration. In this
case, like for the solution with Diode || Resistor network in the GND line, the HSD´s output
stage body diode is forward biased and therefore is conducting during the reverse battery.
The current is limited by the external load. Since no thermal protection works in reverse
condition, special care must be taken on the total power dissipation in the device. During the
reverse battery event, the peak junction temperature shall remain safely below the
maximum allowed junction temperature (TTSD_max). Considering a voltage drop on the
internal body diode of VF_max = 0.7 V, the resulting power dissipation in the HSD per output
channel is PD = 0.7 V · ILOAD.
Zthj-a diagrams reported in HSD datasheets help the user to calculate the maximum
affordable load current for a given PCB layout.
Reverse battery protection UM1922
26/196 UM1922 Rev 2
Figure 8. Generic schematic and test setup with N-channel MOSFET in GND line
Measured values (VND7020AJ)
Table 3 reports the measurement results on VND7020AJ test vehicle: GND voltage on
device is dropping to the reverse battery voltage plus the forward voltage of the integrated
VCC to GND clamping circuit (substrate diode). Voltage on MultiSense pin is dropping to the
reverse battery voltage plus the forward voltage across the internal ESD protection diode.
The maximum allowed DC output current on MultiSense pin (ISENSE) in reverse battery
conditions is limited to 20 mA. Therefore the sense resistor RSENSE must be chosen
accordingly:
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Table 3. Static reverse battery - voltages on pins
Reverse battery
(VCC = -16 V)
Normal operation
(standby mode)
Normal operation
(out0=on, out1 = off)
Normal operation
(out0=on, out1 = on)
VCC [V] -15.99 14 13.97 13.95
VGND [V] -15.37 0 0.000028 0.000042
VG_Q1 [V] -15.92 13.97 13.95 13.94
IR2 [µA] -4.1 0.2 0.2 0.2
m-m
UM1922 Rev 2 27/196
UM1922 Reverse battery protection
195
RSENSE > (|VBAT_reverse – 0.7 V|) / 0.02 A = 765
For generic RSENSE dimensioning rules, please refer to Chapter 7: MultiSense - analogue
current sense .
Due to the clamping voltage of the integrated ESD protection diodes on logic pins
(FaultRST, INx, SELx, SEn) the voltage on those pins is dropping to -10 V about. Therefore a
serial resistor is needed to limit the current and protect the I/O structure on microcontroller
port pins and the high-side driver´s logic pins. The gate voltage of the N-channel MOSFET
is pulled down to the reverse battery voltage, ensuring the MOSFET is fully off. In normal
operation only the leakage current of ZD1 Zener diode is flowing through R2 to GND. In
order to minimize this current even at higher supply voltages, a diode with higher Zener
voltage (i.e. 18 V) might be chosen. The Zener voltage should be anyway always lower than
the maximum rated Gate Source Voltage VGS of the N-channel MOSFET.
The resistor R2 limits the current through the Zener diode at supply voltages higher than the
Zener voltage and limits the charging/discharging current of the gate. In addition the resistor
R2 together with the gate capacitance of the N-channel MOSFET determines the turn-off
time when exposed to fast negative transients or abrupt reverse polarity according to the
LV 124: 2009-10 standard. 15 k as demonstrated by the experiment reported below
appears to be a good compromise between minimizing the charging/discharging current
and ensuring a fast turn-off time.
A capacitor might be placed between Gate and Source of the N-channel MOSFET. The RC
filter composed by R2 and C can be dimensioned to be transparent against the fast negative
pulses ISO 7637-2:2004(E) pulse 1 test level IV, keeping the reverse polarity protection
circuitry switched on. The usage of such capacitor C is not recommended, when the system
must be compliant to ISO 7637-2:2011(E) pulse 1 test level IV. In this case in fact it is
needed that the pulse does not discharge through the HSD and the conducting N-channel
MOSFET as this might be destructive for the HSD.
Figure 9. MOSFET solution in GND – experiment VND7020AJ, ISOpulse 1 (-150V, 90 )
Figure 9 shows the example of a 100 V/100 m N-channel MOSFET in the schematics, as
for Figure 8, submitted to ISO 7637:2-2011(E) pulse 1 transients. In order to limit the current
in this experiment a 90 generator resistor was chosen. As long as the N-channel
MOSFET is still conducting during the negative pulse, the voltage on VCC pin (VBAT) is
clamped to minus one diode voltage due to the forward biased substrate diode of the HSD.
The N-channel MOSFET is turned off once the GND voltage begins to drop. This happens
within a few microseconds. The first current spike is due to the recharging of the VCC
Ibat
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28/196 UM1922 Rev 2
capacitor. As soon as the GND voltage drops to -100 V, the N-channel MOSFET starts to
conduct in avalanche until the pulse amplitude drops below its breakdown voltage
BVDSS = 100 V.
The breakdown voltage BVDSS of the N-channel MOSFET either should be higher than the
maximum negative transient peak voltage of ISO 7637:2-2011(E) or the energy capability of
the N-channel MOSFET in avalanche must be high enough to sustain the transient pulse
energy.
Figure 10. Reverse battery test VN7016AJ (13.5 V -4 V, 82 m, R2 = 15 k) as per
LV 124: 2009-10 standard
Figure 10 shows an example of an abrupt reverse battery test changing the polarity of the
battery supply from 13.5 V to -4 V within a few µs. The test setup used a 100 V/100 m
N-channel MOSFET with a gate resistor R2 = 15 k. The total line impedance is measured
with 82 m in line with the requirements of LV 124: 2009-10.
The N-channel MOSFET is able to turn-off within 10 µs about. During this time a relatively
high current will flow through the HSD substrate diode. The total energy dissipated in the
HSD is around 100 µJ, which is withstood by the M0-7 high-side driver family.
2.2.4 P-channel MOSFET in the VCC line
The P-channel MOSFET is connected in such a way that its Gate is connected to GND via a
resistor R2 and its drain to VCC pin, while the source acts as the reverse polarity protected
supply. In Figure 11 is reported a generic schematic with P-channel MOSFET configuration.
Compared to an N-channel MOSFET the device will be turned on by applying a negative
gate source voltage.
It is important to insert the transistor in the right direction, because the P-channel MOSFET
has as well an intrinsic anti parallel body diode which is in forward direction from drain to
source.
By referring the gate signal to the ground line, the device is fully turned on when the battery
is applied in the right polarity.
R2 = 15k
VCC - GND stress: ~0.1mJ
UM1922 Rev 2 29/196
UM1922 Reverse battery protection
195
Figure 11. Generic schematic and test setup with P-channel MOSFET in VCC line
As soon as the battery voltage is applied and for the first start up, the body diode of the
MOSFET will conduct, until the channel is switched on in parallel. The Zener diode will
clamp the Gate of the MOSFET to its Zener voltage in case of over voltage on the battery
track. In normal operation only the leakage current of ZD1 Zener Diode is flowing through
R2 to GND. In order to minimize this current even at higher supply voltages, a diode with
higher Zener voltage (i.e. 18 V) might be chosen, however it shall be dimensioned to ensure
the Zener voltage is always safely below the maximum rated gate source voltage VGS of the
P-channel MOSFET.
The resistor R2 limits the current through the Zener diode at supply voltages higher than the
Zener Voltage and limits the charging/discharging current of the gate. In addition the resistor
R2 together with the gate capacitance of the P-channel MOSFET determines the turn-off
time when exposed to fast negative transients or abrupt reverse polarity according to
LV 124: 2009-10 standard. 1 k as demonstrated by the experiment reported below
appears to be a good compromise between minimizing the charging/discharging current
and ensuring a fast turn-off time. Due to the fact, that the P-channel MOSFET will carry also
the load current, it needs to be a lower ohmic component compared to an N-channel
reverse polarity protection MOSFET in the GND line. In consequence it will have a higher
gate capacitance, hence longer turn-off times for identical gate resistance R2.
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Measured values (VND7020AJ)
Table 4 reports the measurement results on VND7020AJ test vehicle, according to the
schematic in Figure 11: VCC voltage on device is completely decoupled from the reverse
battery voltage. No negative voltage is present on MultiSense and on logic pins. By reverse
polarity, the MOSFET will be switched off, because the gate source voltage for this case will
be positive VGS > 0 (voltage drop over the Zener diode) and protects the HSD.
The same reverse polarity protection network can be shared among several HSD connected
to the battery.
A capacitor might be placed between gate and source of the P-channel MOSFET. The RC
filter composed by R2 and C can be dimensioned to be transparent against the fast negative
pulses ISO 7637-2:2004(E) pulse 1 test level IV, keeping the reverse polarity protection
circuitry switched ON. The usage of such capacitor C is not recommended, when the
system must be compliant to ISO 7637-2:2011(E) pulse 1 test level IV. In this case in fact it
is needed that the pulse does not discharge through the HSD and the conducting P-channel
MOSFET as this might be destructive for the HSD.
Figure 12. MOSFET solution in VCC – experiment VND7020AJ, ISOpulse 1
(-100 V, 90 )
Figure 12 shows the example of a 55 V/16 m P-channel MOSFET in the schematics as
per Figure 11 submitted to ISO 7637:2-2004(E) pulse 1 transients. In order to limit the
current in this experiment a 90 generator resistor was chosen. As long as the P-channel
Table 4. Static reverse battery - voltages on pins
Reverse battery
(VBAT = -16 V)
Normal operation
(standby mode)
Normal operation
(out0 = on, out1 = off)
Normal operation
(out0 = on, out1 = on)
VBAT [V] -16.02 14.02 14.00 13.98
VCC [V] 0 14.02 13.99 13.97
VG_Q1 [V] 0 0 0 0
IR2 [µA] 0 0 0 0
R2 = 1k
Gate capacitance discharging (~11nF)
MOSFET in avalanche
UM1922 Rev 2 31/196
UM1922 Reverse battery protection
195
MOSFET is still conducting during the negative pulse, the voltage on VCC pin (VBAT) is
clamped to minus one diode voltage due to the forward biased substrate diode of the HSD.
The P-channel MOSFET is turned off once the VBAT voltage begins to drop. This happens
within few tens of microseconds about. As soon as the VBAT voltage drops to -55 V, the
P-channel MOSFET starts to conduct in avalanche until the pulse amplitude drops below its
breakdown voltage BVDSS = 55 V.
The breakdown voltage BVDSS of the P-channel MOSFET either should be higher than the
maximum negative transient peak voltage of ISO 7637:2-2011(E) or the energy capability of
the P-channel MOSFET in avalanche must be high enough to sustain the transient pulse
energy.
Figure 13. Reverse battery test according to LV 124:2009-10: VN7016AJ (13.5 V at
-4 V, 82 m, R2 = 1k)
Figure 13 shows the example of an abrupt reverse battery test changing the polarity of the
battery supply from 13.5 V to -4 V within a few us. The test setup used a 55 V/16 m
P-channel MOSFET with a gate resistor R2 = 1 k. The total line impedance is measured
with 82 m in line with the requirements of LV 124:2009-10.
The P-channel MOSFET is able to turn-off within 20 µs about. During this time a relatively
high current will flow through the HSD substrate diode. The total energy dissipated in the
HSD is around 600 µJ, which is withstood by the M0-7 HSD family.
2.2.5 Dedicated ST Reverse FET solution
The VN5R003H-E is a device made using STMicroelectronics® VIPower® technology. It is
intended to provide reverse battery protection to an electronic module. This device, which
consists of an N-channel MOSFET and its driver circuit, has two power pins (drain and
source) and a control pin, IN (see Figure 14).
R2 = 1k
VCC - GND stress: ~0.6mJ
Reverse battery protection UM1922
32/196 UM1922 Rev 2
Figure 14. Reverse polarity protection – reverse FET protection
Note that a MOSFET has always an intrinsic anti parallel body diode. If the IN voltage
versus drain is negative the device is turned ON. The MOSFET is fully turned on when
applying the battery voltage and the IN pin goes negative versus drain. Due to the fact that
the Source is at high potential, the MOSFET is a high-side switch not referring to ground; a
charge pump circuit is needed to boost the gate voltage over the source voltage to turn the
MOSFET on.
During reverse polarity of the battery, no voltage will supply the gate of the MOSFET which
will automatically switch off. When IN is left open, device is in OFF state and behaves like a
power diode between source and drain pins. The power losses of an N-channel MOSFET
for a reverse battery protection are determined by the RDS(on) of the device and the load
current. The device is able to withstand an abrupt high load current value, typical of an
application where several HSDs are activated simultaneously, and loads like motors or
bulbs can have a transient current above the devices’ DC Current maximum rating. The
diagram reported in Figure 15 gives information about the safe operating area as well as the
maximum pulsed drain current the device is able to manage during normal operation.
The usage of VN5R003H-E for reverse polarity protection is not recommended, when the
system must be compliant to ISO 7637-2:2011(E) pulse 1 test level IV. In this case in fact it
is needed that the pulse does not discharge through the HSD and the conducting
VN5R003H-E device as this might be destructive for the HSD.
The VNR003H-E is robust against “ISO 7637-2 2004 rev E” pulses in the configuration with
IN pin grounded through a resistance R > 5 .
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UM1922 Reverse battery protection
195
Figure 15. Maximum current versus duration time of VN5R003H-E
Note: PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 mm, Copper
areas: minimum pad lay-out and 2 cm2.
Source of disirubances Equi men! ing protection GAPGI mm szs £17
Protection against battery transients UM1922
34/196 UM1922 Rev 2
3 Protection against battery transients
3.1 Introduction on automotive electrical hazards
The automotive environment is the source of many electrical hazards. These hazards, such
as electromagnetic interference, electrostatic discharges and other electrical disturbances
are generated by various accessories like ignition, relay contacts, alternator, injectors,
SMPS (i.e. HID front lights) and other accessories. Because electronic modules are
sensitive to electromagnetic disturbances (EMI), electrostatic discharges (ESD) and other
electrical disturbances, caution must be taken wherever electronic modules are used in the
automotive environment.
These hazards can occur directly in the wiring harness in case of conducted hazards, or be
applied indirectly to the electronic modules by radiation. These generated hazards can
impact the electronics in two ways - either on the data lines or on the supply rail wires,
depending on the environment.
Several standards have been produced to model the electrical hazards that are currently
found in automobiles. As a result, manufacturers and suppliers have to consider these
standards and have to add protection devices to their modules to fulfill the major obligations
imposed by these standards.
The chapter deals with the robustness of M0-L7 monolithic devices submitted to ISO7637-
2:2004 and ISO7637-2:2011 disturbances on the battery line and mounted in the typical
application scheme.
3.2 Source of hazard on automotive
3.2.1 Conducted hazards
These hazards occur directly in the cable harness. They are generated by inductive loads
like electro-valves, solenoids, alternators, etc.
The schematic in Figure 16 is a typical configuration
Figure 16. Conducted hazards
GAPszm IMMS
UM1922 Rev 2 35/196
UM1922 Protection against battery transients
195
These hazards are generated by high current switching like relay contact, high current MOS
or IGBT switches, ignition systems, etc. The electromagnetic field generated by these
circuits directly affects lines or modules near the source of the electromagnetic radiation.
The schematic diagram in Figure 17 indicates how electromagnetic radiation creates such
hazards as electromagnetic interference in electronic modules.
Figure 17. Radiated hazards
3.3 Propagation of electrical hazards on the supply rail
Transients that are generated on the supply rail range mainly concern ISO7637-2 and
ISO10605 standards.
The most energetic transients are those resulting from load-dump and jump start. But all
other hazards may affect the normal operation of electronic modules.
The load-dump is caused by the discharged battery being disconnected from the alternator
while the alternator is generating charging current. This transient can last 400 ms and the
equivalent generator internal resistance is specified as 0.5 minimum to 4 maximum.
According to the ISO 7637-2 standard, the “+100 spikes” are due to supply sudden
interruption of currents in a device connected in parallel with the DUT due to the inductance
of the wiring harness, while the “-150 V spikes” are due to a supply disconnection from
inductive loads.
This chapter deals with voltage transient pulses, detailed on the ISO 7637-2 standard.
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36/196 UM1922 Rev 2
Figure 18. Various surges occurring in the supply rail
3.4 Standard for the protection of automotive electronics
All the hazards indicated above are described by several standards bodies such as the
Society of Automobile Engineers (SAE), the Automotive Electronic Council (AEC) and the
International Standard Organization (ISO).
Since the ISO7637 are the most important automotive standards regarding electrical
hazards transient, this document mainly concerns the cases considering such standard:
Below the electrical characteristics of ISO 7637-2 editions 2004 and 2011;
Table 5. ISO 7637-2: 2004 (E)
ISO
7637-2:
2004(E)
Test
pulse
Test levels
Number of
pulses or test
times
Burst cycle/pulse repetition time
Delay and
impedance
III IV Min. Max.
1 -75 V -100 V 5000 pulses 0.5 s 5 s 2 ms, 10
2a +37 V +50 V 5000 pulses 0.2 s 5 s 50 µs, 2
3a -100 V -150 V 1 h 90 ms 100 ms 0.1 µs, 50
3b +75 V +100 V 1 h 90 ms 100 ms 0.1 µs, 50
4 -6 V -7 V 1 pulses 100 ms, 0.01
5b +65 V +87 V 1 pulses 400 ms, 2
UM1922 Rev 2 37/196
UM1922 Protection against battery transients
195
3.5 Basic application schematic to protect a M0-7 standard
monolithic high-side driver
The hardware design techniques used for an application will establish the baseline immunity
performance. The purpose of hardware techniques is to protect the device from
performance degradation or long-term reliability problems.
Below reported, the STM application proposal, for protecting monolithic HSDs under the
common stress event mentioned in the ISO 7637-2 editions 2004 and 2011.
To provide these electronic safeguards, manufacturers typically chose either a diode, or
resistor or capacitor for protecting both data-line and supply rails.
Components used to suppress or control transients, as well as their implementation details,
are described in the next paragraph, providing a basic description of how the most typically
used components are employed in low-cost designs for achieving the desired level of
transient immunity.
Components used to suppress or control transients can be grouped into two main
categories:
Components that shunt transient currents (voltage limiters)
Components that block transient currents (current limiters)
Note that depending on the rise time (frequency bandwidth) of the transient, a component
may function as either a shunt or a block. For instance, at a slow rise time (low frequency
bandwidth) an inductor will have little impedance (a shunt). At faster rise times (higher
frequency bandwidth), an inductor will have greater impedance (a block). As a result,
transient suppression components must be carefully selected for the optimal operating
conditions. The actual performance of the component in the application will depend on the
frequency-based characteristics of the component and the board layout.
Table 6. ISO 7637-2: 2011 (E)
Test
pulse(1)
Selected
test
level(2)
Test pulse severity level,
US(3) (4) Min. number
of pulses or
test times
Burst cycle/pulse repetition
time
IV III I/II Min. Max.
1 -150 V -112 V -75 500 pulses 0.5 s (5)
2a +112 V +55 V +37 500 pulses 0.2 s 5 s
2b +10 V +10 V +10 10 pulses 0.5 s 5 s
3a -220 V -165 V -112 1 h 90 ms 100 ms
3b +150 +112 V +75 1 h 90 ms 100 ms
1. Test pulse as in 5.6 paragraph of ISO 7637-2:2011(E) (see Appendix A References).
2. Values agreed between vehicle manufacturer and equipment supplier.
3. The amplitudes are the values of US as defined for each test pulse in 5.6 paragraph of ISO 7637-2:2011(E) (see Appendix
A References).
4. The former levels I and II are revised because they did ensure sufficient immunity in subsequent road vehicles’ design.
5. The maximum pulse repetition time shall be chosen so that it is the minimum time for the DUT to be correctly initialized
before the application of the next pulse and shall be 0.5 s.
Protection against battery transients UM1922
38/196 UM1922 Rev 2
Resistors
Series resistance between two nodes can provide inexpensive and effective transient
protection blocking or limiting transients with frequency-independent resistance. Resistance
can be used to create low-pass filters and to decouple power domains. Series resistance is
primarily suited to protecting digital or analog signals that carry low currents and can accept
a modest voltage drop (across the series resistance).
Capacitors
Capacitors are used in a variety of transient protection roles. They can be used to filter the
high frequency pulses produced by an ESD event. They also provide switching current to
ICs and serve as energy storage bins that limit voltage variation.
In either role, the capacitor can be used to effectively shunt fast transients of limited energy,
such as ESD. Important characteristics to consider, when selecting capacitors, are the
maximum DC voltage rating, parasitic inductance, parasitic resistance, and over-voltage
failure mechanism.
3.5.1 Components dimensioning
Because the Reverse Battery event, the device needs to be protected by an external diode
plus a resistor network (in case of inductive loads) connected in series to the ground pin. In
this chapter, the ground network is dimensioned referring to the ISO7637-2 edition 2011 test
pulse 1 and 2.
Due to the presence of such protection network, the Negative ISO pulse 1 level IV (-150 V at
1 ms) is directly transferred to the GND pin via the internal clamping. Then, the HSD with a
diode protection at the GND pin does not clamp negative ISO pulses on the supply line.
Moreover the internal parasitic structures of I/O pins, link these pins directly to VBAT and
then to -150 V (see Figure 19). Therefore an appropriate serial protection resistor should be
used between microcontroller and HSD in order to limit the current injected into these pins.
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UM1922 Rev 2 39/196
UM1922 Protection against battery transients
195
Figure 19. Internal structures involved during application of ISO 7637-2 pulse 1 in a monolithic
HSD and indication of pin voltages
Besides, since the device input may be driven independently of the microcontroller by a
separate HW, which is supplied directly from battery, it’s mandatory to decouple the signal
coming from the microcontroller to the one coming from the limp home circuitry, in order to
avoid any backward supply of one circuit versus the other one. The decoupling is ensured
by a signal diode, placed in series to the Limp Home path connected to the device input.
Dimensioning of the series resistors on I/O line
The resistor value should be calculated according to the maximum injected current to I/O pin
of the used microcontroller. That value can be assumed about 10 mA so that, the resistors
value should be at least 15 k (150 V/10 mA):
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The basic application schematic has been validated in order to be reliable with the following
stress test, based the ISO7637-2 standard edition 2004 and 2011, in different operative
conditions:
ISO n1 (2 msec/10 , 5 K pulses);
Class C must be complied (full operational after each pulse).
ISO n2a (50 µsec/2 , 5 K pulses);
Class C must be complied (full operational after each pulse).
ISO n3a (0.1 µsec/50 , 1h);
Class B must be complied (full operational even during pulses exposure)
ISO n3b (0.1 µsec/50 , 1h);
Class B must be complied (full operational even during pulses exposure)
Figure 20. Basic test setup for ISO 7637-2 pulses applied to VND7020AJ
Below reported the operative conditions (given for VND7020AJ):
Device in OFF state and output in open load
Device in OFF state with OUTs in short circuit to GND
Device in ON state (IN0/IN1 high) and output in open load
Device in ON state (IN0/IN1 high) driving 3 resistive load on each OUT
Device in Limp Home state (IN0/IN1 pulled-up by 2.7 k + Diode to VCC) and output in
OL.
After test exposure device results are given in the Table 7 (here the most severe pulses are
reported):
UM1922 Rev 2 41/196
UM1922 Protection against battery transients
195
Moreover M0-7 Monolithic HSDs pass the load dump clamped pulse test (class C according
to Table 7 criteria) relevant to the standard ISO-7637-2:2004(E) (5b pulse with 40 V
centralized load dump suppressor) as well as the standard ISO 16750-2:2010 (E) (pulse
with 35 V centralized load dump suppressor).
3.6 Component dimensioning for hybrid devices
Differently from monolithic devices, the Hybrids do not need the external reverse battery
protection network since they have an embedded protection formed by an anti-parallel
Zener diode which prevents the signal clamp activation (refer to Figure 5). Moreover the
reverse battery event enables the self turn-on of output channels. For this reason, during the
ISO transients, the parasitic structures of I/O pins are softly triggered with no high current
flowing through them. Nevertheless, as precaution, a serial protection resistance is
suggested between microcontroller and logic pins to limit the current flowing. Hybrid devices
are fully compliant with the tests level specified in the ISO 7637-2: 2004 (see the relevant
table for more details).
Table 7. ISO 7637-2 2004 and 2011 tests and results on monolithic HSDs
ISO
7637-2
TEST PULSE
1
Level III
1
Level IV
2a
Level III
2a
Level IV(1)
3a
Level III
3a
Level IV
3b
Level III
3b
Level IV
2004 Class C Class C Class C Class C Class B Class B Class B Class B
2011 Class C Class C Class C Class C or E(1) Class B Class B Class B Class B
Class C: full operational after each pulse
Class B: full operational even during pulses exposure
Class E: One or more functions of the device do not perform as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device
1. The results on pulse ISO7637-2 2011 2a level IV depend mainly on load status and condition (open load, nominal load,
shorted load, resistive load, inductive load, capacitive load). Lower ohmic loads with low inductive contribution help to
increase the sustainable peak voltage for the device reaching Class C compliance. Tests performed on VND7020AJ, for
example, give as result class C in the condition ON state with a resistive load equivalent to the nominal one on each output
(see Figure 20); instead they give class E with Outputs in open load.
Protection against battery transients UM1922
42/196 UM1922 Rev 2
Figure 21. Internal structures involved during application of ISO 7637-2 (2004) pulse 1 in Hybrid
HSD and indication of pin voltages
Anyway, to be compliant with the ISO 7637-2 (edition 2011) test pulse 1 level IV and 2a level
IV, it is recommended to adopt a GND network in order to limit the current flowing through
the internal clamp structure.
Due to the presence of such protection network, the Negative ISO pulse 1 level IV (-150 V
for 2 ms) is transferred to the GND pin via the 20 V (typical clamp voltage). Then, logic pins
could go down to about -130 V (see Figure 22) and this would lead to a triggering of
parasitic structures on Signal pins. Therefore a suitable serial protection resistor between
microcontroller and HSD is mandatory to limit the current flowing through these pins.
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UM1922 Protection against battery transients
195
Figure 22. Internal structures involved during application of ISO 7637-2 (2011) pulse 1 in Hybrid
HSD and indication of pin voltages
Besides, since the device inputs may be driven independently from the microcontroller by a
separate HW (limp home feature), which is supplied directly from battery, it is mandatory to
decouple the signal coming from the microcontroller to the one coming from the Limp home
Circuitry, in order to avoid any backward supply of one circuit versus the other one. The
decoupling is ensured by a signal diode, placed in series to the Limp Home path connected
to the device input as shown in Figure 22.
3.6.1 Dimensioning of the series resistors on I/O line
The resistor value should be calculated according to the maximum injected current to I/O
pins of the used microcontroller. That value can be assumed equal to 10 mA so that, the
resistors value should be at least 13 k (130 V/10 mA); an input series resistor Ri = 15 k
can be considered a reasonable value.
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The recommended application schematic guarantees device operation according to the
below classes standard ISO7637-2 edition 2004 and 2011, as shown in the table below:
ISO n1 (2 ms/10 , 5K pulses)
Class C must be complied (full operational after each pulse).
ISO n2a (50 µs/2 , 5K pulses)
Class C must be complied (full operational after each pulse).
ISO n3a (0.1 µs/50 , 1h)
Class B must be complied (full operational even during pulses exposure)
ISO n3b (0.1 µs/50 , 1h)
Class B must be complied (full operational even during pulses exposure)
Figure 23. Basic test setup for ISO 7637-2 (2004) pulses applied to VN7004AH-E
3.6.2 Dimensioning of the GND network to pass the ISO n.1 and 2a level IV
(2011 edition)
As already mentioned, to pass the ISO n.1 (-150 V) and 2a (112 V) pulses a dedicated GND
network must be used.
The suggested basic solution is represented by a resistance R1 between device GND and
module GND
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UM1922 Protection against battery transients
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Figure 24. Recommended GND network for ISO 7637-2 (2011) level IV
A second solution with an additional branch in parallel (R2 + low drop diode D) depends on
specific considerations. The Table 8 gives a suggestion according to the Hybrid device type
and to the logic level of Input pin adopted.
The given suggestion, based on some experimental measures, take into account a
minimum high state input voltage on Regulator's side and the maximum voltage drop on
15 k I/O series resistance.
This yields a maximum allowed GND voltage on the device's GND network for 5 V and 3.3 V
system.
R1 must be chosen taking into account the two following limits:
Minimum value is chosen according to the signal clamp structure energy capability
and maximum power dissipation allowed inside the component (the lower is the
resistance value the higher is the Power dissipated during the pulses)
Maximum value is chosen to guarantee PowerMOS operation in full RON during
reverse battery and a GND shift that guarantees device properly driven ON even
in the worst case device limits (relevant parameters to be taken into account at
Table 8. GND network proposals for Hybrids HSDs
Device/VREG supply voltage
Single/double channels
VN7007AH
VN7004AH-E
VND7012AY
Quad channels VNQ7040AY
5V
Assumption: max allowed GND
Shift: 1.67 V
Only R1: 150 (value for each
driver)
R1 = 270 // (low drop D +
series resistor R2 = 47 ) (value
for each driver)
Vz(D) > 150 V
3.3 V
Assumption: max allowed GND
Shift: 0.33 V
Only R1: 33 (value for each
driver)
Only R1 = 18 (value for each
driver)
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device level are minimum VIH and maximum IGND(ON), values are both available in
datasheets). Experimental trials have led to fix the below range:
— 47 < R1 < 300 in case of 5 V Input logic level and single or double channel
Hybrid HSD.
— 18 < R1 < 300 in case of 3.3 V Input logic level and quad channel Hybrid
HSD
The simple reverse battery network (R1) is not always enough. In case of four channels
Hybrid HSD, a further D+R2 network is required in order to keep the GND pin voltage
drop as little as possible and avoid usage of big space demanding, low ohmic R1
component. R2 must be chosen according to the following limits:
Minimum value must limit the current flowing from VCC to GND through the
internal signal clamp structure during the ISO 2a pulse;
Maximum value according to maximum GND shift that guarantees device properly
driven ON even in the worst case device limits (relevant parameters to be taken
into account at device level are minimum VIH and maximum IGND(ON), both values
are available in datasheets). Experimental trials have led to suggest the below
range (assuming R1 = 270 and drop Voltage on diode of 0.4 V):
— 18 < R2 < 91
In Figure 25 a test setup is used in order to measure capability of M0-7 Hybrid device, in this
case the VN7004AH-E, to sustain ISO7637-2: (2011) pulses.
Figure 25. Basic Test setup for ISO 7637-2 (2011) pulses applied to VN7004AH-E
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UM1922 Protection against battery transients
195
Operative conditions (given for VN7004AH-E) are reported below:
Device in OFF state and output in open load
Device in OFF state with OUTs in short circuit to GND
Device in ON state (IN0/IN1 high) and output in open load
Device in ON state (IN0/IN1 high) driving 1.3 resistive load on each OUT
Device in Limp Home state (IN0/IN1 pulled-up by 2.7 K + Diode to VCC) and output in
OL.
Results are reported in Table 9:
Moreover M0-7 Hybrid HSDs pass the load dump clamped pulse test (class C according to
Table 7 criteria) relevant to the standard ISO-7637-2:2004(E) (5b pulse with 40 V
centralized load dump suppressor) as well as the standard ISO 16750-2:2010 (E) (pulse
with 35 V centralized load dump suppressor).
Table 9. ISO 7637-2 levels and results for Hybrid HSDs
ISO
7637-2 Test pulse
1 Level III 1 Level IV 2a Level III 2a Level IV 3a Level III 3a Level IV 3b Level III 3b Level IV
2004 Class C Class C Class C Class C Class B Class B Class B Class B
2011 Class C Class C or
E(1) Class C Class C or
E(2) Class B Class B Class B Class B
Class C: full operational after each pulse
Class B: full operational even during pulses exposure
Class E: One or more functions of the device do not perform as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device
1. By adding a series resistance (47 ) on GND pin, the device is able to pass level IV of ISO 7637-2 (2011) N 1 edition 2011.
2. Device is not able to pass the level IV of ISO 7637-2: 2011 in off-state with open-load condition.
In off-state condition with a minimum series resistance on the GND pin, the device is able to pass level ISO 1 and 2a, level
IV of ISO 7637-2: 2011.
Usage/handling of fault reset and standby UM1922
48/196 UM1922 Rev 2
4 Usage/handling of fault reset and standby
On top of M0-5 Enhanced HSDs functions and protections, in the new M0-7 devices
additional features have been implemented:
Latch-off functionality:
FaultRST pin = high:
The drivers will latch-off in case of power limitation or thermal shutdown. In order
to unlatch the channel(s), a low level pulse on FaultRST pin is required for
minimum duration of tLATCH_RST
. This time ensure the device clears the latch only
if required and not accidentally.
FaultRST pin = low or left open:
The drivers will behave like M0-5Enhanced devices (autorestart in case of power
limitation or thermal shutdown).
Standby mode (all generic input pins: INx, SEn, SELx, FaultRST low or open):
A permanent low level on FaultRST pin, SEn pin, SELx pin and all INx pins disables all
outputs and sets the devices in standby mode after elapse of standby mode blanking
time tD_STBY (open load diagnostic in off-state is disabled). Current consumption in this
state is ISTBY
. The device reverts to active mode (normal operation) as soon as at least
one of the generic inputs is set high.
FaultRST pin and Latch-off functionality are not present on specific device classes of the
M0-7 standard HSD family:
Devices listed in Table 10 operate in auto restart mode in case of power limitation or thermal
shutdown.
4.1 Latch-off functionality
The latch-off functionality is available when the FaultRST pin (logic input) is set high. This
pin is common for all device channels.
In case an overload occurs, the related channel is automatically latched-off at the first
intervention of either power limitation or thermal shutdown. The latch condition is indicated
by VSENSEH level on the related multi sense pin. Please refer to the truth tables to identify
the conditions to detect a latched channel through the VSENSEH level on the related multi
sense pin.
Table 10. M0-7 HSD devices not featuring latch-off functionality and FaultRST pin
Octapak SO-8
VN7004AH-E VN7040AS
VN7007AH VN7050AS
VN7140AS
UM1922 Rev 2 49/196
UM1922 Usage/handling of fault reset and standby
195
As indicated in Table 12 the VSENSEH failure flag is present on MultiSense pin of a latched
channel x, if the following conditions are met:
MultiSense is enabled (SEn = High)
The channel x is driven on through its input (INx = High)
The multiplexed MultiSense is mapped to channel x through appropriate SELx pin
settings
Note: Off-state diagnostic is provided on the MultiSense, if INx = Low.
Table 11. Truth table
Mode Conditions INXFR SEnSELxOUTx MultiSense Comments
Standby All logic inputs
low LL L L L Hi-Z Low quiescent
current consumption
Normal
Nominal load
connected:
Tj < TTSD
and
Tj < Tj_SD
LX
Refer to Table 12
L
Refer to
Table 12
HL H Outputs configured
for auto-restart
HH H Outputs configured
for latch-off
Overload
Overload or
short to GND
causing:
Tj > TTSD
and
Tj > Tj_SD
LX
Refer to Table 12
L
Refer to
Table 12
HL H
Output cycles with
temperature
hysteresis
H H L Outputs latch-off
Undervoltage VCC < VUSD
(falling) XX X X L
L
Hi-Z
Hi-Z
Re-start when
VCC > VUSD
+ VUSD hyst (rising)
OFF-state
diagnostics
Short to VCC LX
Refer to Table 12
H
Refer to
Table 12
Open-load L X H External pull-up
Negative output
voltage
Inductive loads
turn-off LX <0 V
Table 12. MultiSense multiplexer addressing for a dual channel device
SEnSEL1SEL0MUXchannel
MultiSense output
Normal mode Overload OFF-state diag. Negative
output
L X X Hi-Z
HLLChannel 0
diagnostic ISENSE = 1/K * IOUT0 VSENSE = VSENSEH VSENSE = VSENSEH 0
HLH
Channel 1
diagnostic ISENSE = 1/K * IOUT1 VSENSE = VSENSEH VSENSE = VSENSEH 0
HHLT
CHIP sense VSENSE = VSENSE_TC
HHHV
CC sense VSENSE = VSENSE_VCC
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50/196 UM1922 Rev 2
All latched channels can be restarted by setting the FaultRST pin low for a duration
corresponding to the maximum tLATCH_RST (this parameter is given in the datasheet)
A graphical explanation of the latch-off functionality can be seen in Figure 26, Figure 27 and
Figure 28:
Figure 26. Latch functionality - behavior in hard short circuit condition (Tjunction << TTSD)
Figure 27. Latch functionality - behavior in hard short circuit condition (TR < Tjunction < TTSD)
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UM1922 Usage/handling of fault reset and standby
195
Figure 28. Latch functionality - behavior in hard short circuit condition (autorestart mode and
latch-off)
4.2 Standby mode
The standby mode is available when the FaultRST pin, SEn pin, SELx pin and all INx pins
are set low or open and kept in this condition for a duration corresponding to the maximum
tD_STBY
. This time, tD_STBY
, has been introduced in order to avoid entering the standby
condition in case all generic input pins are low during a commutation, so no accidental
standby can occur (see Figure 29). In standby condition the supply current drops down to
0.5 µA (max at 85 °C).
As soon as the device enters the standby mode, all diagnostic latches are reset. This is also
caused by the fact that the FaultRST pin is set low for a time tD_STBY > tLATCH_RST
.
The device exits the standby condition as soon as anyone of FaultRST pin, SEn pin, SELx
pin or one of the INx pins is set high.
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Figure 29. Standby mode activation
The device leaves the Standby mode when any of the above mentioned pins is set high (see
Figure 30).
Figure 30. Standby state diagram
4.3 Flexible blanking time (fault reset management)
On one hand the use of the latch-off functionality provides significant benefits to the
application in terms of safety and reliability due to the very fast reaction and protection
against hazardous conditions induced by heavy overload or short circuit events. On the
other hand it requires from the user a proper selection of the suitable high-side driver for a
given load, in example through load compatibility studies (refer to Chapter 6: Load
compatibility). Concretely, the latch-off functionality might interfere with the load, in case it
has an inrush characteristic as for example an incandescent bulb, a DC motor or a
capacitive load. The transient current, which typically has the highest peak at low ambient
Normal Operation
Stand -by Mode
INx = Low
AND
FaultRST = Low
AND
SEn = Low
AND
SELx = Low
INx = High
OR
FaultRST = High
OR
SEn = High
OR
SELx = High
t > t
D_STBY
UM1922 Rev 2 53/196
UM1922 Usage/handling of fault reset and standby
195
temperature and high battery voltage, may trigger the power limitation, leading to latch-off of
the HSD. In consequence the load will not be turned on. Even though the device could be
restarted again by toggling FaultRST pin low for a time longer than tLATCH_RST
, so that all
latches are reset, the latch will occur again as long as the device is maintained in latch-off
mode.
A possible way to overcome this issue is managing the FaultRST pin in such a way that the
latch-off functionality is blanked out for a time longer than the time of the inrush of the bulb.
The following figure is giving an example, on how the correct turn-on of an incandescent
bulb is ensured by means of a 20 ms blanking pulse on FaultRST pin. Despite the device
toggles in Power Limitation for approximately 10 ms, the load is correctly activated with
negligible delay.
Figure 31. FR handling example - bulb inrush blanking (VNQ7140AJ)
Even more, the FaultRST pin can be managed as a global system pin, connecting this pin of
several high-side drivers in parallel to a specific microcontroller I/O port (refer to example in
Figure 32 and Section 8.1: Paralleling of logic input pins for advice on how to parallel pins).
This signal is always kept high, means all connected devices are configured in latch-off
mode, except
For a periodical “unlatch” pulse for duration longer than tLATCH_RST max, once per
diagnostic period. This “unlatch” pulse aims at restarting all latched channels, which
are supposed to be restarted, i.e. when the debouncing strategy for short circuit
detection is not yet elapsed.
For a blanking pulse (FaultRST low for i.e. 10 ms) generated at every activation of any
channel.
Figure 33 illustrates the described FaultRST pin handling concept.
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54/196 UM1922 Rev 2
Figure 32. Common FaultRST pin handling example – basic schematic (without
decoupling components)
Figure 33. FaultRST pin handling concept
A practical example shall further clarify the concept. A quad channel device is used in the
following conditions:
OUT0: bulb (start-up)
OUT1: floating
OUT2: short to GND (permanent on)
OUT3: floating
Channel 0 is switched on. Channel 1-3 are permanently on. The MultiSense multiplexer is
switched every 10 ms in order to monitor sequentially the current sense information on
channels 0-3, the TCASE temperature information and the VCC local supply voltage
information. Consequently it takes 60ms to sample once each diagnostic source. On the
FaultRST pin a 20 µs “unlatch” pulse is forced once per diagnostic period and 10 ms
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195
blanking pulse is imposed synchronously with the rising edge on IN0. During bulb inrush
Channel 0 operates in power limitation for a few ms.
Figure 34. FaultRST pin handling example - overview
While Figure 34 shows an overview about the sequence of periodical unlatch pulses and the
blanking pulse on FaultRST pin over several diagnostic periods, Figure 35 provides the
detail of one diagnostic period. CurrentSense on channel 0 rises to VSENSEH failure flag as
soon as the channel enters in power limitation. Thanks to the blanking pulse the channel is
able to turn on the bulb correctly in autorestart mode. CurrentSense on channel 1 and
channel 3 report open load failures. CurrentSense on channel 2 indicates the channel is
latched-off due to a power limitation or overtemperature event.
Figure 36 shows the effect of the regular “unlatch” pulse on the shorted channel 2, as long
as its input is kept high. After elapse of tLATCH_RST the channel is turning on into the short
circuit and latching off again as soon as Tj_SD dynamic temperature threshold (power
limitation) is reached. This fast device intervention protects the device and the system,
including connectors and wire harness, from short circuit stress induced degradation. For
details regarding device endurance in short circuit conditions, refer to the relevant AEC-
Q100-012 characterization reports.
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56/196 UM1922 Rev 2
Figure 35. FaultRST pin handling example – detail of diagnostic period
Figure 36. FaultRST pin handling example – detail of unlatch pulse (Ch. 2)
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UM1922 Rev 2 57/196
UM1922 Usage and handling of MultiSense SEL pin
195
5 Usage and handling of MultiSense SEL pin
For diagnostic of M0-7 devices one analog monitoring output signal is used. It is capable to
provide current sense signal reflecting channel output current or digital failure flag in off
state signaling open load (provided by the presence of an external pull-up resistor) or short
to VCC diagnostic. Information about device temperature or VCC voltage can be also
selected. Signal output is controlled by SEn pin (enable/disable MultiSense output signal)
and a set of SEL pins (used for diagnostic signal selection). The number of control pins
depends on implementation and number of channels applied on device.
5.1 Classification of M0-7 HSDs
As preamble of this chapter, we can consider the M0-7 high-side drivers as belonging to two
main groups:
Monolithic HSDs: one chip is present inside the package
Hybrid HSDs: two chips are present inside the package, one acting as power stage and
the other one acting as drive, control and protection stage.
The main difference between the two categories from an application standpoint is that the
Hybrid HSDs have an additional integrated protection against the reverse battery event
(please refer to Chapter 2: Reverse battery protection).
In Table 13 the current M0-7 set of high-side drivers according to the above classification is
presented. The assembly package to which the final suffix in the part number is referring to
is indicated as well.
Note: Final suffix: J = PowerSS0-16; H = OctaPAK; S = SO-8; Y = PowerSSO-36.
Table 13. Classification of M0-7 HSDs
Typical RON 1 channel 2 channels 4 channels
4 mVN7004AH-E(1)
1. Hybrid HSD.
VND7004AY(1)
7 mVN7007AH(1)
10 mVN7010AJ(2)
2. Monolithic HSD.
12 mVND7012AY(1)
16 mVN7016AJ(2)
20 mVN7020AJ(2) VND7020AJ(2)
30 mVND7030AJ(2)
40 mVN7040AJ
VN7040AS(2) VND7040AJ(2) VNQ7040AY(1)
50 mVN7050AJ
VN7050AS(2) VND7050AJ(2) VNQ7050AJ(2)
140 mVN7140AJ
VN7140AS(2) VND70140AJ(2) VNQ7140AJ(2)
Usage and handling of MultiSense SEL pin UM1922
58/196 UM1922 Rev 2
5.2 SEL pins truth table (device dependant)
There are defined two main categories:
Full logic implementation - provide output current sense, VCC and TCHIP sensing
Reduced logic implementation - only current sense of output(s)
Complete encoding and its mapping to devices can be found in the following tables
(different colors show mapping between device and SEL pins used)
Table 14. Full logic implementation
SEL2SEL1 SEL0SEnMultiSense output signal
Quad channel control signals
Double channel control signals
Single channel control signals
XXXL Hi-Z Hi-Z Hi-Z
LLLH
Current Sense
Current Sense Ch0 Current Sense Ch0
LLHH Current Sense Ch1 Current Sense Ch1
LHLHTCHIP Sense TCHIP Sense Current Sense Ch2
LHHH VCC Sense VCC Sense Current Sense Ch3
HL LH TCHIP Sense
HLHH VCC Sense
HH LH TCHIP Sense
HHHH VCC Sense
Only quad channel
devices have SEL2
Devices list
VND7004AY
VN7010AJ VND7012AY
VN7016AJ VND7020AJ
VN7020AJ VND7030AJ
VN7040AJ VND7040AJ VNQ7040AY
VN7050AJ VND7050AJ
VN7140AJ VND7140AJ VNQ7140AJ
CHIP CC
UM1922 Rev 2 59/196
UM1922 Usage and handling of MultiSense SEL pin
195
5.3 Connection of SEL pins with control logic (Microcontroller)
SEL pins are usually driven by microcontroller in order to select MultiSense output signal
(for diagnostic purposes). In order to save microcontroller pins, multiple devices SEL pins
can be driven in parallel, sharing the same Microcontroller pins. To protect devices and
Microcontroller from disturbances or possible damage, there are valid recommendations for
paralleling of SEL pins (for details, see Chapter 11: Usage in “H-Bridge” configurations).
The following examples show possible combinations and influence to a hardware
connection scheme.
Example 1
VN7020AJ + VND7020AJ + VNQ7140AJ
Common power supply, common GND network
Common SEn, SEL0...2 (separate MultiSense)
All three devices are designed in monolithic technology. Devices have different number of
SEL pins. In order to use only one protection resistor on the side of microcontroller, there
must be used common VBAT power supply as well as the same ground protection network
(fulfilling conditions for paralleling SELn on monolithic devices). Each HSD’s MultiSense
output is mapped to separate A/D input.
Additional A/D channel is used for measurement of GND protection network offset. While
MultiSense is switched to voltage mode (VBAT or TCASE), output level is referred to device
ground (not to global GND).
To adjust measured MultiSense value of VBAT or TCASE, GND offset measured value can be
used accordingly:
Table 15. Reduced logic implementation (only current sense signal, no TCHIP
, no VCC)
SEL1 SEL0SEnMultiSense output signal
Quad channel control signals
Single channel control signal
XXL High Z High Z
LLH
Current Sense Current Sense Ch0
LHH Current Sense Ch1
HLH Current Sense Ch2
HHH Current Sense Ch3
Only quad channel device has
SEL0, SEL1
Devices list
VN7004AH-E VNQ7050AJ
VN7007AH
VN7040AS
VN7050AS
VN7140AS
Usage and handling of MultiSense SEL pin UM1922
60/196 UM1922 Rev 2
VBAT or TCHIP corrected value = VSENSE – VGND
Figure 37. Monolithic devices, common power supply rails, separate MultiSense
Truth table shows signals mapping.
Example 2
VN7020AJ + VND7020AJ + VNQ7140AJ
Common power supply, common GND network
Common MultiSense (separate SEn control)
The same HSDs are used like in Example 1, but different topology is used - separate SEn,
common MultiSense signal. This option uses only one A/D channel for all HSDs.
Table 16. Truth table for monolithic devices, separate MultiSense
SEL2SEL1 SEL0SEn
A/D 1
MultiSense U1
VN7020AJ
A/D 2
MultiSense U2
VND7020AJ
A/D 3
MultiSense U3
VNQ7140AJ
X X X L Hi-Z Hi-Z Hi-Z
LL L H
Current Sense
Current Sense Ch0 Current Sense Ch0
L L H H Current Sense Ch1 Current Sense Ch1
LH L HT
CHIP Sense TCHIP Sense Current Sense Ch2
LH H H V
CC Sense VCC Sense Current Sense Ch3
HL L H
Current Sense(1)
1. SEL2 not applicable - output according SEL1, SEL0 and SEn.
Current Sense Ch0(1) TCHIP Sense
H L H H Current Sense Ch1(1) VCC Sense
HH L HT
CHIP Sense(1) TCHIP Sense(1) TCHIP Sense
HH H HV
CC Sense(1) VCC Sense(1) VCC Sense
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
A/ D 1
A/ D 2
A/ D 3
V
DD
GND
15 k
15 k
15 k
15 k
. . . . .
15 k
15 k
470 pF
470 pF
470 pF
15k
15k
R
SEN SE
R
SEN SE
R
SEN SE
R
PR OT
4k7
V
DD
V
BAT
SEn
SEL 0
SEL 1
SEL 2
INx co ntr ol
D
GND
Common bus for SEn, SEL0..2
U1 U2 U3
100 nF/50 V 100 nF /50 V 100 nF /50 V
A/ D 4
470 pF
15 k GN D offset m easurem ent
15 k
GPIO
FaultR ST
control
GND
SEn
SEL 0
OUT0
V
CC
Multisense
SEL 1
IN0
Faul tRST
GND
IN0
IN1
SEn
SEL0
SEL1
OUT0
OUT1
V
CC
Multisense
FaultR ST
GND
IN0
IN1
IN2
IN3
SEn
SEL 0
SEL 1
SEL 2
OUT0
OUT1
OUT2
OUT3
V
CC
Multisense
FaultR ST
15k
mun husmrsELo 2
UM1922 Rev 2 61/196
UM1922 Usage and handling of MultiSense SEL pin
195
On the other hand, a decreased number of analogue channels increases the number of
control signals - separate SEn Pins control. In total, pin count is the same as in Example 1.
The same strategy as GND offset measurement is used in this example.
Improper configuration on SEn_1...2 outputs causes no valid VSENSE result (multiple
MultiSense outputs can be activated - applied into common RSENSE).
Figure 38. Monolithic devices, common power supply rails, common MultiSense
Truth table shows signals mapping.
Table 17. Truth table for monolithic devices, common MultiSense
SEL2SEL1 SEL0SEn_U1 SEn_U2 SEn_U3 A/D (MultiSense)
XXX L L L Hi-Z
N/A
LLH L L
Current Sense
MultiSense
U1
VN7020AJ
LHH L L
HL H L L T
CHIP Sense
HH H L L V
CC Sense
N/A
L L L H L Current Sense Ch0
MultiSense
U2
VND7020AJ
L H L H L Current Sense Ch1
HL L H L T
CHIP Sense
HH L H L V
CC Sense
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
A/ D 1
V
DD
GND
15 k
15 k
15 k
15 k
. . . . .
15 k
15 k
470 pF
15 k
R
SEN SE
R
PR OT
4k7
V
DD
V
BAT
SEn_3
SEL0
SEL1
SEL2
INx control
D
GND
Common bus for SEL0..2
U1 U2 U3
100 nF /50 V 100 nF / 50V 100 nF / 50V
15 k
15 k
SEn_2
SEn_1
100 .. 470 pF
100 .. 470 pF
100 .. 470 pF
A/ D 2
470 pF
15k GND offset m easur em ent
15 k
GPIO
FaultRST
control GND
SEn
SEL0
OUT0
V
CC
Multisense
SEL1
IN0
FaultRST
GND
IN0
IN1
SEn
SEL0
SEL1
OUT0
OUT1
V
CC
Multisense
FaultRST
GND
IN0
IN1
IN2
IN3
SEn
SEL0
SEL1
SEL2
OUT0
OUT1
OUT2
OUT3
V
CC
Multisense
FaultRST
CommunbusanSEUJ 2
Usage and handling of MultiSense SEL pin UM1922
62/196 UM1922 Rev 2
Example 3
VN7020AJ + VND7020AJ + VNQ7140AJ
Separate power supply lines, common GND network
Common MultiSense (Separate SEn control)
Topology of control part (SEn, SEL0...2) is similar to Example 2. The main difference consists
of using separate power supply lines on HSDs. Due to this fact, recommendations of
paralleling SEL signals are implemented as well as MultiSense input (described in
Chapter 8: Paralleling of devices ):
MultiSense monitor is using diode in series to on MultiSense outputs
Each HSD control signal is using own protection resistor
Figure 39. Monolithic devices, separate power supply rails, common MultiSense
Signals mapping truth table is the same as in Example 2.
L L L L L H Current Sense Ch0
MultiSense
U3
VNQ7140AJ
L L H L L H Current Sense Ch1
L H L L L H Current Sense Ch2
L H H L L H Current Sense Ch3
H L L L L H Hi-Z
H L H L L H Hi-Z
HHL L L H T
CHIP Sense
HHH L L H V
CC Sense
x x x Other combinations of SEnHazard states
Table 17. Truth table for monolithic devices, common MultiSense (continued)
SEL2SEL1 SEL0SEn_U1 SEn_U2 SEn_U3 A/D (MultiSense)
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
A/ D 1
V
DD
GND
. . . . .
470 pF
15k
R
SEN SE
R
PR O T
4k7
V
DD
V
BAT 2
SEn _3
SEL0
SEL1
SEL2
INx co ntrol
D
GND
Common bus for SEL0..2
U1 U2 U3
100 nF /50 V 100 nF /50 V 100 nF /50 V
SEn _2
SEn _1
100.. 470 pF
100 .. 470 pF
100 . .470 pF
A/ D 2
470 pF
15k
V
BAT 1
15k
15k
15k
15k
15k 15k
15k
15k
15k
15k
GPIO
FaultRST
control
GND
SEn
SEL 0
OUT0
V
CC
Multisense
SEL 1
IN0
FaultRST
GND
IN0
IN1
SEn
SEL0
SEL1
OUT0
OUT1
V
CC
Multisense
FaultRST
GND
IN0
IN1
IN2
IN3
SEn
SEL0
SEL1
SEL2
OUT0
OUT1
OUT2
OUT3
V
CC
Multisense
FaultRST
15k 15k 15 k
15k
15k
15k
15k
15k
15k
15k
R
PROT
4k7 D
GND
A/ D 3
15k
470 pF
GND offset m easurement
UM1922 Rev 2 63/196
UM1922 Usage and handling of MultiSense SEL pin
195
Example 4
VN7004AH-E + VND7020AJ
Separate power supply lines
Common control pins (SEn), separate MultiSense
Depicted is a combination of hybrid and monolithic HSDs. In order to use common control
signals for both HSDs, protection resistor is used for each device separately (see Chapter 8:
Paralleling of devices , paralleling monolithic and hybrid HSDs). Additional A/D is used for
GND shift offset compensation of TCHIP and VBAT signals.
Figure 40. Monolithic and hybrid device, separate power supply rails, separate
MultiSense
Truth table shows signals mapping.
Example 5
VN7004AH-E + VNQ7040AY
Separate power supply lines
Separate SEn control pins (common MultiSense)
Because of both hybrid HSDs share common MultiSense and different power supply lines
are used on each HSD, serial protection diode is used on each device MultiSense output.
Table 18. Truth table monolithic + hybrid, separate MultiSense
SEL1 SEL0SEn
A/D 1
MultiSense U1
VN7004AH-E
A/D 2
MultiSense U2
VND7020AJ
X X L Hi-Z Hi-Z
LLH
Current Sense
Current Sense Ch0
L H H Current Sense Ch1
HLH T
CHIP Sense
HHH V
CC Sense
GPIO
GPIO
GPIO
GPIO
GPIO
A/ D 1
A/ D 2
V
DD
GND
. . . . .
15 k
470 pF
470 pF
15 k
R
SEN SE
R
SEN SE
R
PR OT
4k7
V
DD
V
BAT 1
SEn
SEL0
SEL1
INx control
D
GND
Common bus for SEn, SEL0..1
U1 U2
100 nF / 50 V 100 nF /50 V
15 k
15 k
15 k
V
BAT 2
A/ D 3
470 pF
15k GND offset m easurem ent
GPIO
FaultR ST
control
GND
IN0
IN1
SEn
SEL 0
SEL 1
OUT0
OUT1
V
CC
Multisense
FaultR ST
15k
15k
15k
15 k
15 k
15 k
GND
IN0
SEn OUT0
V
CC
Multisense
FaultR ST
Usage and handling of MultiSense SEL pin UM1922
64/196 UM1922 Rev 2
Figure 41. Hybrid devices, separate power supply rails, common MultiSense
Truth table shows signals mapping.
Table 19. Truth table hybrid devices separate supply rails, common MultiSense
SEL2SEL1 SEL0SEn_U1 SEn_U2 A/D (MultiSense)
XXX L L Hi-Z
N/A H L Current Sense
MultiSense
U1
VN7004AH-E
L L L L H Current Sense Ch0
MultiSense
U2
VNQ7040AY
L L H L H Current Sense Ch1
L H L L H Current Sense Ch2
L H H L H Current Sense Ch3
HLL L H T
CHIP Sense
HLH L H V
CC Sense
HHL L H T
CHIP Sense
HHH L H V
CC Sense
X X X H H Hazard states
. . . . .
470 pF
15k
RSEN SE
VDD
VBAT 2
SEn _2
SEL0
SEL1
SEL2
INx control
SEL0..2
U1 U2
100 nF /50 V 100 nF /50 V
SEn _1
100 .. 470 pF
100 ..470 pF
VBAT 1
15 k
15 k
15 k
15 k
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
A/ D 1
VDD
GND
GPIO
GPIO
LEDx control
GPIO
FaultR ST
control
15k
15 k
15k
15 k
15 k
GND
IN0
IN1
IN2
IN3
LED 0
LED 1
SEn
SEL 0
SEL 1
SEL 2
OUT0
OUT1
OUT2
OUT3
VCC
Multisense
Faul tRST
15 k
15 k
15 k
15 k15k
GND
IN0
SEn OUT0
VCC
Multisense
FaultR ST
ON
UM1922 Rev 2 65/196
UM1922 Load compatibility
195
6 Load compatibility
6.1 Bulbs
This chapter is intended to suggest drivers that can be used for typical automotive bulb
loads or typical combinations of bulbs. A major consideration when driving bulbs is the
inrush current generated when starting up a cold filament.
A properly selected driver should allow the safe turn on of the bulb without any restrictions
under normal conditions. Under worst case conditions the driver should still be able to turn
on the bulb even if some protection of the driver may be triggered temporarily. However, the
drivers´ long term integrity should not be jeopardized. Typical combinations of bulbs and
M0-7 devices (RON classes), are shown in the following Table 20.
Table 20. Typical bulb loads for given M0-7 RON class
Device RDSON class [m]Suggested bulb types and combinations in the given 1.,
2. and 3. conditions
4
2 x H1 (2 x 55 W)
2 x H4 (2 x 55 W/60 W)
2 x H7 (2 x 55 W)
2 x H9 (2 x 65 W)
7
H1 (55 W)
H4 (55 W/60 W)
H7 (55 W)
H9 (65 W)
10
H1 (55 W)
H4 (55 W/60 W)
H7 (55 W)
H9 (65 W)
12
3 x P27 W + R5 W
H1 (55 W)
H4 (55 W/60 W)
H7 (55 W)
H9 (65W)
16
H1 (55 W)
H4 (55 W/60 W)
H7 (55 W)
H9 (65 W)
20
2 x P21 W
2 x P27 W
2 x P21 W + R5 W
2 x P27 W + R5 W
30 2 x P21 W + R5 W
2 x P27 W
40 P21 W + R5 W
P27 W + R5 W
mm m As» J, E" LmemA ND Elm /\, g WW x9 Laad 396’
Load compatibility UM1922
66/196 UM1922 Rev 2
Simulation example – VN7016AJ with H4 bulb (60 W)
A simulation is performed in order to verify if the driver is able to turn on the bulb and
matches the requirements under the defined conditions – see 1. Normal condition, 2. Cold
condition and 3. Hot condition below. The tool used for this simulation is based on
Matlab/Simulink.
Figure 42. Principle of the setup used for the simulation
1. Normal condition
–V
BAT
: 13.5 V
–T
CASE:25 °C
–T
BULB:25 °C
Requirement: none of the protection functions must be triggered.
50 P21 W
P27 W(1)
140 2 x R5 W
R10 W(2)
1. Condition 3. applied to VNQ7050AJ is fulfilled with TCASE = 90 °C
2. Condition 3. applied to VNQ7140AJ is fulfilled with TCASE = 95 °C
Table 20. Typical bulb loads for given M0-7 RON class (continued)
Device RDSON class [m]Suggested bulb types and combinations in the given 1.,
2. and 3. conditions
GAPG1122131140MS
mum sv‘ m vmmsu mm magma ramuwmmmn 1AmD a JUz mum
UM1922 Rev 2 67/196
UM1922 Load compatibility
195
Figure 43. Simulation result–normal condition
2. Cold condition
–V
BAT
: 16 V
–T
CASE: 25 °C
–T
BULB: -40 °C
Requirement: power limitation allowed for durations of less than 20 ms
(autorestart mode considered).
GAPG1122131141MS
vmmmmm hymns muzzm‘m 7mm «.mmmamm Vha u 02 m», m vM/umuuevmerum vsom U: mum m‘xmon ”mu m. 43 '——~—v——*v——i nm 7 ‘ um um nouwmu m an an 20 mu m LLZ um; um ow nme (s)
Load compatibility UM1922
68/196 UM1922 Rev 2
Figure 44. Simulation result–cold condition
3. Hot condition
–V
BAT
: 16 V
–T
CASE: 105 °C
–T
BULB: 25 °C
Requirement: thermal shutdown is allowed for a duration below 20 ms
(autorestart mode considered).
Figure 45. Simulation result–hot condition
GAPG1122131142MS
GAPG1122131143MS
UM1922 Rev 2 69/196
UM1922 Load compatibility
195
Conclusion
The device is able to turn-on a H4 bulb (60 W) under specified conditions 1. Normal
condition, 2. Cold condition and 3. Hot condition without triggering the device protection
functions (Power Limitation, Thermal shutdown).
Note: The mentioned simulation example only refers to the inrush current at turn-on of a cold bulb.
Still the steady state power dissipation and, in case of PWM is applied, the additional
switching losses of the driver have to be considered in order not to exceed the maximum.
possible power dissipation. This obviously becomes more important with a larger number of
channels per package (i.e. dual or quad channel drivers) and high power loads applied to
more than one channel. In case the application requires latch mode configuration of the
HSD, in order to avoid unwanted turning off of the bulb during the inrush phase it is
suggested to implement a proper software strategy, in order to set up a blanking time
whenever the inrush of the bulb occurs. Blanking time length depends on environmental
conditions, bulb type and device type.
6.2 Power loss calculations
The power loss calculation is an important step during the application design as it is a basis
for further thermal considerations and PCB design.
This chapter is intended to provide guidelines for calculation and estimation of power
dissipation in the device in combination with different kind of loads (resistive, inductive,
capacitive etc.) and with different modes of operation (steady state, PWM).
All next evaluations are focused on power losses in the power MOSFET of the device. The
power dissipation of other parts (control logic, charge pump) is in most cases negligible. If
needed, it can be calculated from the device supply current (IS) and supply voltage value
(VCC):
Device control part power dissipation [W]:
Example 1: For VND7020AJ
Figure 46. Control stage current consumption in ON state, all channels on driving
nominal load - datasheet value)
The next description is divided into 2 sub-chapters:
Conduction losses: steady-state losses (during the ON state)
Switching losses: losses during switching phases
PCTRL VCC IGND ON
=
IGND(ON)
Control stage current
consumption in ON
state. All channels
active.
VCC = 13 V; VSEn = 5 V;
VFR = VSEL0,1 = 0 V;
VIN0 = 5 V; VIN1 = 5 V;
IOUT0 = 3 A; IOUT1 = 3 A
—— 12mA
PCTRL VCC IGND ON
13V 12mA156mW===
'our ON
Load compatibility UM1922
70/196 UM1922 Rev 2
6.2.1 Conduction losses
The conduction losses are given by the power dissipation of the MOSFET switch due to the
ON state resistance (RON).
ON state power dissipation [W]:
ON state energy loss [J]:
where tON = ON state duration
Example 2: For VND7020AJ
Figure 47. Steady state condition, datasheet values IOUT = 3 A, RON at 150 ºC = 44 m
The RON parameter depends mainly on temperature (see measurement on Figure 48). This
should be taken into account during the calculations.
In most cases, it is not necessary to consider the dependency on VCC or IOUT
. The RON is
almost independent of VCC down to ~4 V (see Figure 49) and almost independent of IOUT
for a Drain Source voltage range above the output voltage drop limitation (given in the
datasheet as VON = 20 mV typical - see Figure 49).
PON RON I2OUT
=
WRON PON tON
=
RON ON-state resistance
IOUT = 3 A; Tj = 25 °C 22
m
IOUT = 3 A; Tj = 150 °C 44
IOUT = 3 A; VCC = 4 V;
Tj = 25 °C 30
PON RON I2OUT
44m3A2
396mW===
ON
UM1922 Rev 2 71/196
UM1922 Load compatibility
195
Figure 48. RON dependency on temperature (measured on a VND7140AJ sample)
Figure 49. RON dependency on VCC (measured on a VND7140AJ sample)
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Load compatibility UM1922
72/196 UM1922 Rev 2
Figure 50. RON dependency on IOUT (measured on a VND7140AJ sample)
The calculation of conduction losses in PWM mode is based on similar consideration as in
case of steady state losses (focusing on RON, IOUT
, ton), however it is important to consider
right PWM on time (corrected with the turn-on/off switching delays and switching times) and
right current in on state (for instance in case of bulb it depends on actual duty cycle):
Corrected duty cycle [-]:
where:
Duty cycle applied on input pin
Turn on/off delay time
Turn on switching time
ON state power dissipation [W]
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tperiod
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--------------- [s]
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=
UM1922 Rev 2 73/196
UM1922 Load compatibility
195
Note: In case of bulb, the load current in on state depends on actual duty cycle.
Average power dissipation: [W]:
6.2.2 Switching losses
The switching losses are important especially in PWM operation. Compared to conduction
losses, the calculation depends on many factors like the load characteristic (resistive,
capacitive or inductive), device characteristics (switching times) and environmental
conditions (ambient, temperature, battery voltage).
The switching shapes of M0-7 devices are optimized to fulfill the EMC requirements with
minimum switching losses. Moreover, the turn-on and turn-off shapes are symmetrical to
ensure minimum duty cycle error.
Switching losses-resistive loads, bulbs
This sub chapter deals with all kind of loads with resistive character (such as bulbs, heating
elements etc.). The inductivity of wire harness is neglected (< 5 µH considered). The next
calculations are simplified assuming constant resistance of the load. However, it is
applicable also for non-linear resistive loads (bulbs) driven in PWM mode. The PWM
frequency is usually high enough (>50 Hz) to minimize the filament temperature (resistance)
variation over the PWM period so it behaves like constant resistor.
The instantaneous power dissipation in the switch during the switching phase is equal to
drain to source voltage (VDS) multiplied by the output (load) current (IOUT). With given
switching shapes and resistive load, the instantaneous power dissipation can be
approximated by triangular waveform (see yellow area on Figure 51).
PAVG PON DCOR
=
Load compatibility UM1922
74/196 UM1922 Rev 2
Figure 51. Switching and conduction losses (resistive loads)
Considering resistive load, the maximum instantaneous power dissipation occurs at half of
the nominal output voltage and half of the nominal load current. It is the point where the
switch resistance matches the load resistance (maximum power transfer theorem,
impedance matching).
Peak power dissipation [W]:
Turn-on (Turn-off) energy loss [J]:
Note: Linear shape of the switching phase and symmetrical turn-on/off shapes considered
Same calculations are applicable also on the bulb in PWM mode. If the PWM frequency is
high enough (> 50 Hz) the filament temperature (resistance) variation over the PWM period
is negligible so it behaves like constant resistor.
Note: Typical and maximum switching losses on nominal resistive loads are specified in the
datasheet with parameters WON and WOFF (considering VCC = 13 V, -40 °C < Tj < 150 °C).
The switching losses vary with battery voltage. If we suppose constant switching times at
varying the battery voltage, this yields:
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2
--------------
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2R
--------------VBAT
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4R
--------------==
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1
6
---
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2
R
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== tWON tWOFF
=
UM1922 Rev 2 75/196
UM1922 Load compatibility
195
Experimental measurements on M0-7 HSDs have highlighted that switching times are
slightly decreasing with increasing VCC so the above formulas are approximated.
Calculation example: VND7040AJ
Load: 4.5 resistor
VBAT
: 16 V
tWON, tWOFF: 60 µs this parameter is not explicitly specified in the datasheet.
The value can be obtained by the measurement (this case) or estimated from dVOUT/dt
datasheet parameter
Requirement: driver must not run into thermal shutdown
Peak power dissipation [W]:
Turn-on/Turn-off energy loss [J]:
Switching losses measurement–comparison with calculation
The switching losses in the HSD are measured by an oscilloscope with mathematical
functions. The first function F1 shows the actual power dissipation on the HSD
(VBAT - VOUT) * IOUT
, the second function F4 shows the HSD energy (integral of F1).
WONatVBAT2 WONatVBAT1
PLOADatVBAT2
PLOADatVBAT1
---------------------------------------
=
WOFFatVBAT2 WOFFatVBAT1
PLOADatVBAT2
PLOADatVBAT1
---------------------------------------
=
PMAX
VBAT
2
4R
-------------- 16V2
44.5
---------------------14.2W== =
WON WOFF
1
6
---16V2
4.5
--------------60s 569J== ==
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76/196 UM1922 Rev 2
Figure 52. Example of switching losses on VND7040AJ with 4.5 resistive load
As seen from the measurement, in this case the switching shapes are not absolutely
symmetrical so the turn-off loss is slightly higher (531 µJ turn-off versus 417 µJ turn-on).
Measured values are slightly below the calculated value (569 µJ).
Another measurement example shows switching shapes and losses of VNQ7040AY on
channel 0 configured in bulb mode, VBAT = 16 V, Temperature = 25 ºC, resistive load 5.2:
mmmunsusm
UM1922 Rev 2 77/196
UM1922 Load compatibility
195
Figure 53. Example of switching losses on VNQ7040AY with 5.2 resistive load
Switching losses - LED clusters
The switching losses evaluation in combination with LED loads is a much more complex
task compared with resistive loads. Since there are many different types of the LED string, it
is almost impossible to cover all cases with one general calculation formula (like in case of
resistive loads). Exact calculation is problematic even for specific LED load (with known
behavior) due to its non-linear V/A characteristic (see examples in the next figures).
Therefore, it is usually more efficient to do the estimation only or switching losses
measurement as shown in this chapter.
Figure 54. LED cluster example 1–LED test board (6 x 3 LEDs OSRAM LA E67-4)
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78/196 UM1922 Rev 2
Figure 55. LED cluster example 2–tail & brake light (VW Passat B6)
The first example shows a simple LED cluster with serial-parallel combination of LEDs and
resistors. In the second example there is a schematic and V/A characteristic measured on a
real LED lamp (VW Passat B6). As seen on schematic, on top of the serial-parallel
LED/resistor strings there is a reverse battery protection diode, ESD capacitor on input
terminal and “dummy load” circuitry with bipolar transistors. This circuitry is used to adapt
the LED string behavior (V/A characteristic) according to diagnostic requirements (open
load in on-state, open load in off-state).
Example 1: Switching losses–measurement
The following example shows the switching losses measurement on VND7140AJ with LED
cluster example 1 (LED test board - 6 x 3 LEDs OSRAM LA E67-4) using an oscilloscope
with mathematical functions. The first function F1 shows the actual power dissipation on the
HSD (VBAT - VOUT) * IOUT
, the second function F4 shows the HSD energy (integral of F1).
Conditions:
VBAT
: 16 V
Temperature: 23 °C
PWM: 200 Hz, 70 %
Load: test board with 6 x 3 LED OSRAM LA E67-4 (see Figure 54)
Device: VND7140AJ
UM1922 Rev 2 79/196
UM1922 Load compatibility
195
Figure 56. Slew rate and switching losses (VND7140AJ, LED test board)
Measured losses: WON ~ 6.9 µJ, WOFF ~ 8.5 µJ
Contribution to total average power dissipation:
Example 2: Switching losses – measurement
This example shows the switching losses measurement on VND7140AJ with LED cluster
example 2 (VW Passat B6–tail & brake light) using an oscilloscope with mathematical
functions. The first function F1 shows the actual power dissipation on the HSD
(VBAT - VOUT) * IOUT
, the second function F4 shows the HSD energy (integral of F1).
Conditions:
VBAT
: 16 V
Temperature: 23 °C
PWM: 200 Hz, 70 %
Load: VW Passat B6 – Tail & Brake (see Figure 55)
Device: VND7140AJ
GAPG1127130951MS
VBAT
VOUT
IOUT
PLOSS = (VBAT-VOUT)*IOUT
6.9μJ
0.55W
8.5μJ
0.6W
PSW
WON WOFF
+
TPWM
-------------------------------------6.9J8.5J+
1
200Hz
------------------
-------------------------------------3.1mW===
‘V + R DEMA ‘V G‘ I 0 ‘ .
Load compatibility UM1922
80/196 UM1922 Rev 2
Figure 57. Slew rate and switching losses (VND7140AJ, VW Passat B6–tail & brake)
Measured losses: WON ~ 26 µJ, WOFF ~ 17 µJ
Contribution to total average power dissipation:
Switching losses - inductive loads
A typical characteristic of inductive loads is the tendency to maintain the direction and value
of the actual current flow. Applying nominal voltage on inactive load (turn-on), it takes a
certain time (depending on time constant = L/R) to reach nominal current. Removing the
voltage source from the active load (turn-off), the load inductance tends to continue to drive
the current via any available path (i.e. clamp of the HSD) by reversing its voltage (acts as a
source) until the stored energy (EL=1/2 L I02) is dissipated. Time needed to dissipate this
energy is called demagnetization time (TDEMAG). This time is strongly dependent on the
voltage across the load (VDEMAG) at which the demagnetization is performed (higher
|VDEMAG| shorter TDEMAG). A typical VDEMAG for M0-7 devices is equal to VCC – 46 V.
Corresponding TDEMAG can be calculated as
(neglecting the turn-off switching time of the HSD) where L = load inductance; R = load
resistance and I0 = load current at the beginning of turn-off event.
From these considerations it is obvious that instant power dissipation and switching losses
in the HSD are usually higher at turn-off phase. Since the HSD output behavior
(voltage/current waveforms) depends on several factors (mainly on the ratio between the
demagnetization time and turn-off switching time tWOFF), the next analysis of switching
losses is divided into the following parts:
Low inductance (TDEMAG < tWOFF)
High inductance (TDEMAG > tWOFF)
High inductance (TDEMAG > tWOFF) with external freewheeling diode
Steady state operation (single turn-on / turn-off)
PWM operation
GAPG1127130952MS
V
BAT
V
OUT
I
OUT
P
LOSS
= (V
BAT
-V
OUT
)*I
OUT
26μJ
2.1W
17μJ
1.1W
PSW
WON WOFF
+
TPWM
-------------------------------------26J17J+
1
200Hz
------------------
----------------------------------8.6mW===
TDEMAG
L
R
----VDEMAG I0R+
VDEMAG
-----------------------------------------------
ln=
UM1922 Rev 2 81/196
UM1922 Load compatibility
195
Low inductance (TDEMAG < tWOFF)
If the load inductance is relatively low (so the stored energy is dissipated within the HSD
turn-off time tWOFF), the output voltage decays down to 0 (or slightly in negative) without the
activation of the output clamp (see Figure 58).
Figure 58. Switching losses with low inductance
In this case, the switching losses can be roughly estimated from equivalent losses with pure
resistive load (see calculation in previous chapter). Since the output current is delayed from
the output voltage, the losses at turn-on phase (WON) will be lower, while the losses at turn-
off phase (WOFF) will be higher (up to factor of 5) in comparison with pure resistive load.
This factor was found experimentally in condition when the demagnetization time (TDEMAG)
is matching with turn-off switching time (tWOFF).
Measurement example – Low inductance (TDEMAG < tWOFF)
This measurement example compares the switching losses in the VND7040AJ with two
different loads – pure resistive 13.5 and 60 µH at 13.5 .
Conditions:
VBAT
: 16 V
Temperature: 23 °C
PWM: 200 Hz, 70 %
Load: 13.5 ; 60 µH at 13.5 (calculated TDEMAG = 1.9 µs)
Device: VND7040AJ
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82/196 UM1922 Rev 2
Figure 59. Low inductance (TDEMAG << tWOFF) – measurement example
Measured losses (pure resistive 13.5 ): WON ~ 139 µJ, WOFF ~ 157 µJ
Measured losses (60 µH at 13.5 ): WON ~ 116 µJ, WOFF ~ 204 µJ
WON ratio (60 µH versus pure resistive): 116 / 139 = 0.83x
WOFF ratio (60 µH versus pure resistive): 204 / 157 = 1.30x
High inductance (TDEMAG > tWOFF)
If the load inductance is relatively high (so the time needed for the load demagnetization is
much higher than the HSD turn-off time tWOFF), the output voltage at turn-off phase is forced
negative so the load current continues via the HSD output clamp (see Figure 60).
GAPG1127130954MS
VND7040AJ at 13.5Ω
VND7040AJ at 60μH / 13.5Ω
157μJ
139μJ
204μJ
116μJ
VBAT
VOUT
IOUT
PLOSS = (VBAT-VOUT)*IOUT
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UM1922 Rev 2 83/196
UM1922 Load compatibility
195
Figure 60. Switching losses with high inductance
The above example explains a single turn-on / turn-off event. This means that zero load
current is considered at the beginning of turn-on phase and nominal load current is
considered at the beginning of turn-off phase.
Assuming TDEMAG >> tWOFF
, the switching losses can be calculated as follows:
Turn-on energy loss [J]:
Turn-off energy loss [J]:
(Losses during transition phases tWON and tWOFF neglected)
Calculation example (single turn-on / off event):
Load: 20 mH at 13.5
VBAT
: 16 V
VDEMAG: -30 V (VBAT – 46)
I0: 1.185 A (VBAT / 13.5 )
WON 0 (TDEMAG >> TWON 633 µs >> ~60 µs condition fulfilled)
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------------------------------------------------ LRI
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VDEMAG I0R+
VDEMAG
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

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R
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VDEMAG
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13.5
----------- 301.185 13.5+
30
--------------------------------------------------
ln633s== =
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Load compatibility UM1922
84/196 UM1922 Rev 2
Measurement example, comparison with calculation – high inductance
(TDEMAG > tWOFF)
Conditions:
VBAT
: 16 V
Temperature: 23 °C
Load: 20 mH at 13.5
Device: VND7040AJ
Figure 61. High inductance (TDEMAG >> tWOFF) – measurement example
Measured TDEMAG: 6500 µs (633 µs calculated)
Measured WON: 11 µJ (0 estimated)
Measured WOFF: 13.63 mJ (16 mJ calculated)
Measured losses (pure resistive 13.5 ): WON ~ 139 µJ, WOFF ~ 157 µJ
WON ratio (20 mH versus pure resistive): 11/139 = 0.08x
WOFF ratio (20 mH versus pure resistive): 13630/157 = 86.8x
The measured values correspond to theoretical assumptions and calculations:
High inductance (TDEMAG > tWOFF) with external freewheeling diode
An external clamping circuitry (i.e. freewheeling diode) is usually used to protect the HSD in
case the demagnetization energy is exceeding the energy capability of a given HSD. By
using a standard freewheeling diode, the demagnetization voltage is reduced from –32 V (a
typical VDEMAG of M0-7 device at VBAT = 14 V) to approximately –1 V (depending on
forward voltage of the diode - see Figure 62). This has an influence to the demagnetization
time (lowering |VDEMAG| increasing TDEMAG), as can be derived from the TDEMAG
equation.
WOFF
VDEMAG VBAT
+
R2
------------------------------------------------ LRI
0VDEMAG
VDEMAG I0R+
VDEMAG
-----------------------------------------------
ln



 ==
3016+
13.52
------------------------- 0.02 13.5 1.185 30301.185 13.5+
30
--------------------------------------------------
ln


 16mJ==
GAPG1127130956MS
VND7040AJ at 20mH / 13. 13.63mJ
VBAT
VOUT
IOUT
PLOSS = (VBAT-VOUT)*IOUT
42W
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UM1922 Rev 2 85/196
UM1922 Load compatibility
195
Figure 62. Switching losses with high inductance and external freewheeling (single event)
The above example explains a single turn-on / turn-off event. This means that zero load
current is considered at the beginning of turn-on phase and nominal load current is
considered at the beginning of turn-off phase.
Assuming TDEMAG >> tWOFF
, the switching losses can be estimated as follows:
Turn-on energy loss [J]: WON ~ 0
Turn-off energy loss [J]: WOFF 3x higher versus pure resistive load
Note: The factor 3 is the result of experiment (see Table 21 and Table 22)
In PWM operation (or at turn-on with a small delay after the last turn-off) there is a possibility
that the turn-on event comes before the end of the demagnetization phase (if the PWM off-
state time is shorter that the load demagnetization time: (TDEMAG > TPWM_OFF). This means
that turn-on phase is starting while the current is still forced via the freewheeling diode. This
makes the turn-on switching loss significant if compared with the case of zero starting
current. As a rough estimation a ~3x higher value can be considered versus equivalent
resistive load. This way of the operation is frequently used on purpose – i.e. for the load
current regulation by PWM duty cycle (see Figure 63).
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86/196 UM1922 Rev 2
Figure 63. Switching losses – high inductance + ext. freewheeling (PWM operation)
Assuming TDEMAG >> TPWM_OFF
, the switching losses can be estimated as follows:
VBAT
: 16 V
Temperature: 23 °C
Turn-on energy loss [J]: WON ~3x higher versus equivalent resistive load
Turn-off energy loss [J]: WOFF ~3x higher versus equivalent resistive load
Note: The factor 3 is the result of experiment (see Table 21 and Table 22)
Measurement example 1 – high inductance with external freewheeling (single
event)
Conditions:
VBAT
:16 V
Temperature: 23 °C
Load: 20 mH at 13.5
External freewheeling diode: STPS2H100
Device: VND7040AJ
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UM1922 Rev 2 87/196
UM1922 Load compatibility
195
Figure 64. High inductance (TDEMAG > tWOFF): measurement example 1
Measured losses (20 mH at 13.5 ): WON ~ 11 µJ, WOFF ~ 533 µJ
Measured losses (pure resistive 13.5 ): WON ~ 139 µJ, WOFF ~ 157 µJ
WON ratio (20 mH versus pure resistive): 11 / 139 = 0.08x
WOFF ratio (20 mH versus pure resistive): 533 / 157 = 3.39x
The measured values confirm that the turn-on switching loss is negligible (zero starting
current) while the turn-off switching loss is ~3x higher in comparison with pure resistive load.
Measurement example 2 – High inductance with external freewheeling (single
event)
Conditions
VBAT
:16 V
Temperature: 23 °C
Load: 1 mH at 2
External freewheeling diode: STPS2H100
Device: VN7004AH-E
Figure 65. Figure 62: High inductance (TDEMAG > tWOFF) – measurement example 2
Measured losses (1 mH at 2 ): WON ~ 0.04 mJ, WOFF ~ 1.75 mJ
GAPG1127130959MS
VND7040AJ at 20mH / 13.5Ω
(external freewheeling)
533μJ
VBAT
VOUT
IOUT
PLOSS = (VBAT-VOUT)*IOUT
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Load compatibility UM1922
88/196 UM1922 Rev 2
Measurement example 3 – High inductance with external freewheeling (PWM
operation)
Conditions:
VBAT
:16 V
Temperature: 23 °C
Load: 20 mH at 13.5
External freewheeling diode: STPS2H100
Device: VND7040AJ
PWM: 80 % at 500 Hz
Figure 66. High inductance (TDEMAG > TPWM_OFF) – measurement example
Measured losses (20 mH at 13.5 ): WON ~ 307 µJ (IOUT ~ 1 A)
WOFF ~ 463 µJ (IOUT ~ 1.2 A)
Measured losses (resistive 13.5 ): WON ~ 139 µJ (IOUT = 1.2 A)
WOFF ~ 157 µJ (IOUT = 1.2 A)
WON ratio (20 mH versus resistive equivalent): 307/(139 * 12/1.22) = 3.18x
WOFF ratio (20 mH versus resistive equivalent): 463/157 = 2.95x
GAPG1127131000MS
VND7040AJ at 20mH / 13.
(external freewheeling)
463μJ
P
LOSS
= (V
BAT
-V
OUT
)*I
OUT
16W
307μJ
13W
DEMAG PWM OFF VN7004AI' a! 1mH I 2n (external freewheeling)1 um m n w W __,_.--—— 12“_J/ _( ‘ m K sow PLOSS = (VaAT-Vouv)‘lou1 A n..." ». mum Vznseznsmm) Mummy mummmcu) rs . .. 75. .. um 11mm: 5942124: Imam; menus u.44mJ * mpcmzmsnem
UM1922 Rev 2 89/196
UM1922 Load compatibility
195
The measured values confirm that the turn-on and turn-off losses are ~3x higher in
comparison with equivalent resistive load.
Measurement example 4 – High inductance with external freewheeling (PWM
operation)
Conditions:
VBAT
:16 V
Temperature: 23 °C
Load: 1 mH at 2
External freewheeling diode: STPS2H100
Device: VN7004AH-E
PWM: 80 % at 500 Hz
Figure 67. High inductance (TDEMAG > TPWM_OFF) – measurement example 4
Measured losses (1 mH at 2 ): WON ~ 0.44 mJ, WOFF ~ 1.69 mJ
Load compatibility UM1922
90/196 UM1922 Rev 2
Measurement example – switching losses versus L (VND7040AJ)
In order to get a better idea about the switching losses dependency on the value of the
inductance, a comparative measurement with different load inductances was performed on
VND7040AJ. The summary of this measurement is shown in the tables below. The Table 21
describes the steady state operation (single turn-on / off event), with or without an external
freewheeling diode. For each load inductance, there is a measurement of switching losses
and switching times (time between 10-90 % of nominal VOUT considered). All switching
losses are compared versus the resistive load. In the last column there is a calculation of
demagnetization time (considering VDEMAG = -28 V).
VBAT = 16 V Single turn-on (ILOAD = 0), single turn-off (ILOAD = nominal = 1.2 A)
The Table 22 describes the PWM operation with high duty cycle (shortest possible PWM off-
time adjusted to have complete turn-off / on phase). The measurement was done with
external freewheeling only (Schottky diode). In the last column there is a calculation of
demagnetization time (considering VDEMAG = -0.6 V).
VBAT = 16 V PWM 94 % at 500 Hz (120 µs off-time) shortest possible for complete turn-
off/on phase
Table 21. VND7040AJ measurement of switching losses versus L in steady state
Load WON WOFF
WOFF
(with external
freewheeling)
tON [µs] tOFF
[µs]
TDEMAG
(calculated)
L [µH] R [] [µJ] Ratio vs
res. load [µJ] Ratio vs
res. load [µJ] Ratio vs
res. load
10-90%
of VOUT
90-10%
of VOUT
(at -28 V)
[µs]
1.5 13.5 139 1.00 x 157 1.00 x 157 1.00 x 35 39 0.0
15 13.5 130 0.94 x 173 1.10 x 173 1.10 x 35 38 0.5
60 13.5 116 0.83 x 204 1.30 x 204 1.30 x 35 38 1.9
300 13.5 69 0.50 x 382 2.43 x 321 2.04 x 34 35 9.5
1 000 13.5 54 0.39 x 785 5.00 x 438 2.79 x 33 36 32
3 500 13.5 52 0.37 x 2 370 15.1 x 492 3.13 x 31 36 111
5 400 13.5 50 0.36 x 3 470 22.1 x 487 3.10 x 31 36 171
20 000 13.5 11 0.08 x 13 630 86.82 x 533 3.39 x 30 36 633
Table 22. VND7040AJ measurement of switching losses versus L in PWM mode (with external
freewheeling)
Load
WON
(with external
freewheeling)
WOFF
(with external
freewheeling)
tON [µs] tOFF [µs] TDEMAG
(calculated)
L [µH] R [] [µJ] Ratio vs
res. load [µJ] Ratio vs
res. load
(10-90% of
VOUT)
(90-10% of
VOUT)(at -0.6V) [µs]
1.5 13.5 139 1.00 157 1.00 35 39 0.0
15 13.5 130 0.94 173 1.10 35 38 4
60 13.5 118 0.85 205 1.31 35 38 15
UM1922 Rev 2 91/196
UM1922 Load compatibility
195
Note: Used inductors: 1.5 µH ÷ 5.4 mH: Air coil (1.5 mm2 cable)
20 mH: Iron powder core inductor (ISAT ~ 3 A)
The coil resistance compensated by adding a serial resistor to reach 13.5 in total.
Switching losses - capacitive loads
This chapter deals with the switching losses in combination with capacitive loads. A typical
application example is the usage of the HSD as a supply voltage switch for other modules
(see Figure 68).
Figure 68. A typical example of HSD combined with capacitive load
A capacitive character of the load creates an inrush current during turn-on phase,
depending mainly on the load capacitance, switching time and the load resistance (i.e.
capacitor ESR). A typical requirement for the HSD in such applications is ability to handle
the worst case inrush current without activation of the protection mechanisms (power
limitation or thermal shutdown) to ensure correct operation of connected load (module).
Since there are several variables and conditions depending on application, there is no
calculation provided in this chapter.
300 13.5 65 0.47 315 2.01 34 37 74
1 000 13.5 162 1.17 450 2.87 33 38 246
3 500 13.5 302 2.17 490 3.12 32 37 861
5 400 13.5 360 2.59 505 3.22 31 36 1328
20 000 13.5 398 2.86 490 3.12 31 35 4919
Table 22. VND7040AJ measurement of switching losses versus L in PWM mode (with external
freewheeling) (continued)
Load
WON
(with external
freewheeling)
WOFF
(with external
freewheeling)
tON [µs] tOFF [µs] TDEMAG
(calculated)
L [µH] R [] [µJ] Ratio vs
res. load [µJ] Ratio vs
res. load
(10-90% of
VOUT)
(90-10% of
VOUT)(at -0.6V) [µs]
Clamp
V
BAT
OUT
I
OUT
V
OUT
V
DS
M0-7 - HSD
R
GND
D
GND
ESR
C
Supplied module (s)
R
Switchable supply line
Load compatibility UM1922
92/196 UM1922 Rev 2
The following measurement was performed on several different parts (RDSON classes) in
order to determine the turn-on switching loss, slew rate and maximum possible capacitance
which don’t trigger the device protection. The devices were loaded by an electrolytic
capacitor (or parallel combination of capacitors) and 10 k resistor (for the discharge).
Conditions:
VBAT
: 16 V
Temperature: 23 °C
Device/Load (10 k pull down resistor connected in parallel for discharge)
VND7140AJ, Ch.0:
10 µF
22 µF
32 µF (10+22)
44 µF (22+22)
76 µF (22+22+22+10)
88 µF (22+22+22+22)
VND7040AJ, Ch.0:
100 µF
220 µF
320 µF (100+220)
440 µF (220+220)
660 µF (220+220+220)
VND7020AJ, Ch.0:
220 µF
440 µF (220+220)
1220 µF (1000+220)
1440 µF (1000+220+220)
2200 µF
3200 µF (2200+1000)
– VN7016AJ
220 µF
440 µF (220+220)
1000 µF
2200 µF
2640 µF (2200+220+220)
3200 µF (2200+1000)
– VN7004AH-E
220 µF
440 µF (220+220)
2200 µF
3200 µF (2200+1000)
4700 µF
5700 µF (4700+1000)
m m Memur: vama m memos) 1531mm us p2 M@w(ci) p2 amen p4 W02) p57 ,
UM1922 Rev 2 93/196
UM1922 Load compatibility
195
Used capacitors: Electrolytic – aluminum
1 µF / 50V, ESR = 1.7
10 µF / 25V, ESR = 1
22 µF / 25V, ESR = 0.7
100 µF / 50V, ESR = 0.17
220 µF / 35V, ESR = 0.14
1000 µF / 35V, ESR = 0.03
2200 µF / 25 V, ESR = 0.035
4700 µF / 35 V, ESR = 0.020
Experimental results done on a sample of each mentioned device have highlighted that no
protection is triggered for value of capacitance below the ones indicated in Table 23.
Figure 69. Measurement example - VND7040AJ on 320µF
GAPG1127131002MS
Table 23. Maximum capacitance on the HSD output (no power limitation triggered - Tjstart ~ 25 °C)
Part number
Experimentally
determined maximum
capacitance [µF]
Turn-on loss
[mJ]
Slew rate
(dVOUT/dt)
[V/µs]
Max. capacitance [µF]
(safety margin applied)
VND7140AJ 76 (22+22+22+10) 6.05 0.11 47
VND7040AJ 320 (100+220) 19.9 0.084 220
VND7020AJ 1220 (1000+220) 44.7 0.039 820
VN7016AJ 2200 80 0.031 1500
VN7004AH-E 4700 357 0.008 3300
Load compatibility UM1922
94/196 UM1922 Rev 2
Switching losses - Xenon
Since there are several different types of the Xenon modules/Lamps, there is probably no
general way for the switching losses calculation or estimation. Aim of this chapter is to show
one example related to a measurement with specific Xenon module and Xenon lamp.
In most cases, there are two inrush currents phases. The first peak comes during the HSD
activation (charging of the input capacitor of the module) and the second peak after the
ignition of the Xenon bulb. Therefore, in terms of switching losses, the xenon module
behaves like a capacitive load (the first inrush current peak). When the input capacitor is
charged (VOUT reaches nominal current) the input current falls down (usually almost zero)
until the ignition starts (usually after a few ms delay). This second inrush phase is not
contributing to the turn-on switching loss since the HSD is already turned–on. The losses
during HSD deactivation are usually negligible due to the capacitive character of the load.
Switching losses – measurement example
VBAT
: 16 V
Temperature: 23 °C
Load:
Xenon lamp: Phillips D2S 35 W
Ballast: Hella 5DV 008 290-00
Device: VN7016AJ
Figure 70. Xenon load - slew rate, switching losses (VN7016AJ)
Measured values:
WON ~ 3.1 mJ (dVOUT/dt)ON = 0.8*16 V/44 µs = 0.29 V/µs
GAPG1127131003MS
ZOOM
Turn-off after
60s on-time
UM1922 Rev 2 95/196
UM1922 Load compatibility
195
WOFF ~ 0 mJ (dVOUT/dt)OFF = 0.8*16 V/251 µs = 0.051 V/µs
During the HSD channel activation the xenon module behaves like capacitive load
(waveforms / losses equivalent to ~47 µF capacitor). When the input capacitor is charged
(VOUT = nominal) the input current falls to ~0 until the convertor starts (~1.5 ms delay).
The losses during HSD deactivation are below the measurement resolution (capacitive
character of the load).
6.3 Inductive loads
Switching inductive loads such as relays, solenoids, motors etc. can generate transient
voltages of many times the steady-state value. For example, turning off a 12 volt relay coil
can easily create a negative spike of several hundred volts. The M0-7 high-side drivers are
well designed to drive such kind of loads, in most cases without any external protection.
Nevertheless there are physical limits for each component that have to be respected in
order to decide if an external protection is necessary or not.
As a feature of the M0-7 drivers it can be highlighted that a relatively high output voltage
clamping leads to a fast demagnetization of the inductive load.
The aim of this chapter is to have a simple guide on how to check the conditions during
demagnetization, how to select a proper HSD (and the external clamping if necessary)
according to the given load.
6.3.1 Turn-on
When a HSD turns on an inductive load the current is increasing with a time constant given
by L/R values, so the nominal load current is not reached immediately. This fact should be
considered in diagnostics software (i.e. to avoid false open-load detection).
Figure 71. HSD turn-on phase with inductive load
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Load compatibility UM1922
96/196 UM1922 Rev 2
Figure 72. Turn-on example: VND7140AJ with inductive load (L = 260 mH, R = 81 )
6.3.2 Turn-off
The HSD turn-off phase with inductive load is explained in Figure 73. The inductance
reverses the output voltage in order to be able to continue driving the current in the same
direction. This voltage (so called demagnetization voltage) is limited to the value given by
the clamping voltage of the HSD and the battery voltage:
Equation 3
GAPG1127131005MS
VDEMAG VBAT VCLAMP
13V 46V (typical)==
VDEMAG ‘VDEMAG‘ + '0
UM1922 Rev 2 97/196
UM1922 Load compatibility
195
Figure 73. Inductive load–HSD turn-off phase
The load current decays exponentially (linearly if R 0) and reaches zero when all energy
stored in the inductor is dissipated in the HSD and the load resistance.
Since the HSD output clamp is related to the VBAT pin, the energy absorbed by the HSD
grows with increasing battery voltage (the battery is in series with the high-side switch and
load so the energy contribution of the battery is increasing with the battery voltage).
6.3.3 Calculation of dissipated energy
The energy dissipated in the high-side driver is given by the integral of the actual power on
the MOSFET through the demagnetization time:
To integrate the above formula we need to know the current response iOUT(t) and the
demagnetization time TDEMAG
. The IOUT(t) can be obtained from the well-known formula of
R/L circuit current response using the initial current I0 and the final current VDEMAG/R
considering iOUT 0 condition (see Figure 73):
Putting i(t) = 0 we can calculate the demagnetization time:
Equation 4
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EHSD VCLAMP iOUT ttd
0
TDEMAG
=
iOUT t I0I0
VDEMAG
R
---------------------------+


1e
tR
L
-------------



= 0tT
DEMAG iOUT 0
TDEMAG
L
R
----
VDEMAG I0R+
VDEMAG
-----------------------------------------------



ln=
VBAT+ VDEMAG‘ ‘ ‘ 2 VBAT+ ‘VDEMAG‘ \V \ V V V 13.5 46 ‘VDEMAG‘ + '0 \V \ ‘VDEMAG‘ + '0 \V \ 32.5V
Load compatibility UM1922
98/196 UM1922 Rev 2
Equation 5
Substituting the TDEMAG and iOUT(t) by the formulas above we can calculate the energy
dissipated in the HSD:
then
Equation 6
Equation 7
Calculation example:
This example shows how to use above equations to calculate the demagnetization time and
energy dissipated in the HSD:
Battery voltage: VBAT = 13.5 V
HSD: VND7040AJ
Clamping voltage: VCLAMP = 46 V (typical for M0-7)
Load resistance: R = 81
Load inductance: L = 260 mH
Load current (at turn-off event): I0 = VBAT/R = 167 mA
Step 1) Demagnetization voltage calculation using Equation 1
Step 2) Demagnetization time calculation using Equation 2:
limR0TDEMAG LI0
VDEMAG
------------------------=(simplified for R 0
EHSD VCLAMP iOUT ttd
0
TDEMAG
VBAT VDEMAG
+iOUT ttd
0
TDEMAG
==
EHSD
VBAT VDEMAG
+
R2
------------------------------------------------ LRI
0VDEMAG
VDEMAG I0R+
VDEMAG
-----------------------------------------------



ln=
limR0EHSD
1
2
---LI
20
VBAT VDEMAG
+
VDEMAG
------------------------------------------------ =(simplified for R 0
VDEMAG VBAT VCLAMP
13.5 4632.5V===
TDEMAG
L
R
----
VDEMAG I0R+
VDEMAG
-----------------------------------------------



ln0.260
81
---------------ln 32.5 0.167 81+
32.5
--------------------------------------------


1.12ms== =
VBAT * VDEMAG‘ 2 ‘VDEMAG‘ + '0 ‘ WW \ vha Lecrov IPLDSS 1% Elm) \ a r J , ‘ 7m ‘ n A Mzasur: m magical 721mm) ammo mm P57 , Fan vamn 251 mum: an 555mg sums m H mm m m. u“ unsu‘
UM1922 Rev 2 99/196
UM1922 Load compatibility
195
Step 3) Calculation of energy dissipated in the HSD using Equation 6:
Step 4) Measurement (comparison with theory):
Figure 74. Inductive load: turn-off example: VND7040AJ, L = 260 mH, R = 81
The demagnetization energy dissipated in the HSD was measured by an oscilloscope with
mathematical functions. The first function F1 shows the actual power dissipation on the
HSD (VBAT - VOUT) * IOUT
, the second function F4 shows the HSD energy (integral of F1).
As seen from the oscillogram, measured values are close to the theoretical calculation:
EHSD = 3.6 mJ (4.04 mJ calculated), TDEMAG = 1.2 ms (1.12 ms calculated).
6.3.4 Selection criterion with reference to I-L plot
Even if the device is internally protected against break down during the demagnetization
phase, the energy capability has to be taken into account during the design of the
application.
EHSD
VBAT VDEMAG
+
R2
------------------------------------------------ LRI
0VDEMAG
VDEMAG I0R+
VDEMAG
-----------------------------------------------



ln ==
13.5 32.5+
812
----------------------------- 0.260 81 0.167 32.5 32.5 0.167 81+
32.5
--------------------------------------------


ln 4.04mJ==
GAPG1127131007MS
VOUT
VBAT
IOUT
PLOSS = (VBAT-VOUT)*IOUT
E = 3.6mJ
VCLAMP = 42.5V
TDEMAG = 1.2ms
VDEMAG = 29V
‘VDEMAG‘ + '0 \V \ VBAT+ VDEMAG‘ [ 2 ‘VDEMAG‘ J“ '0 \V \ ]
Load compatibility UM1922
100/196 UM1922 Rev 2
It is possible to identify two main mechanisms that can lead to the device failure:
The temperature during the demagnetization rises quickly (depending on the
inductance) and the uneven energy distribution on the power surface can cause the
presence of a hot spot causing the device failure with a single shot.
Like in a normal operation, the life time of the device is affected by the fast thermal
variation as described by the Coffin-Manson law. A repetitive demagnetization energy
causing a temperature variation above 60 K will cause a shorter life time.
These considerations lead to two simple design rules:
The energy has to be below the energy the device can withstand at a given inductance.
In case of a repetitive pulse, the average temperature variation of the device should not
exceed 60 K at turn-off.
To fulfill these rules the designer has to calculate the energy dissipated in the HSD at turn-
off and then to compare this number with the datasheet values as shown in the following
example.
Example:
Check if the VND7020AJ device can safely drive the inductive load 2.2 mH at 4 under
following conditions:
Battery voltage: VBAT = 16 V
HSD: VND7020AJ
Load resistance: R = 4
Load inductance: L = 2.2 mH
Load current (at turn-off event): I0 = VBAT/R = 16 V/4 = 4 A
Power clamping voltage: VCLAMP = 46 V (typical value considered)
Step 1) Demagnetization voltage calculation using Equation 1
Step 2) Demagnetization time calculation using Equation 2:
Step 3) Calculation of energy dissipated in the HSD using Equation 6:
Step 4) HSD datasheet analysis:
The maximum demagnetization energy is derived from the I-L diagram in the datasheet (see
Figure 75).
VDEMAG VBAT VCLAMP
16 4630V===
TDEMAG
L
R
----
VDEMAG I0R+
VDEMAG
-----------------------------------------------



ln0.0022
4
------------------ln 30 4 4+
30
------------------------


235s===
EHSD
VBAT VDEMAG
+
R2
------------------------------------------------ LRI
0VDEMAG
VDEMAG I0R+
VDEMAG
-----------------------------------------------



ln ==
16 30+
42
------------------- 0.0022 4 4 30 30 4 4+
30
------------------------


ln 20.1mJ==
100 10 —vunvazou-s:ny- Puts: —n-p-urm pun Humane-c —Rapmm pun mamas-c 1(4) 0.01 L ("I") 0, 1 10 VBAT + ‘VDEMAG‘ \V \
UM1922 Rev 2 101/196
UM1922 Load compatibility
195
Figure 75. Maximum turn-off current versus inductance – VND7020AJ datasheet
The maximum turn-off current for 2.2 mH inductance is 5.5 A (for the repetitive pulse,
Tjstart = 125 ºC) which is above the load current in this example (I0 = 4 A). However, this
current limit is specified for R = 0 and VBAT = 13.5 V. Since these conditions are different
from conditions considered in this example (R = 4 , VBAT = 16 V), it is recommended to
find the energy limit in the I-L diagram with same demagnetization time as calculated in the
example (235 µs). Then it is possible to directly compare this limit with calculated energy in
the application (regardless the different condition). As a first step, the 2.2 mH, 5.5 A limit is
selected from the I-L diagram and related energy limit and demagnetization time is
calculated:
Demagnetization energy related to selected point (2.2 mH, 5.5 A) using Equation 7:
Demagnetization time related to selected point (2.2 mH, 5.5 A) using Equation 5:
Note: Same calculation as EMAX and TDEMAG is performed at 1 mH and 0.1 mH, just to see the
dependency on inductance (see Figure 75).
As seen from the calculation, the maximum energy related to selected point is 47.1 mJ at
372 µs. In order to find the energy limit at 235 µs, either an iterative process can be
performed in graphical way (repeat the same calculation with different I-L point choices until
the TDEMAG is matching), or the following empiric formula can be used, where E1 is the
sustainable energy for time t1 and E2 is sustainable energy corresponding to different
application condition (time t2):
GAPG1127131008MS
Specified at:
VCC = 13.5V
R = 0Ω
2.2
5.5
2.2mH, 5.5A:
EMAX =~47.1mJ
TDEMAG = ~372μs
1mH, 7.7A
EMAX = ~42mJ
TDEMAG = ~237μs
0.1mH, 18A
EMAX = ~22.9mJ
TDEMAG = ~55μs
EMAX
1
2
---LI
2MAX
VBAT VDEMAG
+
VDEMAG
------------------------------------------------  1
2
---0.0022 5.5213.5 32.5+
35.5
-----------------------------47.1mJ===
TDEMAG LI0
VDEMAG
------------------------0.0022 5.5
32.5
-----------372s== =
2 235,15 t 43 m A Lang u m l ‘ W ,5”; P ~11: ‘ m... mm mm mmmcv NV 757 Va W wsqznnus mm“: W y, 325 594 vs
Load compatibility UM1922
102/196 UM1922 Rev 2
Conclusion: The device is able to safely drive the selected load since the calculated
demagnetization energy (20.1 mJ at 235 µs) is clearly below the maximum allowed
demagnetization energy derived from the I-L diagram for the repetitive operation
Tjstart = 125 ºC: 37.4 mJ at 235 µs.
Step 5) Measurement (comparison with theory):
The demagnetization energy dissipated in the HSD was measured by an oscilloscope with
mathematical functions. The first function F1 shows the actual power dissipation on the
HSD (VBAT - VOUT) * IOUT
, the second function F4 shows the HSD energy (integral of F1).
Figure 76. Inductive load – turn-off: VND7020AJ, L = 2.2 mH, R = 4
As seen from the oscillogram, measured values are close to the theoretical calculation:
EHSD = 19.1 mJ (20.1 mJ calculated), TDEMAG = 220 µs (235 µs calculated).
Conclusion:
The device can safely drive the load without additional protection. The worst case
demagnetization energy is clearly below the device limit.
6.3.5 External clamping protection
The main function of an external clamping circuitry is to clamp the demagnetization voltage
and dissipate the demagnetization energy in order to protect the HSD. It can be used as a
cost effective alternative in case the demagnetization energy is exceeding the energy
capability of a given HSD. A typical example is driving DC motors (high currents in
combination with high inductance). During the selection of a suitable HSD for such kind of
application we usually end up in the situation that a given HSD is fitting in terms of current
profile, but the worst case demagnetization energy is too high (turn-off from stall condition at
E2E1
t2
t1
----47.1mJ 235s
372s
-----------------37.4mJ==
fills/I.
UM1922 Rev 2 103/196
UM1922 Load compatibility
195
16 V, -40 ºC). Rather than selecting a bigger HSD the use of an external clamp can be the
most convenient choice.
External clamping circuitry – requirements summary:
Negative clamping voltage below the HSD clamping voltage
No conduction at:
Normal operation (0-16 V)
Jump start (27 V for 60 s)
Load Dump (36 V for 400 ms)
Reverse battery condition (-16 V for 60 s)
Proper energy capability
Single demagnetization pulse
Repetitive demagnetization pulse
An example of external clamping circuitry (compatible with all above listed requirements) is
shown on Figure 77.
Figure 77. Example of external clamping circuitry
It is a combination of standard freewheeling diode and active reverse battery protection with
N-channel MOSFET (introduced in previous reverse battery protection chapter). Since the
anode of the diode is connected to the source of the MOSFET, it is protected (disconnected)
during reverse battery condition or negative ISO pulse. In normal operation conditions it
behaves like a standard freewheeling diode (connected in parallel with load). By using a
standard silicon diode, the demagnetization voltage is reduced from –32 V (a typical
VDEMAG of M0-7 device at VBAT = 14 V) to approximately –1 V (depending on forward
voltage of the diode and the voltage drop on the MOSFET). This has an influence to the
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Load compatibility UM1922
104/196 UM1922 Rev 2
demagnetization time (lowering |VDEMAG| increasing TDEMAG), as can be derived from
the TDEMAG equation.
Component selection:
MOSFET Q1:
According to ISO pulse requirements – see reverse battery protection chapter
Drain current (pulsed) IDM: IDM(a) > Load current
Diode DF:
Peak repetitive reverse voltage VRRM: VRRM > 52 V
(must not conduct during positive transient on the output limited by the
VCC_GND clamp VCLAMP_max = 52 V)
Non-repetitive peak forward surge current IFSM: IFSM > Load current
This parameter must be aligned with TDEMAG
Average rectified forward current IF(AV): IFAV > (Average clamp current in repetitive
operation)
Limited by max. junction temperature
Experimental verification of described clamping circuitry
Check the freewheeling operation at different conditions (different duty cycle in repetitive
operation, negative ISO pulse, loss of VCC).
VBAT
: 14 V
Temperature: 25 °C
Device: VND7040AJ
Load: 2 mH, 5.5
a. Limited by safe operating area according to TDEMAG (single pulse).
Limited by max. junction temperature (repetitive pulses).
UM1922 Rev 2 105/196
UM1922 Load compatibility
195
Figure 78. Test setup-verification of new external clamp proposal
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106/196 UM1922 Rev 2
Figure 79. PWM 50% at 100 Hz, 2 mH / 5.5 (VND7040AJ)
Repetitive operation – PWM 80 % at 400 Hz (the demagnetization time is longer than the
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