PIC32MM0064GPL036 Family Datasheet by Microchip Technology

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6‘ MICROCHIP
2015-2018 Microchip Technology Inc. DS60001324C-page 1
PIC32MM0064GPL036 FAMILY
Operating Conditions
2.0V to 3.6V, -40°C to +125°C, DC to 25 MHz
2.0V to 3.6V, -40°C to +85°C, DC to 25 MHz
Low-Power Modes
Low-Power modes:
- Idle: CPU off, peripherals run from system clock
- Sleep: CPU and peripherals off:
- Fast wake-up Sleep with retention
- Low-power Sleep with retention
•0.5 μA Sleep Current for Regulator Retention mode and
5 μA for Regulator Standby mode
On-Chip 1.8V Voltage Regulator (VREG)
On-Chip Ultra Low-Power Retention Regulator
High-Performance 32-Bit RISC CPU
microAptiv™ UC 32-Bit Core with 5-Stage Pipeline
microMIPS™ Instruction Set for 35% Smaller Code and
98% Performance compared to MIPS32 Instructions
DC-25 MHz Operating Frequency
3.17 CoreMark
®
/MHz (79 CoreMark) Performance
1.53 DMIPS/MHz (37 DMIPS) (Dhrystone 2.1) Performance
16-Bit/32-Bit Wide Instructions with 32-Bit Wide Data Path
Two Sets of 32 Core Register Files (32-bit) to Reduce
Interrupt Latency
Single-Cycle 32x16 Multiply and Two-Cycle 32x32 Multiply
Hardware Divide Unit
64-Bit, Zero Wait State Flash with ECC to Maximize
Endurance/Retention
Microcontroller Features
Low Pin Count Packages, Ranging from 20 to 36 Pins,
including UQFN as Small as 4x4 mm
Up to 64K Flash Memory:
- 20,000 erase/write cycle endurance
- 20 years minimum data retention
- Self-programmable under software control
Up to 8K Data Memory
Pin-Compatible with Most PIC24 MCU/dsPIC
®
DSC Devices
Multiple Interrupt Vectors with Individually
Programmable Priority
Fail-Safe Clock Monitor mode
Configurable Watchdog Timer with On-Chip, Low-Power
RC Oscillator
Programmable Code Protection
Selectable Oscillator Options including:
- High-precision, 8 MHz internal Fast RC (FRC) oscillator
- High-speed crystal/resonator oscillator or external clock
- 2x/3x/4x/6x/12x/24x PLL, which can be clocked from the
FRC or primary oscillator
Peripheral Features
Atomic Set, Clear and Invert Operation on Select
Peripheral Registers
High-Current Sink/Source 11 mA/16 mA on All Ports
Independent, Low-Power 32 kHz Timer Oscillator
Two 4-Wire SPI modules (up to 25 MHz non-PPS,
20 MHz PPS):
- 16-byte FIFO
-I
2
S mode
Two UARTs:
- RS-232, RS-485 and LIN/J2602 support
- IrDA
®
with on-chip hardware encoder and decoder
External Edge and Level Change Interrupt on All Ports
CRC module
Hardware Real-Time Clock and Calendar (RTCC)
Up to 20 Peripheral Pin Select (PPS) Remappable Pins
Seven Total 16-Bit Timers:
- Timer1: Dedicated 16-bit timer/counter
- Two additional 16-bit timers in each MCCP and SCCP
module
Capture/Compare/PWM/Timer modules:
- Two 16-bit timers or one 32-bit timer in each module
- PWM resolution down to 21 ns
- One Multiple Output (MCCP) module:
- Flexible configuration as PWM, input capture, output
compare or timers
- Six PWM outputs
- Programmable dead time
- Auto-shutdown
- Two Single Output (SCCP) modules:
- Flexible configuration as PWM, input capture, output
compare or timers
- Single PWM output
Reference Clock Output (REFO)
Two Configurable Logic Cells (CLC) with Internal
Connections to Select Peripherals and PPS
Debug Features
Two Programming and Debugging Interfaces:
- 2-wire ICSP™ interface with non-intrusive access
and real-time data exchange with application
-4-wire MIPS
®
standard Enhanced JTAG interface
IEEE Standard 1149.2 Compatible (JTAG) Boundary Scan
32-Bit Flash Microcontroller with MIPS32
®
microAptiv™ UC Core
with Low Power and Low Pin Count
PIC32MM0064GPL036 FAMILY
DS60001324C-page 2 2015-2018 Microchip Technology Inc.
Analog Features
Two Analog Comparators with Input Multiplexing
Programmable High/Low-Voltage Detect (HLVD)
5-Bit DAC with Output Pin
Up to 14-Channel, Software-Selectable 10/12-Bit SAR
Analog-to-Digital Converter (ADC):
- 12-bit, up to 222k samples/second conversion rate
- 10-bit, up to 250k samples/second conversion rate
- Sleep mode operation
- Band gap reference input feature
- Windowed threshold compare feature
- Auto-scan feature
Brown-out Reset (BOR)
TABLE 1: PIC32MM0064GPL036 FAMILY DEVICES
Device
Pins
Program Memory (Kbytes)
Data Memory (Kbytes)
General Purpose I/O/PPS
16-Bit Timers Maximum
PWM Outputs Maximum
Remappable
Peripherals
10/12-Bit ADC (Channels)
Comparators
CRC
RTCC
JTAG
Packages
UART
(1)
/LIN/J2602
16-Bit Timers
MCCP
(3)
SCCP
(4)
CLC
SPI
(2)
/I
2
S
PIC32MM0016GPL020 20 16 416/16 7 8 2 1 1 2 2 2 11 2Yes Yes Yes SSOP/QFN
PIC32MM0032GPL020 20 32 816/16 7 8 2 1 1 2 2 2 11 2Yes Yes Yes SSOP/QFN
PIC32MM0064GPL020 20 64 816/16 7 8 2 1 1 2 2 2 11 2Yes Yes Yes SSOP/QFN
PIC32MM0016GPL028 28 16 422/19 7 8 2 1 1 2 2 2 12 2Yes Yes Yes SSOP/SOIC/
QFN/UQFN
PIC32MM0032GPL028 28 32 822/19 7 8 2 1 1 2 2 2 12 2Yes Yes Yes SSOP/ SOIC/
QFN/UQFN
PIC32MM0064GPL028 28 64 822/19 7 8 2 1 1 2 2 2 12 2Yes Yes Yes SPDIP/SSOP/
SOIC/QFN/
UQFN
PIC32MM0016GPL036 36/40 16 429/20 7 8 2 1 1 2 2 2 14 2Yes Yes Yes VQFN/UQFN
PIC32MM0032GPL036 36/40 32 829/20 7 8 2 1 1 2 2 2 14 2Yes Yes Yes VQFN/UQFN
PIC32MM0064GPL036 36/40 64 829/20 7 8 2 1 1 2 2 2 14 2Yes Yes Yes VQFN/UQFN
Note 1: UART1 has assigned pins. UART2 is remappable.
2: SPI1 has assigned pins. SPI2 is remappable.
3: MCCP can be configured as a PWM with up to 6 outputs, input capture, output compare, 2 x 16-bit timers or
1 x 32-bit timer.
4: SCCP can be configured as a PWM with 1 output, input capture, output compare, 2 x 16-bit timers or 1 x 32-bit timer.
jjjjjjjlij M O CCCCCCCCCC
2015-2018 Microchip Technology Inc. DS60001324C-page 3
PIC32MM0064GPL036 FAMILY
Pin Diagrams
20-Pin SSOP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
MCLR
PGEC2/RP1/RA0
PGED2/RP2/RA1
PGED1/RP14/RB0
PGEC1/RP15/RB1
RP16/RB2
CLKI/RP3/RA2
CLKO/RP4/RA3
(1)
PGED3/SOSCI/RP5/RB4
PGEC3/SOSCO/RP6/RA4 RP11/RB7
RP7/RB8
(1)
RP8/RB9
(1)
V
CAP
RP12/RB12
RP13/RB13
RP9/RB14
RP10/RB15
(1)
AV
SS
/V
SS
AV
DD
/V
DD
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
PIC32MMXXXXGPL020
TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 20-PIN SSOP DEVICES
Pin Function Pin Function
1MCLR 11 RP11/RB7
2PGEC2/VREF+/AN0/RP1/OCM1E/INT3/RA0 12 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)
3PGED2/VREF-/AN1/RP2/OCM1F/RA1 13 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/
INT2/RB9(1)
4PGED1/AN2/C1IND/C2INB/RP14/RB0 14 VCAP
5PGEC1/AN3/C1INC/C2INA/RP15/RB1 15 TDO/AN7/LVDIN/RP12/RB12
6AN4/RP16/RB2 16 TDI/AN8/RP13/RB13
7OSC1/CLKI/AN5/C1INB/RP3/OCM1C/RA2 17 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
8OSC2/CLKO/AN6/C1INA/RP4/OCM1D/RA3(1)18 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
9PGED3/SOSCI/RP5/RB4 19 AVSS/VSS
10 PGEC3/SOSCO/SCLKI/RP6/PWRLCLK/RA4 20 AVDD/VDD
Note 1: Pin has an increased current drive strength.
r—u—u—u—‘m r—u—u—u—‘m l_Al_Al_1-_- chs G/mRTs
PIC32MM0064GPL036 FAMILY
DS60001324C-page 4 2015-2018 Microchip Technology Inc.
Pin Diagrams (Continued)
20-Pin QFN
(2)
PGEC1/RP15/RB1
RP16/RB2
CLKI/RP3/RA2
CLKO/RP4/RA3
(1)
PGED1/RP14/RB0
PGED3/SOSCI/RP5/RB4
PGEC3/SOSCO/RP6/RA4
RP11/RB7
RP7/RB8
(1)
RP8/RB9
(1)
RP12/RB12
RP13/RB13
V
CAP
RP9/RB14
RP10/RB15
(1)
AV
SS
/V
SS
PGEC2/RP1/RA0
AV
DD
/V
DD
MCLR
18 17 1620 19
PGED2/RP2/RA1
PIC32MMXXXXGPL020
2
3
1
5
4
14
13
15
11
12
891067
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
2: The back side thermal pad is not electrically connected.
TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 20-PIN QFN DEVICES
Pin Function Pin Function
1PGED1/AN2/C1IND/C2INB/RP14/RB0 11 VCAP
2PGEC1/AN3/C1INC/C2INA/RP15/RB1 12 TDO/AN7/LVDIN/RP12/RB12
3AN4/RP16/RB2 13 TDI/AN8/RP13/RB13
4OSC1/CLKI/AN5/C1INB/RP3/OCM1C/RA2 14 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
5OSC2/CLKO/AN6/C1INA/RP4/OCM1D/RA3(1)15 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
6PGED3/SOSCI/RP5/RB4 16 AVSS/VSS
7PGEC3/SOSCO/SCLKI/RP6/PWRLCLK/RA4 17 AVDD/VDD
8RP11/RB7 18 MCLR
9TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)19 PGEC2/VREF+/AN0/RP1/OCM1E/INT3/RA0
10 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/
C2OUT/OCM1B/INT2/RB9(1)20 PGED2/VREF-/AN1/RP2/OCM1F/RA1
Note 1: Pin has an increased current drive strength.
2015-2018 Microchip Technology Inc. DS60001324C-page 5
PIC32MM0064GPL036 FAMILY
Pin Diagrams (Continued)
28-Pin SPDIP
(2)
/SSOP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR
RP1/RA0
RP2/RA1
PGED1/RP14/RB0
PGEC1/RP15/RB1
RP16/RB2
RB3
V
SS
CLKI/RP3/RA2
CLKO/RP4/RA3
(1)
SOSCI/RP5/RB4
SOSCO/RP6/RA4
V
DD
PGED3/RB5 PGEC3/RB6
RP11/RB7
RP7/RB8
(1)
RP8/RB9
(1)
RP19/RC9
V
CAP
PGED2/RP17/RB10
PGEC2/RP18/RB11
RP12/RB12
RP13/RB13
RP9/RB14
RP10/RB15
(1)
V
SS
/AV
SS
V
DD
/AV
DD
PIC32MMXXXXGPL028
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
2: Only PIC32MM0064GPL028 comes in a 28-pin SPDIP package.
TABLE 4: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 28-PIN SPDIP/SSOP/SOIC DEVICES
Pin Function Pin Function
1MCLR 15 PGEC3/RB6
2 VREF+/AN0/RP1/OCM1E/INT3/RA0 16 RP11/RB7
3 VREF-/AN1/RP2/OCM1F/RA1 17 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)
4PGED1/AN2/C1IND/C2INB/RP14/RB0 18 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/INT2/RB9(1)
5PGEC1/AN3/C1INC/C2INA/RP15/RB1 19 RP19/RC9
6AN4/C1INB/RP16/RB2 20 VCAP
7AN11/C1INA/RB3 21 PGED2/TDO/RP17/RB10
8 VSS 22 PGEC2/TDI/RP18/RB11
9OSC1/CLKI/AN5/RP3/OCM1C/RA2 23 AN7/LVDIN/RP12/RB12
10 OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)24 AN8/RP13/RB13
11 SOSCI/RP5/RB4 25 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
12 SOSCO/SCLKI/RP6/PWRLCLK/RA4 26 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
13 VDD 27 VSS/AVSS
14 PGED3/RB5 28 VDD/AVDD
Note 1: Pin has an increased current drive strength.
7_\7_\7_\V_\7_\7_\7_\ r—u—u—u—u—u—ufi “uuuuu
PIC32MM0064GPL036 FAMILY
DS60001324C-page 6 2015-2018 Microchip Technology Inc.
Pin Diagrams (Continued)
28-Pin QFN/UQFN
(2)
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
5
4
PGEC1/RP15/RB1
RP16/RB2
RB3
V
SS
CLKI/RP3/RA2
CLKO/RP4/RA3
(1)
PGED1/RP14/RB0
SOSCI/RP5/RB4
SOSCO/RP6/RA4
V
DD
PGED3/RB5
PGEC3/RB6
RP11/RB7
RP7/RB8
(1)
RP8/RB9
(1)
RP19/RC9
V
CAP
PGED2/RP17/RB10
PGEC2/RP18/RB11
RP12/RB12
RP13/RB13
RP9/RB14
RP10/RB15
(1)
V
SS
/AV
SS
V
DD
/AV
DD
MCLR
RP1/RA0
RP2/RA1
PIC32MMXXXXGPL028
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
2: The back side thermal pad is not electrically connected.
TABLE 5: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 28-PIN QFN/UQFN DEVICES
Pin Function Pin Function
1PGED1/AN2/C1IND/C2INB/RP14/RB0 15 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/
INT2/RB9(1)
2PGEC1/AN3/C1INC/C2INA/RP15/RB1 16 RP19/RC9
3AN4/C1INB/RP16/RB2 17 VCAP
4AN11/C1INA/RB3 18 PGED2/TDO/RP17/RB10
5 VSS 19 PGEC2/TDI/RP18/RB11
6OSC1/CLKI/AN5/RP3/OCM1C/RA2 20 AN7/LVDIN/RP12/RB12
7OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)21 AN8/RP13/RB13
8SOSCI/RP5/RB4 22 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
9SOSCO/SCLKI/RP6/PWRLCLK/RA4 23 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
10 VDD 24 VSS/AVSS
11 PGED3/RB5 25 VDD/AVDD
12 PGEC3/RB6 26 MCLR
13 RP11/RB7 27 VREF+/AN0/RP1/OCM1E/INT3/RA0
14 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)28 VREF-/AN1/RP2/OCM1F/RA1
Note 1: Pin has an increased current drive strength.
r—u—u—u—u—u—u—u—‘m r—u—u—u—u—u—u—u—‘m -x_:-x_n_u_n_n_n_. L_1-\_H_H_A-—-\_A- G/mRTs TCK/RP7/U1CTS
2015-2018 Microchip Technology Inc. DS60001324C-page 7
PIC32MM0064GPL036 FAMILY
Pin Diagrams (Continued)
36-Pin VQFN
(2)
RP16/RB2
RB3
RC0
RC1
RC2
V
SS
CLKI/RP3/RA2
CLKO/RP4/RA3
(1)
SOSCI/RP5/RB4
SOSCO/RP6/RA4
RP20/RA9
V
SS
V
DD
RC3
PGED3/RB5
PGEC3/RB6
RP11/RB7
RP7/RB8
(1)
RP8/RB9
(1)
RC8
RP19/RC9
V
CAP
V
DD
PGEC2/RP18/RB11
RP12/RB12
PGED2/RP17/RB10
RP13/RB13
RP9/RB14
RP10/RB15
(1)
V
SS
/AV
SS
V
DD
/AV
DD
MCLR
RP1/RA0
RP2/RA1
PGED1/RP14/RB0
PGEC1/RP15/RB1
9
1
2
3
4
5
16
17
18
10
11
12
13
31
7
6
36
35
34
33
32
14
15
24
25
26
27
19
20
21
22
23
29
28
8
30
PIC32MMXXXXGPL036
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
2: The back side thermal pad is not electrically connected.
TABLE 6: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 36-PIN VQFN DEVICES
Pin Function Pin Function
1AN4/C1INB/RP16/RB2 19 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/C2OUT/OCM1B/INT2/RB9(1)
2AN11/C1INA/RB3 20 RC8
3AN12/RC0 21 RP19/RC9
4AN13/RC1 22 VCAP
5RC2 23 VDD
6 VSS 24 PGED2/TDO/RP17/RB10
7OSC1/CLKI/AN5/RP3/OCM1C/RA2 25 PGEC2/TDI/RP18/RB11
8OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)26 AN7/LVDIN/RP12/RB12
9SOSCI/RP5/RB4 27 AN8/RP13/RB13
10 SOSCO/SCLKI/RP6/PWRLCLK/RA4 28 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
11 RP20/RA9 29 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
12 VSS 30 VSS/AVSS
13 VDD 31 VDD/AVDD
14 RC3 32 MCLR
15 PGED3/RB5 33 VREF+/AN0/RP1/OCM1E/INT3/RA0
16 PGEC3/RB6 34 VREF-/AN1/RP2/OCM1F/RA1
17 RP11/RB7 35 PGED1/AN2/C1IND/C2INB/RP14/RB0
18 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)36 PGEC1/AN3/C1INC/C2INA/RP15/RB1
Note 1: Pin has an increased current drive strength.
r—u—H—w—u—u—H—u—u—‘m r—u—H—u—u—u—H—u—H—‘m l_l-l_ll_ll_ll_ll_ll_ll_ll_l -l_Al_ll_A-_-l_/-l_/- 7/chs G/mRTs
PIC32MM0064GPL036 FAMILY
DS60001324C-page 8 2015-2018 Microchip Technology Inc.
Pin Diagrams (Continued)
40-Pin UQFN
(2)
RP16/RB2
RB3
RC0
RC1
RC2
V
SS
OSCI/RP3/RA2
OSCO/RP4/RA3(1)
SOSCI/RP5/RB4
SOSCO/RP6/RA4
RP20/RA9
V
SS
V
DD
RC3
RB5/PGED3
RB6/PGEC3
RP11/RB7
RP7/RB8
(1)
N/C
RP8
/RB9
(1)
RC8
RP19/RC9
N/C
V
CAP
N/C
V
DD
RP17/RB10/PGED2
RP18/RB11/PGEC2
RP12/RB12
RP13/RB13
RP9
/RB14
RP10
/RB15(1)
V
SS
/AV
SS
V
DD
/AV
DD
MCLR
RP1
/RA0
RP2
/RA1
RP14
/RB0/PGED1
RP15
/RB1/PGEC1
N/C
PIC32MMXXXXGPL036
9
1
2
3
4
5
17
18
19
11
12
13
14
34
7
6
39
38
37
36
35
15
16
26
27
28
29
21
22
23
24
25
32
31
8
33
10
20
30
40
Legend: Shaded pins are up to 5V tolerant.
Note 1: Pin has an increased current drive strength. Refer to Section 26.0 “Electrical Characteristics” for details.
2: The back side thermal pad is not electrically connected.
TABLE 7: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 40-PIN UQFN DEVICES
Pin Function Pin Function
1AN4/C1INB/RP16/RB2 21 RC8
2AN11/C1INA/RB3 22 RP19/RC9
3AN12/RC0 23 N/C
4AN13/RC1 24 VCAP
5RC2 25 N/C
6 VSS 26 VDD
7OSC1/CLKI/AN5/RP3/OCM1C/RA2 27 PGED2/TDO/RP17/RB10
8OSC2/CLKO/AN6/RP4/OCM1D/RA3(1)28 PGEC2/TDI/RP18/RB11
9SOSCI/RP5/RB4 29 AN7/LVDIN/RP12/RB12
10 SOSCO/SCLKI/RP6/PWRLCLK/RA4 30 AN8/RP13/RB13
11 RP20/RA9 31 CDAC1/AN9/RP9/RTCC/U1TX/SDI1/C1OUT/INT1/RB14
12 VSS 32 AN10/REFCLKO/RP10/U1RX/SS1/FSYNC1/INT0/RB15(1)
13 VDD 33 VSS/AVSS
14 RC3 34 VDD/AVDD
15 PGED3/RB5 35 MCLR
16 PGEC3/RB6 36 VREF+/AN0/RP1/OCM1E/INT3/RA0
17 RP11/RB7 37 VREF-/AN1/RP2/OCM1F/RA1
18 TCK/RP7/U1CTS/SCK1/OCM1A/RB8(1)38 PGED1/AN2/C1IND/C2INB/RP14/RB0
19 N/C 39 PGEC1/AN3/C1INC/C2INA/RP15/RB1
20 TMS/REFCLKI/RP8/T1CK/T1G/U1RTS/U1BCLK/SDO1/
C2OUT/OCM1B/INT2/RB9(1)40 N/C
Note 1: Pin has an increased current drive strength.
2015-2018 Microchip Technology Inc. DS60001324C-page 9
PIC32MM0064GPL036 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with 32-Bit Microcontrollers........................................................................................................ 19
3.0 CPU............................................................................................................................................................................................ 23
4.0 Memory Organization ................................................................................................................................................................. 33
5.0 Flash Program Memory.............................................................................................................................................................. 37
6.0 Resets ........................................................................................................................................................................................ 45
7.0 CPU Exceptions and Interrupt Controller ................................................................................................................................... 51
8.0 Oscillator Configuration .............................................................................................................................................................. 65
9.0 I/O Ports ..................................................................................................................................................................................... 79
10.0 Timer1 ........................................................................................................................................................................................ 89
11.0 Watchdog Timer (WDT) ............................................................................................................................................................. 93
12.0 Capture/Compare/PWM/Timer Modules (MCCP and SCCP) .................................................................................................... 97
13.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I
2
S)....................................................................................................... 111
14.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 119
15.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 125
16.0 12-Bit Analog-to-Digital Converter with Threshold Detect........................................................................................................ 135
17.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 149
18.0 Configurable Logic Cell (CLC).................................................................................................................................................. 153
19.0 Comparator .............................................................................................................................................................................. 165
20.0 Control Digital-to-Analog Converter (CDAC)............................................................................................................................ 171
21.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 175
22.0 Power-Saving Features ........................................................................................................................................................... 179
23.0 Special Features ...................................................................................................................................................................... 183
24.0 Development Support............................................................................................................................................................... 201
25.0 Instruction Set .......................................................................................................................................................................... 205
26.0 Electrical Characteristics.......................................................................................................................................................... 207
27.0 Packaging Information.............................................................................................................................................................. 235
Appendix A: Revision History............................................................................................................................................................. 259
Index .................................................................................................................................................................................................. 261
The Microchip Web Site..................................................................................................................................................................... 265
Customer Change Notification Service .............................................................................................................................................. 265
Customer Support .............................................................................................................................................................................. 265
Product Identification System ............................................................................................................................................................ 267
PIC32MM0064GPL036 FAMILY
DS60001324C-page 10 2015-2018 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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2015-2018 Microchip Technology Inc. DS60001324C-page 11
PIC32MM0064GPL036 FAMILY
Referenced Sources
This device data sheet is based on the following
individual sections of the “PIC32 Family Reference
Manual. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Section 1. “Introduction” (DS60001127)
Section 5. “Flash Programming” (DS60001121)
Section 7. “Resets” (DS60001118)
Section 8. “Interrupts” (DS60001108)
Section 10. “Power-Saving Modes” (DS60001130)
Section 14. “Timers” (DS60001105)
Section 19. “Comparator” (DS60001110)
Section 21. “UART” (DS60001107)
Section 23. “Serial Peripheral Interface (SPI)” (DS61106)
Section 25. “12-Bit Analog-to-Digital Converter (ADC) with Threshold Detect” (DS60001359)
Section 28. “RTCC with Timestamp” (DS60001362)
Section 30. “Capture/Compare/PWM/Timer (MCCP and SCCP)” (DS60001381)
Section 33. “Programming and Diagnostics” (DS61129)
Section 36. “Configurable Logic Cell” (DS60001363)
Section 45. “Control Digital-to-Analog Converter (CDAC)” (DS60001327)
Section 50. “CPU for Devices with MIPS32
®
microAptiv™ and M-Class Cores” (DS60001192)
Section 59. “Oscillators with DCO” (DS60001329)
Section 60. “32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS60001336)
Section 62. “Dual Watchdog Timer” (DS60001365)
Note: To access the documents listed below,
browse the documentation section of the
Microchip web site (www.microchip.com).
PIC32MM0064GPL036 FAMILY
DS60001324C-page 12 2015-2018 Microchip Technology Inc.
NOTES:
X—b 3 E: % m
2015-2018 Microchip Technology Inc. DS60001324C-page 13
PIC32MM0064GPL036 FAMILY
1.0 DEVICE OVERVIEW
This data sheet contains device-specific information for
the PIC32MM0064GPL036 family devices.
Figure 1-1 illustrates a general block diagram of the core
and peripheral modules in the PIC32MM0064GPL036
family of devices.
Table 1-1 lists the pinout I/O descriptions for the pins
shown in the device pin tables.
FIGURE 1-1: PIC32MM0064GPL036 FAMILY BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32). The
information in this data sheet supersedes
the information in the FRM.
UART1,2
Comparators
PORTA
PORTB
JTAG Priority
ICD
IS DS
EJTAG INT
Bus Matrix
Line Buffer RAM Peripheral Bridge
64
64-Bit Wide Flash
32
32 32
Peripheral Bus Clocked by PBCLK
Program Flash Memory Controller
32
Module
32 32
Interrupt
Controller
Boundary
PORTC
CRC
5-Bit DAC
SPI1,2
SCCP2,3
MCCP1
OSC1/CLKI
OSC2/CLKO
VDD,
Timing
Generation
VSS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Precision
Reference
Band Gap
Regulator
Voltage
VCAP
Primary
Dividers
SYSCLK
PBCLK (1:1 with SYSCLK)
Peripheral Bus Clocked by PBCLK
PLL
RTCC
12-Bit ADC
Timer1
32
32
Oscillator
FRC/LPRC
Oscillators
SOSCO/SCLKI Secondary
Oscillator
AVDD, AVSS
I/O Change
Notification
HLVD
MIPS32® microAptiv™ UC
CPU Core
SOSCI
Scan
PIC32MM0064GPL036 FAMILY
DS60001324C-page 14 2015-2018 Microchip Technology Inc.
TABLE 1-1: PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION
Pin Name
Pin Number
Pin
Type Buffer
Type Description
20-Pin
QFN 20-Pin
SSOP
28-Pin
QFN/
UQFN
28-Pin
SPDIP/
SSOP/SOIC
36-Pin
VQFN 40-Pin
UQFN
AN0 19 2 27 2 33 36 I ANA Analog-to-Digital Converter input channels
AN1 20 3 28 3 34 37 I ANA
AN2 1 4 1 4 35 38 I ANA
AN3 2 5 2 5 36 39 I ANA
AN4 3 6 3 6 1 1 I ANA
AN5 4 7 6 9 7 7 I ANA
AN6 5 8 7 10 8 8 I ANA
AN7 12 15 20 23 26 29 I ANA
AN8 13 16 21 24 27 30 I ANA
AN9 14 17 22 25 28 31 I ANA
AN10 15 18 23 26 29 32 I ANA
AN11 4 7 2 2 I ANA
AN12 3 3 I ANA
AN13 4 4 I ANA
AV
DD
17 20 25 28 31 34 P Analog modules power supply
(1)
AV
SS
16 19 24 27 30 33 P Analog modules ground
(2)
C1INA 5 8 4 7 2 2 I ANA Comparator 1 Input A
C1INB 4 7 3 6 1 1 I ANA Comparator 1 Input B
C1INC 2 5 2 5 36 39 I ANA Comparator 1 Input C
C1IND 1 4 1 4 35 38 I ANA Comparator 1 Input D
C1OUT 14 17 22 25 28 31 O DIG Comparator 1 output
C2INA 2 5 2 5 36 39 I ANA Comparator 2 Input A
C2INB 1 4 1 4 35 38 I ANA Comparator 2 Input B
C2OUT 10 13 15 18 19 20 O DIG Comparator 2 output
CLKI 4 7 6 9 7 7 I ST External Clock input (EC mode)
CLKO 5 8 7 10 8 8 O DIG System clock output
CDAC1 14 17 22 25 28 31 O ANA Digital-to-Analog Converter output
FSYNC1 15 18 23 26 29 32 I/O ST/DIG SPI1 frame signal input or output
INT0 15 18 23 26 29 32 I ST External Interrupt 0
INT1 14 17 22 25 28 31 I ST External Interrupt 1
INT2 10 13 15 18 19 20 I ST External Interrupt 2
INT3 19 2 27 2 33 36 I ST External Interrupt 3
LVDIN 12 15 20 23 26 29 I ANA High/Low-Voltage Detect input
MCLR 18 1 26 1 32 35 I ST Master Clear (device Reset)
OCM1A 9 12 14 17 18 18 O DIG MCCP1 Output A
OCM1B 10 13 15 18 19 20 O DIG MCCP1 Output B
OCM1C 4 7 6 9 7 7 O DIG MCCP1 Output C
OCM1D 5 8 7 10 8 8 O DIG MCCP1 Output D
OCM1E 19 2 27 2 33 36 O DIG MCCP1 Output E
OCM1F 20 3 28 3 34 37 O DIG MCCP1 Output F
OSC1 4 7 6 9 7 7 Primary Oscillator crystal
OSC2 5 8 7 10 8 8 Primary Oscillator crystal
Legend: ST = Schmitt Trigger input buffer DIG = Digital input/output ANA = Analog level input/output
Note 1: V
DD
and AV
DD
are internally connected.
2: V
SS
and AV
SS
are internally connected.
2015-2018 Microchip Technology Inc. DS60001324C-page 15
PIC32MM0064GPL036 FAMILY
PGEC1 2 5 2 5 36 39 I ST ICSP™ Port 1 programming clock input
PGEC2 19 2 19 22 25 28 I ST ICSP Port 2 programming clock input
PGEC3 7 10 12 15 16 16 I ST ICSP Port 3 programming clock input
PGED1 1 4 1 4 35 38 I/O ST/DIG ICSP Port 1 programming data
PGED2 20 3 18 21 24 27 I/O ST/DIG ICSP Port 2 programming data
PGED3 6 9 11 14 15 15 I/O ST/DIG ICSP Port 3 programming data
PWRLCLK 7 10 9 12 10 10 I ST Real-Time Clock 50/60 Hz clock input
RA0 19 2 27 2 33 36 I/O ST/DIG PORTA digital I/O
RA1 20 3 28 3 34 37 I/O ST/DIG PORTA digital I/O
RA2 4 7 6 9 7 7 I/O ST/DIG PORTA digital I/O
RA3 5 8 7 10 8 8 I/O ST/DIG PORTA digital I/O
RA4 7 10 9 12 10 10 I/O ST/DIG PORTA digital I/O
RA9 11 11 I/O ST/DIG PORTA digital I/O
RB0 1 4 1 4 35 38 I/O ST/DIG PORTB digital I/O
RB1 2 5 2 5 36 39 I/O ST/DIG PORTB digital I/O
RB2 3 6 3 6 1 1 I/O ST/DIG PORTB digital I/O
RB3 4 7 2 2 I/O ST/DIG PORTB digital I/O
RB4 6 9 8 11 9 9 I/O ST/DIG PORTB digital I/O
RB5 11 14 15 15 I/O ST/DIG PORTB digital I/O
RB6 12 15 16 16 I/O ST/DIG PORTB digital I/O
RB7 8 11 13 16 17 17 I/O ST/DIG PORTB digital I/O
RB8 9 12 14 17 18 18 I/O ST/DIG PORTB digital I/O
RB9 10 13 15 18 19 20 I/O ST/DIG PORTB digital I/O
RB10 18 21 24 27 I/O ST/DIG PORTB digital I/O
RB11 19 22 25 28 I/O ST/DIG PORTB digital I/O
RB12 12 15 20 23 26 29 I/O ST/DIG PORTB digital I/O
RB13 13 16 21 24 27 30 I/O ST/DIG PORTB digital I/O
RB14 14 17 22 25 28 31 I/O ST/DIG PORTB digital I/O
RB15 15 18 23 26 29 32 I/O ST/DIG PORTB digital I/O
RC0 3 3 I/O ST/DIG PORTC digital I/O
RC1 4 4 I/O ST/DIG PORTC digital I/O
RC2 5 5 I/O ST/DIG PORTC digital I/O
RC3 14 14 I/O ST/DIG PORTC digital I/O
RC8 20 21 I/O ST/DIG PORTC digital I/O
RC9 16 19 21 22 I/O ST/DIG PORTC digital I/O
REFCLKI 10 13 15 18 19 20 I ST Reference clock input
REFCLKO 15 18 23 26 29 32 O DIG Reference clock output
TABLE 1-1: PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin Name
Pin Number
Pin
Type Buffer
Type Description
20-Pin
QFN 20-Pin
SSOP
28-Pin
QFN/
UQFN
28-Pin
SPDIP/
SSOP/SOIC
36-Pin
VQFN 40-Pin
UQFN
Legend: ST = Schmitt Trigger input buffer DIG = Digital input/output ANA = Analog level input/output
Note 1: V
DD
and AV
DD
are internally connected.
2: V
SS
and AV
SS
are internally connected.
PIC32MM0064GPL036 FAMILY
DS60001324C-page 16 2015-2018 Microchip Technology Inc.
RP1 19 2 27 2 33 36 I/O ST/DIG Remappable peripherals (input or output)
RP2 20 3 28 3 34 37 I/O ST/DIG
RP3 4 7 6 9 7 7 I/O ST/DIG
RP4 5 8 7 10 8 8 I/O ST/DIG
RP5 6 9 8 11 9 9 I/O ST/DIG
RP6 7 10 9 12 10 10 I/O ST/DIG
RP7 9 12 14 17 18 18 I/O ST/DIG
RP8 10 13 15 18 19 20 I/O ST/DIG
RP9 14 17 22 25 28 31 I/O ST/DIG
RP10 15 18 23 26 29 32 I/O ST/DIG
RP11 8 11 13 16 17 17 I/O ST/DIG
RP12 12 15 20 23 26 29 I/O ST/DIG
RP13 13 16 21 24 27 30 I/O ST/DIG
RP14 1 4 1 4 35 38 I/O ST/DIG
RP15 2 5 2 5 36 39 I/O ST/DIG
RP16 3 6 3 6 1 1 I/O ST/DIG
RP17 18 21 24 27 I/O ST/DIG
RP18 19 22 25 28 I/O ST/DIG
RP19 16 19 21 22 I/O ST/DIG
RP20 11 11 I/O ST/DIG
RTCC 14 17 22 25 28 31 O DIG Real-Time Clock alarm/seconds output
SCK1 9 12 14 17 18 18 I/O ST/DIG SPI1 clock (input or output)
SCLKI 7 10 9 12 10 10 I ST Secondary Oscillator external clock input
SDI1 14 17 22 25 28 31 I ST SPI1 data input
SDO1 10 13 15 18 19 20 O DIG SPI1 data output
SOSCI 6 9 8 11 9 9 Secondary Oscillator crystal
SOSCO 7 10 9 12 10 10 Secondary Oscillator crystal
SS1 15 18 23 26 29 32 I ST SPI1 slave select input
T1CK 10 13 15 18 19 20 I ST Timer1 external clock input
T1G 10 13 15 18 19 20 I ST Timer1 clock gate input
TCK 9 12 14 17 18 18 I ST JTAG clock input
TDI 13 16 19 22 25 28 I ST JTAG data input
TDO 12 15 18 21 24 27 O DIG JTAG data output
TMS 10 13 15 18 19 20 I ST JTAG mode select input
U1BCLK 10 13 15 18 19 20 O DIG UART1 IrDA
®
16x baud clock output
U1CTS 9 12 14 17 18 18 I ST UART1 transmission control input
U1RTS 10 13 15 18 19 20 O DIG UART1 reception control output
U1RX 15 18 23 26 29 32 I ST UART1 receive data input
U1TX 14 17 22 25 28 31 O DIG UART1 transmit data output
TABLE 1-1: PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin Name
Pin Number
Pin
Type Buffer
Type Description
20-Pin
QFN 20-Pin
SSOP
28-Pin
QFN/
UQFN
28-Pin
SPDIP/
SSOP/SOIC
36-Pin
VQFN 40-Pin
UQFN
Legend: ST = Schmitt Trigger input buffer DIG = Digital input/output ANA = Analog level input/output
Note 1: V
DD
and AV
DD
are internally connected.
2: V
SS
and AV
SS
are internally connected.
2015-2018 Microchip Technology Inc. DS60001324C-page 17
PIC32MM0064GPL036 FAMILY
V
CAP
11 14 17 20 22 24 P Core voltage regulator filter capacitor
connection
V
DD
17 20 10,25 13,28 13,23,31 13,26,
34
P Digital modules power supply
(1)
V
REF
- 20 3 28 3 34 37 I ANA ADC negative reference
V
REF
+ 19 2 27 2 33 36 I ANA ADC and DAC positive reference
V
SS
16 19 5,24 8,27 6,12,30 6,12,
33
P Digital modules ground
(2)
TABLE 1-1: PIC32MM0064GPL036 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin Name
Pin Number
Pin
Type Buffer
Type Description
20-Pin
QFN 20-Pin
SSOP
28-Pin
QFN/
UQFN
28-Pin
SPDIP/
SSOP/SOIC
36-Pin
VQFN 40-Pin
UQFN
Legend: ST = Schmitt Trigger input buffer DIG = Digital input/output ANA = Analog level input/output
Note 1: V
DD
and AV
DD
are internally connected.
2: V
SS
and AV
SS
are internally connected.
PIC32MM0064GPL036 FAMILY
DS60001324C-page 18 2015-2018 Microchip Technology Inc.
NOTES:
2015-2018 Microchip Technology Inc. DS60001324C-page 19
PIC32MM0064GPL036 FAMILY
2.0 GUIDELINES FOR GETTING
STARTED WITH 32-BIT
MICROCONTROLLERS
2.1 Basic Connection Requirements
Getting started with the PIC32MM0064GPL036 family
of 32-bit Microcontrollers (MCUs) requires attention to
a minimal set of device pin connections before
proceeding with development. The following is a list of
pin names, which must always be connected:
•All V
DD
and V
SS
pins (see Section 2.2
“Decoupling Capacitors”)
•All AV
DD
and AV
SS
pins, even if the ADC module
is not used (see Section 2.2 “Decoupling
Capacitors”)
MCLR pin (see Section 2.3 “Master Clear
(MCLR) Pin”)
•V
CAP
pin (see Section 2.4 “Capacitor on
Internal Voltage Regulator (V
CAP
)”)
PGECx/PGEDx pins, used for In-Circuit Serial
Programming™ (ICSP™) and debugging
purposes (see Section 2.6 “ICSP Pins”)
OSC1 and OSC2 pins, when external oscillator
source is used (see Section 2.8 “External
Oscillator Pins”)
The following pin(s) may be required as well:
V
REF
+/V
REF
- pins, used when external voltage
reference for the ADC module is implemented.
2.2 Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as V
DD
, V
SS
, AV
DD
and AV
SS
, is required.
See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance frequency
in the range of 20 MHz and higher. It is further
recommended that ceramic capacitors be used.
Placement on the printed circuit board: The
decoupling capacitors should be placed as close to
the pins as possible. It is recommended that the
capacitors be placed on the same side of the board
as the device. If space is constricted, the capacitor
can be placed on another layer on the PCB using a
via; however, ensure that the trace length from the
pin to the capacitor is within one-quarter inch
(6 mm) in length.
Handling high-frequency noise: If the board is
experiencing high-frequency noise, upward of tens
of MHz, add a second ceramic-type capacitor in par-
allel to the above described decoupling capacitor.
The value of the second capacitor can be in the
range of 0.01 µF to 0.001 µF. Place this second
capacitor next to the primary decoupling capacitor.
In high-speed circuit designs, consider implement-
ing a decade pair of capacitances, as close to the
power and ground pins as possible. For example,
0.1 µF in parallel with 0.001 µF.
Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first, and
then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track inductance.
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
The information in this data sheet
supersedes the information in the FRM.
Note: The AV
DD
and AV
SS
pins must be
connected, regardless of ADC use and
the ADC voltage reference source.
The back side thermal pad, if present, is
not electrically connected.
MCLR MCLR MCLR
PIC32MM0064GPL036 FAMILY
DS60001324C-page 20 2015-2018 Microchip Technology Inc.
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTION
2.2.1 BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
2.3 Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
•Device Reset
Device Programming and Debugging
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (V
IH
and V
IL
) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor, C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
(1,2,3)
2.4 Capacitor on Internal Voltage
Regulator (VCAP)
A low-ESR (<1 Ohm) capacitor is required on the V
CAP
pin, which is used to stabilize the internal voltage regu-
lator output. The V
CAP
pin must not be connected to
V
DD
and must have a C
EFC
capacitor, with at least a 6V
rating, connected to ground. The type can be ceramic
or tantalum. The recommended value of the C
EFC
capacitor is 10 μF. On the printed circuit board, it should
be placed as close to the V
CAP
pin as possible. If the
board is experiencing high-frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor in
parallel to this capacitor. The value of the second
capacitor can be in the range of 0.01 μF to 0.001 μF.
PIC32
VDD
VSS
VSS/AVSS
VDD/AVDD
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
C
R
V
DD
MCLR
0.1 µF
Ceramic
R1
CEFC
10 µF
VCAP
Note 1: 470 R1 1 k will limit any current flowing into
MCLR from the external capacitor, C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
interfering with the debug/programmer tools.
2: The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3: No pull-ups or bypass capacitors are allowed on active
debug/program PGECx/PGEDx pins.
R1(1)
10k
VDD
MCLR
PIC32
1 k
0.1 µF(2)
PGECx(3)
PGEDx(3)
ICSP™
1
5
4
2
3
6
VDD
VSS
NC
R
C
2015-2018 Microchip Technology Inc. DS60001324C-page 21
PIC32MM0064GPL036 FAMILY
2.5 Voltage Regulator Pin (VCAP)
A low-ESR (< 5) capacitor is required on the V
CAP
pin
to stabilize the output voltage of the on-chip voltage
regulator. The V
CAP
pin must not be connected to V
DD
and must use a capacitor of 10 µF connected to ground.
The type can be ceramic or tantalum. Suitable examples
of capacitors are shown in Table 2-1. Capacitors with
equivalent specifications can be used.
The placement of this capacitor should be close to V
CAP
.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 26.0 “Electrical
Characteristics” for additional information.
Designers may use Figure 2-3 to evaluate ESR
equivalence of candidate devices.
FIGURE 2-3: FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED V
CAP
.
10
1
0.1
0.01
0.001 0.01 0.1 1 10 100 1000 10,000
Frequency (MHz)
ESR ()
Note: Typical data measurement at +25°C, 0V DC bias.
TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS
Make Part # Nominal
Capacitance Base Tolerance Rated Voltage Temp. Range
TDK C3216X7R1C106K 10 µF ±10% 16V -55 to +125°C
TDK C3216X5R1C106K 10 µF ±10% 16V -55 to +85°C
Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to +125°C
Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to +85°C
Murata GRM319R61C106KE15D 10 µF ±10% 16V -55 to +85°C
PIC32MM0064GPL036 FAMILY
DS60001324C-page 22 2015-2018 Microchip Technology Inc.
2.6 ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on
the device as short as possible. If the ICSP connec-
tor is expected to experience an ESD event, a series
resistor is recommended, with the value in the range
of a few tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin Input Voltage High
(V
IH
) and Input Voltage Low (V
IL
) requirements.
Ensure that the “Communication Channel Select”
(i.e., PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB
®
ICD 3 or MPLAB REAL ICE™ In-Circuit
Emulator.
For more information on MPLAB ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available from the Microchip web site.
“Using MPLAB
®
ICD 3 In-Circuit Debugger”
(poster) (DS51765)
“Development Tools Design Advisory” (DS51764)
“MPLAB
®
REAL ICE™ In-Circuit Emulator User’s
Guide” (DS51616)
“Using MPLAB
®
REAL ICE™ In-Circuit Emulator”
(poster) (DS51749)
2.7 JTAG
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action Group
(JTAG) standard. It is recommended to keep the trace
length between the JTAG connector, and the JTAG pins
on the device, as short as possible. If the JTAG connector
is expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few tens
of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended as
they will interfere with the programmer/debugger com-
munications to the device. If such discrete components
are an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin Input Voltage High (V
IH
)
and Input Voltage Low (V
IL
) requirements.
2.8 External Oscillator Pins
The PIC32MM0064GPL036 family has options for two
external oscillators: a high-frequency primary oscillator
and a low-frequency secondary oscillator (refer to
Section 8.0 “Oscillator Configuration” for details).
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator
circuit close to the respective oscillator pins, not
exceeding one-half inch (12 mm) distance between
them. The load capacitors should be placed next to the
oscillator itself, on the same side of the board. Use a
grounded copper pour around the oscillator circuit to
isolate them from surrounding circuits. The grounded
copper pour should be routed directly to the MCU
ground. Do not run any signal traces or power traces
inside the ground pour. Also, if using a two-sided board,
avoid any traces on the other side of the board where
the crystal is placed. A suggested layout is illustrated in
Figure 2-4.
FIGURE 2-4: SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
2.9 Unused I/Os
To minimize power consumption, unused I/O pins
should not be allowed to float as inputs. They can be
configured as outputs and driven to a logic low or logic
high state.
Alternatively, inputs can be reserved by ensuring the pin
is always configured as an input and externally connect-
ing the pin to V
SS
or V
DD
. A current-limiting resistor may
be used to create this connection if there is any risk of
inadvertently configuring the pin as an output with the
logic output state opposite of the chosen power rail.
Main Oscillator
Guard Ring
Guard Trace
Secondary
Oscillator
2015-2018 Microchip Technology Inc. DS60001324C-page 23
PIC32MM0064GPL036 FAMILY
3.0 CPU
The MIPS32
®
microAptiv™ UC microprocessor core is
the heart of the PIC32MM0064GPL036 family devices.
The CPU fetches instructions, decodes each
instruction, fetches source operands, executes each
instruction and writes the results of the instruction
execution to the proper destinations.
3.1 Features
The PIC32MM0064GPL036 family processor core key
features include:
5-Stage Pipeline
32-Bit Address and Data Paths
MIPS32 Enhanced Architecture:
- Multiply-add and multiply-subtract instructions
- Targeted multiply instruction
- Zero and one detect instructions
-WAIT instruction
- Conditional move instructions
- Vectored interrupts
- Atomic interrupt enable/disable
- One GPR shadow set to minimize latency of
interrupts
- Bit field manipulation instructions
microMIPS™ Instruction Set:
- microMIPS allows improving the code size
density over MIPS32, while maintaining
MIPS32 performance.
- microMIPS supports all MIPS32 instructions
(except for branch-likely instructions) with
new optimized 32-bit encoding. Frequent
MIPS32 instructions are available as 16-bit
instructions.
- Added seventeen new and thirty-five
MIPS32
®
corresponding commonly used
instructions in 16-bit opcode format.
- Stack Pointer implicit in instruction.
- MIPS32 assembly and ABI compatible.
Memory Management Unit with Simple Fixed
Mapping Translation (FMT) Mechanism
Multiply/Divide Unit (MDU):
- Configurable using high-performance
multiplier array.
- Maximum issue rate of one 32x16 multiply
per clock.
- Maximum issue rate of one 32x32 multiply
every other clock.
- Early-in iterative divide. Minimum 11 and
maximum 33 clock latency (dividend (rs) sign
extension dependent).
Power Control:
- No minimum frequency: 0 MHz.
- Power-Down mode (triggered by WAIT
instruction).
EJTAG Debug/Profiling:
- CPU control with start, stop and single
stepping.
- Software breakpoints via the SDBBP
instruction.
- Optional simple hardware breakpoints on
virtual addresses, 4 instruction and 2 data
breakpoints.
- PC and/or load/store address sampling for
profiling.
- Performance counters.
- Supports Fast Debug Channel (FDC).
A block diagram of the PIC32MM0064GPL036 family
processor core is shown in Figure 3-1.
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 50. “CPU for
Devices with MIPS32
®
microAptiv™
and M-Class Cores” (DS60001192) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
MIPS32
®
microAptiv™ UC microproces-
sor core resources are available at:
www.imgtec.com. The information in this
data sheet supersedes the information in
the FRM.
PIC32MM0064GPL036 FAMILY
DS60001324C-page 24 2015-2018 Microchip Technology Inc.
FIGURE 3-1: PIC32MM0064GPL036 FAMILY MICROPROCESSOR CORE
BLOCK DIAGRAM
System Bus
Execution Unit
ALU/Shift
Atomic/LdSt
MCU ASE
System
Coprocessor
Enhanced MDU
GPR
(2 sets)
Debug/Profiling
Breakpoints
Fast Debug Channel
Performance Counters
Power
System
Interface
Interrupt
Interface
MMU
Decode
(microMIPS™)
EJTAG
2-Wire Debug
Management
SYSCLK
MIPS32® microAptiv™ UC Microprocessor Core
2015-2018 Microchip Technology Inc. DS60001324C-page 25
PIC32MM0064GPL036 FAMILY
3.2 Architecture Overview
The MIPS32
®
microAptiv™ UC microprocessor core in
the PIC32MM0064GPL036 family devices contains
several logic blocks, working together in parallel, pro-
viding an efficient high-performance computing engine.
The following blocks are included with the core:
Execution Unit
General Purpose Register (GPR)
Multiply/Divide Unit (MDU)
System Control Coprocessor (CP0)
Memory Management Unit (MMU)
Power Management
microMIPS Instructions Decoder
Enhanced JTAG (EJTAG) Controller
3.2.1 EXECUTION UNIT
The processor core execution unit implements a load/
store architecture with single-cycle ALU operations
(logical, shift, add, subtract) and an autonomous Multiply/
Divide Unit (MDU). The core contains thirty-two 32-bit
General Purpose Registers (GPRs) used for integer
operations and address calculation. One additional
register file shadow set (containing thirty-two registers) is
added to minimize context switching overhead during
interrupt/exception processing. The register file consists
of two read ports and one write port, and is fully bypassed
to minimize operation latency in the pipeline.
The execution unit includes:
32-bit adder used for calculating the data address
Address unit for calculating the next instruction address
Logic for branch determination and branch target
address calculation
Load aligner
Bypass multiplexers used to avoid Stalls when
executing instruction streams where data produc-
ing instructions are followed closely by consumers
for their results
Leading zero/one detect unit for implementing the
CLZ and CLO instructions
Arithmetic Logic Unit (ALU) for performing
arithmetic and bitwise logical operations
Shifter and store aligner
3.2.2 MULTIPLY/DIVIDE UNIT (MDU)
The microAptiv UC core includes a Multiply/Divide Unit
(MDU) that contains a separate pipeline for multiply
and divide operations. This pipeline operates in parallel
with the Integer Unit (IU) pipeline and does not stall
when the IU pipeline stalls. This allows the long-
running MDU operations to be partially masked by
system Stalls and/or other Integer Unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, Result/Accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
microAptiv UC core only checks the value of the rt
operand to determine how many times the operation
must pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle. Appro-
priate interlocks are implemented to stall the issuance of
back-to-back, 32x32 multiply operations. The multiply
operand size is automatically determined by logic built
into the MDU. Divide operations are implemented with a
simple 1-bit-per-clock iterative algorithm. An early-in
detection checks the sign extension of the dividend (rs)
operand. If rs is 8 bits wide, 23 iterations are skipped.
For a 16-bit wide rs, 15 iterations are skipped, and for a
24-bit wide rs, 7 iterations are skipped. Any attempt to
issue a subsequent MDU instruction while a divide is still
active causes an IU pipeline Stall until the divide
operation has completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be re-issued), and latency
(number of cycles until a result is available) for the
microAptiv UC core multiply and divide instructions.
The approximate latency and repeat rates are listed in
terms of pipeline clocks.
TABLE 3-1: MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode Operand Size (mul rt) (div rs)Latency Repeat Rate
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU
16 bits 1 1
32 bits 2 2
MUL (GPR destination) 16 bits 2 1
32 bits 3 2
DIV/DIVU 8 bits 12 11
16 bits 19 18
24 bits 26 25
32 bits 33 32
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DS60001324C-page 26 2015-2018 Microchip Technology Inc.
The MIPS
®
architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, the MIPS
architecture also defines a Multiply instruction, MUL,
which places the least significant results in the primary
register file instead of the HI/LO register pair. By avoid-
ing the explicit MFLO instruction, required when using the
LO register, and by supporting multiple destination
registers, the throughput of multiply-intensive operations
is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
3.2.3 SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. These
configuration options and other system information is
available by accessing the CP0 registers listed in
Table 3-2.
2015-2018 Microchip Technology Inc. DS60001324C-page 27
PIC32MM0064GPL036 FAMILY
TABLE 3-2: COPROCESSOR 0 REGISTERS
Register
Number Register
Name Function
0-3 Reserved Reserved in the microAptiv™ UC.
4 UserLocal User information that can be written by privileged software and read via
RDHWR, Register 29.
5-6 Reserved Reserved in the microAptiv UC.
7 HWREna Enables access via the RDHWR instruction to selected hardware registers in
Non-Privileged mode.
8BadVAddr
(1)
Reports the address for the most recent address related exception.
9 Count
(1)
Processor cycle count.
10 Reserved Reserved in the microAptiv UC.
11 Compare
(1)
Timer interrupt control.
12 Status/
IntCtl/
SRSCtl/
SRSMap1/
View_IPL/
SRSMAP2
Processor status and control; interrupt control and shadow set control.
13 Cause
(1)
/
View_RIPL
Cause of last exception.
14 EPC
(1)
Program Counter at last exception.
15 PRId/
EBase/
CDMMBase
Processor identification and revision; exception base address; Common Device
Memory Map Base register.
16 CONFIG/
CONFIG1/
CONFIG2/
CONFIG3/
CONFIG7
Configuration registers.
7-22 Reserved Reserved in the microAptiv UC.
23 Debug/
Debug2/
TraceControl/
TraceControl2/
UserTraceData1/
TraceBPC
(2)
EJTAG Debug register.
EJTAG Debug Register 2.
EJTAG Trace Control register.
EJTAG Trace Control Register 2.
EJTAG User Trace Data 1 register.
EJTAG Trace Breakpoint register.
24 DEPC
(2)
/
UserTraceData2
Program Counter at last debug exception.
EJTAG User Trace Data 2 register.
25 PerfCtl0/
PerfCnt0/
PerfCtl1/
PerfCnt1
Performance Counter 0 control.
Performance Counter 0.
Performance Counter 1 control.
Performance Counter 1.
26 ErrCtl Software parity check enable.
27 CacheErr Records information about SRAM parity errors.
28-29 Reserved Reserved in the PIC32 core.
30 ErrorEPC
(1)
Program Counter at last error.
31 DeSAVE
(2)
Debug Handler Scratchpad register.
Note 1: Registers used in exception processing.
2: Registers used in debug.
PIC32MM0064GPL036 FAMILY
DS60001324C-page 28 2015-2018 Microchip Technology Inc.
3.3 Power Management
The processor core offers a number of power
management features, including low-power design,
active power management and Power-Down modes
of operation. The core is a static design that
supports slowing or halting the clocks, which reduces
system power consumption during Idle periods.
The mechanism for invoking Power-Down mode is
implemented through execution of the WAIT
instruction. The majority of the power consumed by
the processor core is in the clock tree and clocking
registers. The PIC32MM family makes extensive use
of local gated clocks to reduce this dynamic power
consumption.
3.4 EJTAG Debug Support
The microAptiv UC core has an Enhanced JTAG
(EJTAG) interface for use in the software debug. In
addition to the standard mode of operation, the
microAptiv UC core provides a Debug mode that is
entered after a debug exception (derived from a hard-
ware breakpoint, single-step exception, etc.) is taken
and continues until a Debug Exception Return (DERET)
instruction is executed. During this time, the processor
executes the debug exception handler routine.
The EJTAG interface operates through the Test
Access Port (TAP), a serial communication port used
for transferring test data in and out of the microAptiv
UC core. In addition to the standard JTAG instructions,
special instructions defined in the EJTAG specification
specify which registers are selected and how they are
used.
3.5 MIPS32® microAptiv™ UC Core
Configuration
Register 3-1 through Register 3-4 show the default
configuration of the microAptiv UC core, which is
included on PIC32MM0064GPL036 family devices.
2015-2018 Microchip Technology Inc. DS60001324C-page 29
PIC32MM0064GPL036 FAMILY
REGISTER 3-1: CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 r-0
K23<2:0> KU<2:0>
23:16
r-0 R-0 R-1 R-0 r-0 r-0 r-0 R-1
UDI SB MDU — — —DS
15:8
R-0 R-0 R-0 R-0 R-0 R-1 R-0 R-1
BE AT<1:0> AR<2:0> MT<2:1>
7:0
R-1 r-0 r-0 r-0 r-0 R/W-0 R/W-1 R/W-0
MT<0> — K0<2:0>
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: This bit is hardwired to1’ to indicate the presence of the CONFIG1 register
bit 30-28 K23<2:0>: Cacheability of the kseg2 and kseg3 Segments bits
010 = Cache is not implemented
bit 27-25 KU<2:0>: Cacheability of the kuseg and useg Segments bits
010 = Cache is not implemented
bit 24-23 Reserved: Must be written as zeros; returns zeros on reads
bit 22 UDI: User-Defined bit
0 = CorExtend user-defined instructions are not implemented
bit 21 SB: SimpleBE bit
1 = Only simple byte enables are allowed on the internal bus interface
bit 20 MDU: Multiply/Divide Unit bit
0 = Fast, high-performance MDU
bit 19-17 Reserved: Must be written as zeros; returns zeros on reads
bit 16 DS: Dual SRAM Interface bit
1 = Dual instruction/data SRAM interface
bit 15 BE: Endian Mode bit
0 = Little-endian
bit 14-13 AT<1:0>: Architecture Type bits
00 = MIPS32
®
bit 12-10 AR<2:0>: Architecture Revision Level bits
001 = MIPS32
Release 2
bit 9-7 MT<2:0>: MMU Type bits
011 = Fixed mapping
bit 6-3 Reserved: Must be written as zeros; returns zeros on reads
bit 2-0 K0<2:0>: kseg0 Coherency Algorithm bits
010 = Cache is not implemented
PIC32MM0064GPL036 FAMILY
DS60001324C-page 30 2015-2018 Microchip Technology Inc.
REGISTER 3-2: CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — —
7:0
U-0 U-0 U-0 R-1 R-0 R-0 R-1 R-0
—PCWRCAEPFP
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the CONFIG2 register
bit 30-5 Unimplemented: Read as0
bit 4 PC: Performance Counter bit
1 = The processor core contains performance counters
bit 3 WR: Watch Register Presence bit
0 = No Watch registers are present
bit 2 CA: Code Compression Implemented bit
0 = No MIPS16e
®
are present
bit 1 EP: EJTAG Present bit
1 = Core implements EJTAG
bit 0 FP: Floating-Point Unit bit
0 = Floating-Point Unit is not implemented
2015-2018 Microchip Technology Inc. DS60001324C-page 31
PIC32MM0064GPL036 FAMILY
REGISTER 3-3: CONFIG3: CONFIGURATION REGISTER 3; CP0 REGISTER 16, SELECT 3
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — —
23:16
U-0 R-0 R-1 R-0 R-0 R-0 R-1 R-1
IPLW<1:0> MMAR<2:0> MCU ISAONEXC
15:8
R-0 R-1 R-1 R-1 U-0 U-0 U-0 R-0
ISA<1:0> ULRI RXI — — —ITL
7:0
U-0 R-1 R-1 R-0 R-1 U-0 U-0 R-0
VEIC VINT SP CDMM —TL
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: This bit is hardwired as ‘0
bit 30-23 Unimplemented: Read as ‘0
bit 22-21 IPLW<1:0>: Width of the Status IPL and Cause RIPL bits
01 = IPL and RIPL bits are 8 bits in width
bit 20-18 MMAR<2:0>: microMIPS™ Architecture Revision Level bits
000 = Release 1
bit 17 MCU: MIPS
®
MCU ASE Implemented bit
1 = MCU ASE is implemented
bit 16 ISAONEXC: ISA on Exception bit
1 = microMIPS is used on entrance to an exception vector
bit 15-14 ISA<1:0>: Instruction Set Availability bits
01 = Only microMIPS is implemented
bit 13 ULRI: UserLocal Register Implemented bit
1 = UserLocal Coprocessor 0 register is implemented
bit 12 RXI: RIE and XIE Implemented in PageGrain bit
1 = RIE and XIE bits are implemented
bit 11-9 Unimplemented: Read as ‘0
bit 8 ITL: Indicates that iFlowtrace™ Hardware is Present bit
0 = The iFlowtrace hardware is not implemented in the core
bit 7 Unimplemented: Read as ‘0
bit 6 VEIC: External Vector Interrupt Controller bit
1 = Support for an external interrupt controller is implemented.
bit 5 VINT: Vector Interrupt bit
1 = Vector interrupts are implemented
bit 4 SP: Small Page bit
0 = 4-Kbyte page size
bit 3 CDMM: Common Device Memory Map bit
1 = CDMM is implemented
bit 2-1 Unimplemented: Read as ‘0
bit 0 TL: Trace Logic bit
0 = Trace logic is not implemented
PIC32MM0064GPL036 FAMILY
DS60001324C-page 32 2015-2018 Microchip Technology Inc.
REGISTER 3-4: CONFIG5: CONFIGURATION REGISTER 5; CP0 REGISTER 16, SELECT 5
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-1
— — —NF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-1 Unimplemented: Read as0
bit 0 NF: Nested Fault bit
1 = Nested Fault feature is implemented
2015-2018 Microchip Technology Inc. DS60001324C-page 33
PIC32MM0064GPL036 FAMILY
4.0 MEMORY ORGANIZATION
PIC32MM microcontrollers provide 4 Gbytes of unified
virtual memory address space. All memory regions,
including program, data memory, SFRs and Configura-
tion registers, reside in this address space at their
respective unique addresses. The data memory can be
made executable, allowing the CPU to execute code
from data memory.
Key features include:
32-Bit Native Data Width
Separate Boot Flash Memory (BFM) for
Protected Code
Robust Bus Exception Handling to Intercept
Runaway Code
Simple Memory Mapping with Fixed Mapping
Translation (FMT) Unit
The PIC32MM0064GPL036 family devices implement
two address spaces: virtual and physical. All hardware
resources, such as program memory, data memory and
peripherals, are located at their respective physical
addresses. Virtual addresses are exclusively used by the
CPU to fetch and execute instructions. Physical
addresses are used by peripherals, such as Flash
controllers, that access memory independently of the
CPU.
The virtual address space is divided into two segments
of 512 Mbytes each, labeled kseg0 and kseg1. The
Program Flash Memory (PFM) and Data RAM Memory
(DRM) are accessible from either kseg0 or kseg1, while
the Boot Flash Memory (BFM) and peripheral SFRs are
accessible only from kseg1.
The Fixed Mapping Translation (FMT) unit translates
the memory segments into corresponding physical
address regions. Figure 4-1 through Figure 4-3 illus-
trate the fixed mapping scheme, implemented by the
PIC32MM0064GPL036 family core, between the virtual
and physical address space.
The mapping of the memory segments depends on the
CPU error level, set by the ERL bit in the CPU STATUS
Register (SR). Error level is set (ERL = 1) by the CPU
on a Reset, Soft Reset or NMI. In this mode, the CPU
can access memory by the physical address. This
mode is provided for compatibility with other MIPS
®
processor cores that use a TLB-based MMU. The C
start-up code clears the ERL bit to zero, so that when
application software starts up, it sees the proper virtual
to physical memory mapping.
4.1 Alternate Configuration Bits
Space
Every Configuration Word has an associated Alternate
Word (designated by the letter A as the first letter in the
name of the word). During device start-up, Primary
Words are read, and if uncorrectable ECC errors are
found, the BCFGERR (RCON<27>) flag is set and
Alternate Words are used. If uncorrectable ECC errors
are found in Primary and Alternate Words, the
BCFGFAIL (RCON<26>) flag is set, and the default
configuration is used. The Primary Configuration bits
area is located at the address range, from 0x1FC01780
to 0x1FC017E8. The Alternate Configuration bits area
is located at the address range, from 0x1FC01700 to
0x1FC01768.
\ Y )\ V / \/
PIC32MM0064GPL036 FAMILY
DS60001324C-page 34 2015-2018 Microchip Technology Inc.
FIGURE 4-1: MEMORY MAP FOR DEVICES WITH 16 Kbytes OF PROGRAM MEMORY
(1)
Virtual
Memory Map
0x00000000 Reserved
0x7FFFFFFF
0x80000000 4 Kbytes RAM
0x80000FFF
0x80001000 Reserved
0x9CFFFFFF
0x9D000000 16 Kbytes Flash
0x9D003FFF
0x9D004000 Reserved Physical
Memory Map
0x9F7FFFFF
0x9F800000 SFRs(2)4 Kbytes RAM 0x00000000
0x9F80FFFF 0x00000FFF
0x9F810000 Reserved Reserved 0x00001000
0x9FBFFFFF 0x1CFFFFFF
0x9FC00000 Boot Flash(2)16 Kbytes Flash 0x1D000000
0x9FC016FF 0x1D003FFF
0x9FC01700 Configuration Bits(2,3)Reserved 0x1D004000
0x9FC017FF 0x1F7FFFFF
0x9FC01800 Reserved SFRs 0x1F800000
0x9FFFFFFF 0x1F80FFFF
0xA0000000 4 Kbytes RAM Reserved 0x1F810000
0xA0000FFF 0x1FBFFFFF
0xA0001000 Reserved Boot Flash 0x1FC00000
0xBCFFFFFF 0x1FC016FF
0xBD000000 16 Kbytes Flash Configuration Bits(3)0x1FC01700
0xBD003FFF 0x1FC017FF
0xBD004000 Reserved Reserved 0x1FC01800
0xBF7FFFFF 0xFFFFFFFF
0xBF800000 SFRs
0xBF80FFFF
0xBF810000 Reserved
0xBFBFFFFF
0xBFC00000 Boot Flash
0xBFC016FF
0xBFC01700 Configuration Bits(3)
0xBFC017FF
0xBFC01800 Reserved
0xFFFFFFFF
Note 1: Memory areas are not shown to scale.
2: This region should be accessed from kseg1 space only.
3: Primary Configuration bits area is located at the address range, from 0x1FC01780 to 0x1FC017E8.
Alternate Configuration bits area is located at the address range, from 0x1FC01700 to 0x1FC01768.
Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.
kseg1 kseg0
V\// /
2015-2018 Microchip Technology Inc. DS60001324C-page 35
PIC32MM0064GPL036 FAMILY
FIGURE 4-2: MEMORY MAP FOR DEVICES WITH 32 Kbytes OF PROGRAM MEMORY
(1)
Virtual
Memory Map
0x00000000 Reserved
0x7FFFFFFF
0x80000000 8 Kbytes RAM
0x80001FFF
0x80002000 Reserved
0x9CFFFFFF
0x9D000000 32 Kbytes Flash
0x9D007FFF
0x9D008000 Reserved Physical
Memory Map
0x9F7FFFFF
0x9F800000 SFRs(2)8 Kbytes RAM 0x00000000
0x9F80FFFF 0x00001FFF
0x9F810000 Reserved Reserved 0x00002000
0x9FBFFFFF 0x1CFFFFFF
0x9FC00000 Boot Flash(2)32 Kbytes Flash 0x1D000000
0x9FC016FF 0x1D007FFF
0x9FC01700 Configuration Bits(2,3)Reserved 0x1D008000
0x9FC017FF 0x1F7FFFFF
0x9FC01800 Reserved SFRs 0x1F800000
0x9FFFFFFF 0x1F80FFFF
0xA0000000 8 Kbytes RAM Reserved 0x1F810000
0xA0001FFF 0x1FBFFFFF
0xA0002000 Reserved Boot Flash 0x1FC00000
0xBCFFFFFF 0x1FC016FF
0xBD000000 32 Kbytes Flash Configuration Bits(3)0x1FC01700
0xBD007FFF 0x1FC017FF
0xBD008000 Reserved Reserved 0x1FC01800
0xBF7FFFFF 0xFFFFFFFF
0xBF800000 SFRs
0xBF80FFFF
0xBF810000 Reserved
0xBFBFFFFF
0xBFC00000 Boot Flash
0xBFC016FF
0xBFC01700 Configuration Bits(3)
0xBFC017FF
0xBFC01800 Reserved
0xFFFFFFFF
Note 1: Memory areas are not shown to scale.
2: This region should be accessed from kseg1 space only.
3: Primary Configuration bits area is located at the address range, from 0x1FC01780 to 0x1FC017E8.
Alternate Configuration bits area is located at the address range, from 0x1FC01700 to 0x1FC01768.
Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.
kseg1 kseg0
\ /,\ /
PIC32MM0064GPL036 FAMILY
DS60001324C-page 36 2015-2018 Microchip Technology Inc.
FIGURE 4-3: MEMORY MAP FOR DEVICES WITH 64 Kbytes OF PROGRAM MEMORY
(1)
Virtual
Memory Map
0x00000000 Reserved
0x7FFFFFFF
0x80000000 8 Kbytes RAM
0x80001FFF
0x80002000 Reserved
0x9CFFFFFF
0x9D000000 64 Kbytes Flash
0x9D00FFFF
0x9D010000 Reserved Physical
Memory Map
0x9F7FFFFF
0x9F800000 SFRs(2)8 Kbytes RAM 0x00000000
0x9F80FFFF 0x00001FFF
0x9F810000 Reserved Reserved 0x00002000
0x9FBFFFFF 0x1CFFFFFF
0x9FC00000 Boot Flash(2)64 Kbytes Flash 0x1D000000
0x9FC016FF 0x1D00FFFF
0x9FC01700 Configuration Bits(2,3)Reserved 0x1D010000
0x9FC017FF 0x1F7FFFFF
0x9FC01800 Reserved SFRs 0x1F800000
0x9FFFFFFF 0x1F80FFFF
0xA0000000 8 Kbytes RAM Reserved 0x1F810000
0xA0001FFF 0x1FBFFFFF
0xA0002000 Reserved Boot Flash 0x1FC00000
0xBCFFFFFF 0x1FC016FF
0xBD000000 64 Kbytes Flash Configuration Bits(3)0x1FC01700
0xBD00FFFF 0x1FC017FF
0xBD010000 Reserved Reserved 0x1FC01800
0xBF7FFFFF 0xFFFFFFFF
0xBF800000 SFRs
0xBF80FFFF
0xBF810000 Reserved
0xBFBFFFFF
0xBFC00000 Boot Flash
0xBFC016FF
0xBFC01700 Configuration Bits(3)
0xBFC017FF
0xBFC01800 Reserved
0xFFFFFFFF
Note 1: Memory areas are not shown to scale.
2: This region should be accessed from kseg1 space only.
3: Primary Configuration bits area is located at the address range, from 0x1FC01780 to 0x1FC017E8.
Alternate Configuration bits area is located at the address range, from 0x1FC01700 to 0x1FC01768.
Refer to Section 4.1 “Alternate Configuration Bits Space” for more information.
kseg1 kseg0
2015-2018 Microchip Technology Inc. DS60001324C-page 37
PIC32MM0064GPL036 FAMILY
5.0 FLASH PROGRAM MEMORY
PIC32MM0064GPL036 family devices contain an
internal Flash program memory for executing user
code. The Program and Boot Flash Memory can be
write-protected. The erase page size is 512 32-bit
words. The program row size is 64 32-bit words. The
memory can be programmed by rows or by two 32-bit
words.
The devices implement an Error Correcting Code
(ECC). The memory control block contains a logic to
write and read ECC bits to and from the Flash memory.
The Flash is programmed at the same time as the cor-
responding ECC bits. The ECC provides improved
resistance to Flash errors. The ECC single-bit error will
be transparently corrected. The ECC double-bit error
results in a bus error exception.
There are three methods by which the user can
program this memory:
Run-Time Self-Programming (RTSP)
EJTAG Programming
In-Circuit Serial Programming™ (ICSP™)
RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP tech-
niques is described in Section 5. “Flash Program-
ming” in the “PIC32 Family Reference Manual”.
EJTAG programming is performed using the JTAG port
of the device. ICSP programming requires fewer con-
nections than for EJTAG programming. The EJTAG
and ICSP methods are described in the “PIC32 Flash
Programming Specification” (DS60001145), which is
available for download from the Microchip web site.
5.1 Flash Controller Registers Write
Protection
The NVMPWP and NVMBWP registers, and the WR bit
in the NVMCON register are protected (locked) from an
accidental write. A special unlock sequence is required
to modify the content of these registers or bits.
To unlock, the following steps should be done:
1. Disable interrupts prior to the unlock sequence.
2. Execute the system unlock sequence by writ-
ing the key values of 0xAA996655 and
0x556699AA to the NVMKEY register in two
back-to-back Assembly or ‘C’ instructions.
3. Write the new value to the required bits.
4. Re-enable interrupts.
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 5. “Flash Programming
(DS60001121) in the PIC32 Family Refer-
ence Manual”, which is available from the
Microchip web site (www.microchip.com/
PIC32). The information in this data sheet
supersedes the information in the FRM.
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DS60001324C-page 38 2015-2018 Microchip Technology Inc.
5.2 Flash Control Registers
TABLE 5-1: FLASH CONTROLLER REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2380 NVMCON(1)31:16 — — — — — — 0000
15:0 WR WREN WRERR LVDERR — — — — NVMOP<3:0> 0000
2390 NVMKEY 31:16 NVMKEY<31:0> 0000
15:0 0000
23A0 NVMADDR(1)31:16 NVMADDR<31:0> 0000
15:0 0000
23B0 NVMDATA0 31:16 NVMDATA0<31:0> 0000
15:0 0000
23C0 NVMDATA1 31:16 NVMDATA1<31:0> 0000
15:0 0000
23D0 NVMSRCADDR 31:16 NVMSRCADDR<31:0> 0000
15:0 0000
23E0 NVMPWP(1)31:16 PWPULOCK — — — — — PWP<23:16> 8000
15:0 PWP<15:0> 0000
23F0 NVMBWP(1)31:16 — — — 0000
15:0 BWPULOCK — — BWP<2:0> — — — — — 8700
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These registers have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively.
2015-2018 Microchip Technology Inc. DS60001324C-page 39
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REGISTER 5-1: NVMCON: NVM PROGRAMMING CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
15:8 R/W-0, HC R/W-0 R-0, HS, HC R-0, HS, HC r-0 U-0 U-0 U-0
WR
(1,4)
WREN
(1)
WRERR
(1,2)
LVDERR
(1,2)
— —
7:0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —NVMOP<3:0>
(3)
Legend: HS = Hardware Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared r = Reserved bit
bit 31-16 Unimplemented: Read as ‘0
bit 15 WR: Write Control bit
(1,4)
This bit cannot be cleared and can be set only when WREN = 1, and the unlock sequence has been performed.
1 = Initiates a Flash operation
0 = Flash operation is complete or inactive
bit 14 WREN: Write Enable bit
(1)
1 = Enables writes to the WR bit and disables writes to the NVMOP<3:0> bits
0 = Disables writes to the WR bit and enables writes to the NVMOP<3:0> bits
bit 13 WRERR: Write Error bit
(1,2)
This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12 LVDERR: Low-Voltage Detect Error bit
(1,2)
This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.
1 = Low voltage is detected (possible data corruption if WRERR is set)
0 = Voltage level is acceptable for programming
bit 11 Reserved: Maintain as0
bit 10-4 Unimplemented: Read as ‘0
Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other Reset sources.
2: These bits are cleared by setting NVMOP<3:0> = 0000 and initiating a Flash operation (i.e., WR).
3: NVMOP<3:0> bits are write-protected if the WREN bit is set.
4: Writes to the WR bit require an unlock sequence. Refer to Section 5.1 “Flash Controller Registers Write
Protection” for details.
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DS60001324C-page 40 2015-2018 Microchip Technology Inc.
bit 3-0 NVMOP<3:0>: NVM Operation bits
(3)
These bits are only writable when WREN = 0.
1111 = Reserved
1000 = Reserved
0111 = Program Erase Operation: Erases all of Program Flash Memory (all pages must be unprotected in
the NVMPWP register, Boot Flash Memory is not erased)
0110 = Reserved
0101 = Reserved
0100 = Page Erase Operation: Erases page selected by NVMADDR (erases Boot or Program Flash
Memory, page must be unprotected in the NVMBWP or NVMPWP register)
0011 = Row Program Operation: Programs row selected by NVMADDR (programs Boot or Program Flash
Memory, page must be unprotected in the NVMBWP or NVMPWP register)
0010 = Double-Word Program Operation: Programs two words to the address selected by NVMADDR
(programs Boot or Program Flash Memory, page must be unprotected in the NVMBWP or
NVMPWP register)
0001 = Reserved
0000 = No operation, clears WRERR and LVDERR bits
REGISTER 5-1: NVMCON: NVM PROGRAMMING CONTROL REGISTER (CONTINUED)
Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other Reset sources.
2: These bits are cleared by setting NVMOP<3:0> = 0000 and initiating a Flash operation (i.e., WR).
3: NVMOP<3:0> bits are write-protected if the WREN bit is set.
4: Writes to the WR bit require an unlock sequence. Refer to Section 5.1 “Flash Controller Registers Write
Protection” for details.
2015-2018 Microchip Technology Inc. DS60001324C-page 41
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REGISTER 5-2: NVMKEY: NVM PROGRAMMING UNLOCK REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<31:24>
23:16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<23:16>
15:8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<15:8>
7:0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMKEY<31:0>: NVM Unlock Register bits
These bits are write-only and read as 0’ on any read.
REGISTER 5-3: NVMADDR: NVM FLASH ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMADDR<31:0>: NVM Flash Address bits
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DS60001324C-page 42 2015-2018 Microchip Technology Inc.
REGISTER 5-4: NVMDATAx: NVM FLASH DATA x REGISTER (x = 0-1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATAx<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATAx<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATAx<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATAx<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMDATAx<31:0>: NVM Flash Data x bits
Double-Word Program: Writes NVMDATA1:NVMDATA0 to the target Flash address defined in NVMADDR.
NVMDATA0 contains the least significant instruction word.
REGISTER 5-5: NVMSRCADDR: NVM SOURCE DATA ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMSRCADDR<31:0>: NVM Source Data Address bits
The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits
(NVMCON<3:0>) are set to perform row programming.
2015-2018 Microchip Technology Inc. DS60001324C-page 43
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REGISTER 5-6: NVMPWP: NVM PROGRAM FLASH WRITE-PROTECT REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0
PWPULOCK — —
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWP<23:16>
(2)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWP<15:8>
(2)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWP<7:0>
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 PWPULOCK: Program Flash Memory Page Write-Protect Unlock bit
1 = Register is not locked and can be modified
0 = Register is locked and cannot be modified
This bit is only clearable and cannot be set except by any Reset.
bit 30-24 Unimplemented: Read as ‘0
bit 23-0 PWP<23:0>: Flash Program Write-Protect (Page) Address bits
(2)
Physical memory below address, 0x1DXXXXXX, is write-protected, where ‘XXXXXX’ is specified by
PWP<23:0>. When the PWP<23:0> bits have a value of ‘0’, write protection is disabled for the entire
Program Flash Memory. If the specified address falls within the page, the entire page and all pages below
the current page will be protected.
Note 1: Writes to this register require an NVMKEY unlock sequence. Refer to Section 5.1 “Flash Controller
Registers Write Protection” for details.
2: These bits can be modified only when the unlock bit (PWPULOCK) is set.
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DS60001324C-page 44 2015-2018 Microchip Technology Inc.
REGISTER 5-7: NVMBWP: NVM BOOT FLASH (PAGE) WRITE-PROTECT REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
15:8
R/W-1 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1
BWPULOCK —BWP2
(2)
BWP1
(2)
BWP0
(2)
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as0
bit 15 BWPULOCK: Boot Alias Write-Protect Unlock bit
1 = BWPx bits are not locked and can be modified
0 = BWPx bits are locked and cannot be modified
This bit is only clearable and cannot be set except by any Reset.
bit 14-11 Unimplemented: Read as0
bit 10 BWP2: Boot Alias Page 2 Write-Protect bit
(2)
1 = Write protection for physical address, 0x1FC01000 through 0x1FC017FF, is enabled
0 = Write protection for physical address, 0x1FC01000 through 0x1FC017FF, is disabled
bit 9 BWP1: Boot Alias Page 1 Write-Protect bit
(2)
1 = Write protection for physical address, 0x1FC00800 through 0x1FC00FFF, is enabled
0 = Write protection for physical address, 0x1FC00800 through 0x1FC00FFF, is disabled
bit 8 BWP0: Boot Alias Page 0 Write-Protect bit
(2)
1 = Write protection for physical address, 0x1FC00000 through 0x1FC007FF, is enabled
0 = Write protection for physical address, 0x1FC00000 through 0x1FC007FF, is disabled
bit 7-0 Unimplemented: Read as0
Note 1: Writes to this register require an NVMKEY unlock sequence. Refer to Section 5.1 “Flash Controller
Registers Write Protection” for details.
2: These bits can be modified only when the associated unlock bit (BWPULOCK) is set.
2015-2018 Microchip Technology Inc. DS60001324C-page 45
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6.0 RESETS
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
device Reset sources are as follows:
Power-on Reset (POR)
Master Clear Reset Pin (MCLR)
Software Reset (SWR)
Watchdog Timer Reset (WDTR)
Brown-out Reset (BOR)
Configuration Mismatch Reset (CMR)
A simplified block diagram of the Reset module is
illustrated in Figure 6-1.
FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM
Note: This data sheet summarizes the features of
the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 7. “Resets” (DS60001118)
in the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
The information in this data sheet
supersedes the information in the FRM.
MCLR
V
DD
V
DD
Rise
Detect
POR
Sleep or Idle
Glitch Filter
BOR
Configuration
SYSRST
Software Reset
Power-up
Timer
Voltage Regulator
Reset
WDTR
SWR
CMR
MCLR
Mismatch
NMI
Time-out
WDT
Time-out
Brown-out
Reset
Enabled
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DS60001324C-page 46 2015-2018 Microchip Technology Inc.
6.1 Reset Control Registers
TABLE 6-1: RESETS REGISTER MAP
Virtual Address
(BF80_#)
Register
Name(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
1240 RCON 31:16 PORIO PORCORE BCFGERR BCFGFAIL C000
15:0 CMR EXTR SWR WDTO SLEEP IDLE BOR POR 0003
1250 RSWRST 31:16 0000
15:0 SWRST 0000
1260 RNMICON 31:16 WDTR SWNMI GNMI CF WDTS 0000
15:0 NMICNT<15:0> 0000
1270 PWRCON 31:16 0000
15:0 SBOREN RETEN VREGS 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively.
MCLR
2015-2018 Microchip Technology Inc. DS60001324C-page 47
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REGISTER 6-1: RCON: RESET CONTROL REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-1, HS R/W-1, HS U-0 U-0 R/W-0, HS R/W-0, HS U-0 U-0
PORIO PORCORE BCFGERR BCFGFAIL — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS U-0
— — —CMR
7:0
R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS
EXTR SWR WDTO SLEEP IDLE
(2)
BOR POR
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 PORIO: V
DD
POR Flag bit
Set by hardware at detection of a V
DD
POR event.
1 = A Power-on Reset has occurred due to V
DD
voltage
0 = A Power-on Reset has not occurred due to V
DD
voltage
bit 30 PORCORE: Core Voltage POR Flag bit
Set by hardware at detection of a core POR event.
1 = A Power-on Reset has occurred due to core voltage
0 = A Power-on Reset has not occurred due to core voltage
bit 29-28 Unimplemented: Read as ‘0
bit 27 BCFGERR: Primary Configuration Registers Error Flag bit
1 = An error occurred during a read of the Primary Configuration registers
0 = No error occurred during a read of the Primary Configuration registers
bit 26 BCFGFAIL: Primary/Secondary Configuration Registers Error Flag bit
1 = An error occurred during a read of the Primary and Alternate Configuration registers
0 = No error occurred during a read of the Primary and Alternate Configuration registers
bit 25-10 Unimplemented: Read as ‘0
bit 9 CMR: Configuration Mismatch Reset Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred
bit 8 Unimplemented: Read as ‘0
bit 7 EXTR: External Reset (MCLR) Pin Flag bit
1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset Flag bit
1 = Software Reset was executed
0 = Software Reset was not executed
bit 5 Unimplemented: Read as ‘0
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
Note 1: User software must clear bits in this register to view the next detection.
2: The IDLE bit will also be set when the device wakes from Sleep mode.
PIC32MM0064GPL036 FAMILY
DS60001324C-page 48 2015-2018 Microchip Technology Inc.
bit 3 SLEEP: Wake from Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
bit 2 IDLE: Wake from Idle Flag bit
(2)
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1 BOR: Brown-out Reset Flag bit
1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred
REGISTER 6-1: RCON: RESET CONTROL REGISTER
(1)
(CONTINUED)
Note 1: User software must clear bits in this register to view the next detection.
2: The IDLE bit will also be set when the device wakes from Sleep mode.
REGISTER 6-2: RSWRST: SOFTWARE RESET REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC
SWRST
(1,2)
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-1 Unimplemented: Read as ‘0
bit 0 SWRST: Software Reset Trigger bit
(1,2)
1 = Enables Software Reset event
0 = No effect
Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to
Section 23.4 “System Registers Write Protection” for details.
2: Once this bit is set, any read of the RSWRST register will cause a Reset to occur.
2015-2018 Microchip Technology Inc. DS60001324C-page 49
PIC32MM0064GPL036 FAMILY
REGISTER 6-3: RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/HS
— — —WDTR
23:16
R/W-0/HS U-0 U-0 U-0 R/W-0/HS U-0 R/W-0/HS R/W-0/HS
SWNMI — — —GNMI —CFWDTS
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NMICNT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NMICNT<7:0>
Legend: HS = Hardware Settable bits
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-25 Unimplemented: Read as ‘0
bit 24 WDTR: Watchdog Timer Time-out in Run Mode Flag bit
1 = A Run mode WDT time-out has occurred and caused an NMI
0 = WDT time-out has not occurred
Setting this bit will cause a WDT NMI event and NMICNT<15:0> will begin counting.
bit 23 SWNMI: Software NMI Trigger bit
1 = An NMI has been generated
0 = An NMI was not generated
bit 22-20 Unimplemented: Read as ‘0
bit 19 GNMI: Software General NMI Trigger bit
1 = A general NMI has been generated
0 = A general NMI was not generated
bit 18 Unimplemented: Read as ‘0
bit 17 CF: Clock Fail Detect bit
1 = FSCM has detected clock failure and caused an NMI
0 = FSCM has not detected clock failure
Setting this bit will cause a CF NMI event, but will not cause a clock switch to the FRC.
bit 16 WDTS: Watchdog Timer Time-out in Sleep Mode Flag bit
1 = WDT time-out has occurred during Sleep mode and caused a wake-up from Sleep
0 = WDT time-out has not occurred during Sleep mode
Setting this bit will cause a WDT NMI.
bit 15-0 NMICNT<15:0>: NMI Reset Counter Value bits
These bits specify the reload value used by the NMI Reset counter.
FFFFh-0001h = Number of SYSCLK cycles before a device Reset occurs
(2)
0000h = No delay between NMI assertion and device Reset event
Note 1: Writes to this register require an unlock sequence. Refer to Section 23.4 “System Registers Write
Protection” for details.
2: If a Watchdog Timer NMI event (when not in Sleep mode) is cleared before this counter reaches 0’, no
device Reset is asserted. This NMI Reset counter is only applicable to the Watchdog Timer NMI event.
PIC32MM0064GPL036 FAMILY
DS60001324C-page 50 2015-2018 Microchip Technology Inc.
REGISTER 6-4: PWRCON: POWER CONTROL REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
7:0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— SBOREN
(3)
RETEN
(2)
VREGS
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0
bit 2 SBOREN: BOR During Sleep Control bit
(3)
1 = BOR is turned on
0 = BOR is turned off
bit 1 RETEN: Output Level of the Regulator During Sleep Selection bit
(2)
1 = Writing a ‘1’ to this bit will cause the main regulator to be put in a low-power state during Sleep mode
0 = Writing a ‘0’ to this bit will have no effect
bit 0 VREGS: Voltage Regulator Standby Enable bit
(2)
1 = Voltage regulator will remain active during Sleep mode
0 = Voltage regulator will go to Standby mode during Sleep mode
Note 1: Writes to this register require an unlock sequence. Refer to Section 23.4 “System Registers Write
Protection” for details.
2: Refer to Section 22.4 “On-Chip Voltage Regulator Low-Power Modes” for details.
3: This bit is enabled only when the BOREN<1:0> Configuration bits (FPOR<1:0>) are set to ‘01’.
2015-2018 Microchip Technology Inc. DS60001324C-page 51
PIC32MM0064GPL036 FAMILY
7.0 CPU EXCEPTIONS AND
INTERRUPT CONTROLLER
PIC32MM0064GPL036 family devices generate inter-
rupt requests in response to interrupt events from
peripheral modules. The interrupt control module exists
externally to the CPU logic and prioritizes the interrupt
events before presenting them to the CPU.
The CPU handles interrupt events as part of the excep-
tion handling mechanism, which is described in
Section 7.1 “CPU Exceptions”.
The PIC32MM0064GPL036 family device interrupt
module includes the following features:
Single Vector or Multivector mode Operation
Five External Interrupts with Edge Polarity Control
Interrupt Proximity Timer
Module Freeze in Debug mode
Seven User-Selectable Priority Levels for each
Vector
Four User-Selectable Subpriority Levels within
each Priority
One Shadow Register Set that can be used for
any Priority Level, Eliminating Software Context
Switching and Reducing Interrupt Latency
Software can Generate any Interrupt
User-Configurable Interrupt Vectors’ Offset and
Vector Table Location
Figure 7-1 shows the block diagram for the interrupt
controller and CPU exceptions.
FIGURE 7-1: CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 8. “Interrupts”
(DS60001108) and Section 50. “CPU for
Devices with MIPS32
®
microAptiv™ and
M-Class Cores” (DS60001192) in the
“PIC32 Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32). The informa-
tion in this data sheet supersedes the
information in the FRM
Interrupt Requests
Vector Number and Offset
CPU Core
Priority Level
Shadow Set Number
SYSCLK
(Exception Handling)
Interrupt Controller
PIC32MM0064GPL036 FAMILY
DS60001324C-page 52 2015-2018 Microchip Technology Inc.
7.1 CPU Exceptions
CPU Coprocessor 0 contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including boundary cases in data,
external events or program errors. Ta b l e 7-1 lists the exception types in order of priority.
TABLE 7-1: MIPS32
®
microAptiv™ UC MICROPROCESSOR CORE EXCEPTION TYPES
Exception Type
(In Order of
Priority) Description Branches to Status
Bits Set Debug Bits
Set EXCCODE XC32 Function Name
Highest Priority
Reset Assertion of MCLR.0xBFC0_0000 BEV, ERL _on_reset
Soft Reset Execution of a RESET instruction. 0xBFC0_0000 BEV, SR,
ERL
_on_reset
DSS EJTAG debug single step. 0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
DSS — —
DINT EJTAG debug interrupt. Caused by setting the
EjtagBrk bit in the ECR register.
0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
DINT — —
NMI Non-maskable interrupt. 0xBFC0_0000 BEV, NMI,
ERL
_nmi_handler
Interrupt Assertion of unmasked hardware or software
interrupt signal.
See Ta b l e 7-2 IPL<2:0> Int (0x00) See Ta b l e 7-2
DIB EJTAG debug hardware instruction break matched. 0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
DIB — —
AdEL Load address alignment error. EBASE + 0x180 EXL ADEL (0x04) _general_exception_handler
IBE Instruction fetch bus error. EBASE + 0x180 EXL IBE (0x06) _general_exception_handler
DBp EJTAG breakpoint (execution of SDBBP
instruction).
0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
DBp — —
Sys Execution of SYSCALL instruction. EBASE + 0x180 EXL Sys (0x08) _general_exception_handler
Bp Execution of BREAK instruction. EBASE + 0x180 EXL Bp (0x09) _general_exception_handler
2015-2018 Microchip Technology Inc. DS60001324C-page 53
PIC32MM0064GPL036 FAMILY
CpU Execution of a coprocessor instruction for a
coprocessor that is not enabled.
EBASE + 0x180 CU, EXL CpU (0x0B) _general_exception_handler
RI Execution of a reserved instruction. EBASE + 0x180 EXL RI (0x0A) _general_exception_handler
Ov Execution of an arithmetic instruction that
overflowed.
EBASE + 0x180 EXL Ov (0x0C) _general_exception_handler
Tr Execution of a trap (when trap condition is true). EBASE + 0x180 EXL Tr (0x0D) _general_exception_handler
DDBL EJTAG data address break (address only) or
EJTAG data value break on load (address and
value).
0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
DDBL for a
load
instruction
or DDBS for
a store
instruction
— —
DDBS EJTAG data address break (address only) or
EJTAG data value break on store (address and
value).
0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
DDBL for a
load
instruction
or DDBS for
a store
instruction
— —
AdES Store address alignment error. EBASE + 0x180 EXL ADES
(0x05)
_general_exception_handler
DBE Load or store bus error. EBASE + 0x180 EXL DBE (0x07) _general_exception_handler
CBrk EJTAG complex breakpoint. 0xBFC0_0480
(ProbEn = 0 in ECR)
0xBFC0_0200
(ProbEn = 1 in ECR)
DIBImpr,
DDBLImpr
and/or
DDBSImpr
— —
Lowest Priority
TABLE 7-1: MIPS32
®
microAptiv™ UC MICROPROCESSOR CORE EXCEPTION TYPES (CONTINUED)
Exception Type
(In Order of
Priority) Description Branches to Status
Bits Set Debug Bits
Set EXCCODE XC32 Function Name
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DS60001324C-page 54 2015-2018 Microchip Technology Inc.
7.2 Interrupts
The PIC32MM0064GPL036 family uses fixed offset for vector spacing. For details, refer to Section 8. “Interrupts” (DS60001108) in the “PIC32 Family Reference
Manual. Table 7-2 provides the interrupt related vectors and bits information.
TABLE 7-2: INTERRUPTS
Interrupt Source MPLAB
®
XC32 Vector Name Vector
Number
Interrupt Related Bits Location Persistent
Interrupt
Flag Enable Priority Subpriority
Core Timer _CORE_TIMER_VECTOR 0IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> No
Core Software 0 _CORE_SOFTWARE_0_VECTOR 1IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> No
Core Software 1 _CORE_SOFTWARE_1_VECTOR 2IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> No
External 0 _EXTERNAL_0_VECTOR 3IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> No
External 1 _EXTERNAL_1_VECTOR 4IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> No
External 2 _EXTERNAL_2_VECTOR 5IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> No
External 3 _EXTERNAL_3_VECTOR 6IFS0<6> IEC0<6> IPC1<20:18> IPC1<17:16> No
External 4 _EXTERNAL_4_VECTOR 7IFS0<7> IEC0<7> IPC1<28:26> IPC1<25:24> No
PORTA Change Notification _CHANGE_NOTICE_A_VECTOR 8IFS0<8> IEC0<8> IPC2<4:2> IPC2<1:0> No
PORTB Change Notification _CHANGE_NOTICE_B_VECTOR 9IFS0<9> IEC0<9> IPC2<12:10> IPC2<9:8> No
PORTC Change Notification _CHANGE_NOTICE_C_VECTOR 10 IFS0<10> IEC0<10> IPC2<20:18> IPC2<17:16> No
Timer1 _TIMER_1_VECTOR 11 IFS0<11> IEC0<11> IPC2<28:26> IPC2<25:24> No
Comparator 1 _COMPARATOR_1_VECTOR 12 IFS0<12> IEC0<12> IPC3<4:2> IPC3<1:0> No
Comparator 2 _COMPARATOR_2_VECTOR 13 IFS0<13> IEC0<13> IPC3<12:10> IPC3<9:8> No
Real-Time Clock Alarm _RTCC_VECTOR 14 IFS0<14> IEC0<14> IPC3<20:18> IPC3<17:16> No
ADC Conversion _ADC_VECTOR 15 IFS0<15> IEC0<15> IPC3<28:26> IPC3<25:24> No
CRC _CRC_VECTOR 16 IFS0<16> IEC0<16> IPC4<4:2> IPC4<1:0> Yes
High/Low-Voltage Detect _HLVD_VECTOR 17 IFS0<17> IEC0<17> IPC4<12:10> IPC4<9:8> Yes
Logic Cell 1 _CLC1_VECTOR 18 IFS0<18> IEC0<18> IPC4<20:18> IPC4<17:16> No
Logic Cell 2 _CLC2_VECTOR 19 IFS0<19> IEC0<19> IPC4<28:26> IPC4<25:24> No
SPI1 Error _SPI1_ERR_VECTOR 20 IFS0<20> IEC0<20> IPC5<4:2> IPC5<1:0> Yes
SPI1 Transmission _SPI1_TX_VECTOR 21 IFS0<21> IEC0<21> IPC5<12:10> IPC5<9:8> Yes
SPI1 Reception _SPI1_RX_VECTOR 22 IFS0<22> IEC0<22> IPC5<20:18> IPC5<17:16> Yes
2015-2018 Microchip Technology Inc. DS60001324C-page 55
PIC32MM0064GPL036 FAMILY
UART1 Reception _UART1_RX_VECTOR 23 IFS0<23> IEC0<23> IPC5<28:26> IPC5<25:24> Yes
UART1 Transmission _UART1_TX_VECTOR 24 IFS0<24> IEC0<24> IPC6<4:2> IPC6<1:0> Yes
UART1 Error _UART1_ERR_VECTOR 25 IFS0<25> IEC0<25> IPC6<12:10> IPC6<9:8> Yes
CCP1 Input Capture or Output Compare _CCP1_VECTOR 29 IFS0<29> IEC0<29> IPC7<12:10> IPC7<9:8> No
CCP1 Timer _CCT1_VECTOR 30 IFS0<30> IEC0<30> IPC7<20:18> IPC7<17:16> No
CCP2 Input Capture or Output Compare _CCP2_VECTOR 31 IFS0<31> IEC0<31> IPC7<28:26> IPC7<25:24> No
CCP2 Timer _CCT2_VECTOR 32 IFS1<0> IEC1<0> IPC8<4:2> IPC8<1:0> No
CCP3 Input Capture or Output Compare _CCP3_VECTOR 33 IFS1<1> IEC1<1> IPC8<12:10> IPC8<9:8> No
CCP3 Timer _CCT3_VECTOR 34 IFS1<2> IEC1<2> IPC8<20:18> IPC8<17:16> No
RESERVED 35 — —
RESERVED 36 — —
SPI2 Error _SPI2_ERR_VECTOR 37 IFS1<5> IEC1<5> IPC9<12:10> IPC9<9:8> Yes
SPI2 Transmission _SPI2_TX_VECTOR 38 IFS1<6> IEC1<6> IPC9<20:18> IPC9<17:16> Yes
SPI2 Reception _SPI2_RX_VECTOR 39 IFS1<7> IEC1<7> IPC9<28:26> IPC9<25:24> Yes
UART2 Reception _UART2_RX_VECTOR 40 IFS1<8> IEC1<8> IPC10<4:2> IPC10<1:0> Yes
UART2 Transmission _UART2_TX_VECTOR 41 IFS1<9> IEC1<9> IPC10<12:10> IPC10<9:8> Yes
UART2 Error _UART2_ERR_VECTOR 42 IFS1<10> IEC1<10> IPC10<20:18> IPC10<17:16> Yes
NVM Program or Erase Complete _NVM_VECTOR 46 IFS1<14> IEC1<14> IPC11<20:18> IPC11<17:16> Yes
Core Performance Counter _PERFORMANCE_COUNTER_VECTOR 47 IFS1<15> IEC1<15> IPC11<28:26> IPC11<25:24> No
TABLE 7-2: INTERRUPTS (CONTINUED)
Interrupt Source MPLAB
®
XC32 Vector Name Vector
Number
Interrupt Related Bits Location Persistent
Interrupt
Flag Enable Priority Subpriority
PIC32MM0064GPL036 FAMILY
DS60001324C-page 56 2015-2018 Microchip Technology Inc.
TABLE 7-3: INTERRUPT REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
F000 INTCON 31:16 — — — — VS<6:0>
0000
15:0 ———MVEC —TPC<2:0>— — INT4EP INT3EP INT2EP INT1EP INT0EP
0000
F010 PRISS 31:16 PRI7SS<3:0> PRI6SS<3:0> PRI5SS<3:0> PRI4SS<3:0>
0000
15:0 PRI3SS<3:0> PRI2SS<3:0> PRI1SS<3:0> — — —SS0
0000
F020 INTSTAT 31:16 — — — —
0000
15:0 — — — — SRIPL<2:0> SIRQ<7:0>
0000
F030 IPTMR 31:16 IPTMR<31:0>
0000
15:0
0000
F040 IFS0 31:16 CCP2IF CCT1IF CCP1IF — — U1EIF U1TXIF U1RXIF SPI1RXIF SPI1TXIF SPI1EIF CLC2IF CLC1IF LVDIF CRCIF
0000
15:0 AD1IF RTCCIF CMP2IF CMP1IF T1IF CNCIF
(2)
CNBIF CNAIF INT4IF INT3IF INT2IF INT1IF INT0IF CS1IF CS0IF CTIF
0000
F050 IFS1 31:16 — — — — — — — —
0000
15:0 CPCIF NVMIF — — U2EIF U2TXIF U2RXIF SPI2RXIF SPI2TXIF SPI2EIF CCT3IF CCP3IF CCT2IF
0000
F0C0 IEC0 31:16 CCP2IE CCT1IE CCP1IE — — U1EIE U1TXIE U1RXIE SPI1RXIE SPI1TXIE SPI1EIE CLC2IE CLC1IE LVDIE CRCIE
0000
15:0 AD1IE RTCCIE CMP2IE
CMP1IE
T1IE CNCIE
(2)
CNBIE CNAIE INT4IE INT3IE INT2IE INT1IE INT0IE CS1IE CS0IE CTIE
0000
F0D0 IEC1 31:16 — — — —
0000
15:0 CPCIE NVMIE — — U2EIE U2TXIE U2RXIE SPI2RXIE SPI2TXIE SPI2EIE CCT3IE CCP3IE CCT2IE
0000
F140 IPC0 31:16 —— INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0>
0000
15:0 —— CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0>
0000
F150 IPC1 31:16 —— INT4IP<2:0> INT4IS<1:0> — — — INT3IP<2:0> INT3IS<1:0>
0000
15:0 —— INT2IP<2:0> INT2IS<1:0> — — — INT1IP<2:0> INT1IS<1:0>
0000
F160 IPC2 31:16 —— T1IP<2:0> T1IS<1:0> — — — CNCIP<2:0>
(2)
CNCIS<1:0>
(2)
0000
15:0 —— CNBIP<2:0> CNBIS<1:0> — — — CNAIP<2:0> CNAIS<1:0>
0000
F170 IPC3 31:16 —— AD1IP<2:0> AD1IS<1:0> — — RTCCIP<2:0> RTCCIS<1:0>
0000
15:0 —— CMP2IP<2:0> CMP2IS<1:0> — — CMP1IP<2:0> CMP1IS<1:0>
0000
F180 IPC4 31:16 —— CLC2IP<2:0> CLC2IS<1:0> — — CLC1IP<2:0> CLC1IS<1:0>
0000
15:0 —— LVDIP<2:0> LVDIS<1:0> — — — CRCIP<2:0> CRCIS<1:0>
0000
F190 IPC5 31:16 —— U1RXIP<2:0> U1RXIS<1:0> — — SPI1RXIP<2:0> SPI1RXIS<1:0>
0000
15:0 —— SPI1TXIP<2:0> SPI1TXIS<1:0> — — SPI1EIP<2:0> SPI1EIS<1:0>
0000
F1A0 IPC6 31:16 — — — — — —
0000
15:0 —— U1EIP<2:0> U1EIS<1:0> — — U1TXIP<2:0> U1TXIS<1:0>
0000
F1B0 IPC7 31:16 CCP2IP<2:0> CCP2IS<1:0> — — CCT1IP<2:0> CCT1IS<1:0>
0000
15:0 —— CCP1IP<2:0> CCP1IS<1:0> — —
0000
Legend:
— = unimplemented, read as
0
’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
2: These bits are not available on 20-pin devices.
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F1C0 IPC8 31:16 — — — CCT3IP<2:0> CCT3IS<1:0>
0000
15:0 —— CCP3IP<2:0> CCP3IS<1:0> — — CCT2IP<2:0> CCT2IS<1:0>
0000
F1D0 IPC9 31:16 —— SPI2RXIP<2:0> SPI2RXIS<1:0> — — SPI2TXIP<2:0> SPI2TXIS<1:0>
0000
15:0 —— SPI2EIP<2:0> SPI2EIS<1:0> — —
0000
F1E0 IPC10 31:16 — — — — U2EIP<2:0> U2EIS<1:0>
0000
15:0 —— U2TXIP<2:0> U2TXIS<1:0> — — U2RXIP<2:0> U2RXIS<1:0>
0000
F1F0 IPC11 31:16 —— CPCIP<2:0> CPCIS<1:0> — — — NVMIP<2:0> NVMIS<1:0>
0000
15:0 — — — — — —
0000
TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend:
— = unimplemented, read as
0
’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
2: These bits are not available on 20-pin devices.
Sgacing Bemeen Vectors.
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DS60001324C-page 58 2015-2018 Microchip Technology Inc.
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
23:16
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VS<6:0>
15:8
U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— — MVEC —TPC<2:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — INT4EP INT3EP INT2EP INT1EP INT0EP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-23 Unimplemented: Read as0
bit 22-16 VS<6:0>: Vector Spacing bits
Spacing Between Vectors:
0000000 = 0 Bytes
0000001 = 8 Bytes
0000010 = 16 Bytes
0000100 = 32 Bytes
0001000 = 64 Bytes
0010000 = 128 Bytes
0100000 = 256 Bytes
1000000 = 512 Bytes
All other values are reserved. The operation of this device is undefined if a reserved value is written to this
field. If MVEC = 0, this field is ignored.
bit 15-13 Unimplemented: Read as0
bit 12 MVEC: Multivector Configuration bit
1 = Interrupt controller configured for Multivectored mode
0 = Interrupt controller configured for Single Vectored mode
bit 11 Unimplemented: Read as0
bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits
111 = Interrupts of Group Priority 7 or lower start the interrupt proximity timer
110 = Interrupts of Group Priority 6 or lower start the interrupt proximity timer
101 = Interrupts of Group Priority 5 or lower start the interrupt proximity timer
100 = Interrupts of Group Priority 4 or lower start the interrupt proximity timer
011 = Interrupts of Group Priority 3 or lower start the interrupt proximity timer
010 = Interrupts of Group Priority 2 or lower start the interrupt proximity timer
001 = Interrupts of Group Priority 1 start the interrupt proximity timer
000 = Disables interrupt proximity timer
bit 7-5 Unimplemented: Read as0
bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
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bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER (CONTINUED)
REGISTER 7-2: PRISS: PRIORITY SHADOW SELECT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRI7SS<3:0>
(1)
PRI6SS<3:0>
(1)
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRI5SS<3:0>
(1)
PRI4SS<3:0>
(1)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRI3SS<3:0>
(1)
PRI2SS<3:0>
(1)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
PRI1SS<3:0>
(1)
SS0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 PRI7SS<3:0>: Interrupt with Priority Level 7 Shadow Set bits
(1)
11111 = Reserved
0010 = Reserved
0001 = Interrupt with a priority level of 7 uses Shadow Set 1
0000 = Interrupt with a priority level of 7 uses Shadow Set 0
bit 27-24 PRI6SS<3:0>: Interrupt with Priority Level 6 Shadow Set bits
(1)
1111 = Reserved
0010 = Reserved
0001 = Interrupt with a priority level of 6 uses Shadow Set 1
0000 = Interrupt with a priority level of 6 uses Shadow Set 0
Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.
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bit 23-20 PRI5SS<3:0>: Interrupt with Priority Level 5 Shadow Set bits
(1)
1111 = Reserved
0010 = Reserved
0001 = Interrupt with a priority level of 5 uses Shadow Set 1
0000 = Interrupt with a priority level of 5 uses Shadow Set 0
bit 19-16 PRI4SS<3:0>: Interrupt with Priority Level 4 Shadow Set bits
(1)
1111 = Reserved
0010 = Reserved
0001 = Interrupt with a priority level of 4 uses Shadow Set 1
0000 = Interrupt with a priority level of 4 uses Shadow Set 0
bit 15-12 PRI3SS<3:0>: Interrupt with Priority Level 3 Shadow Set bits
(1)
1111 = Reserved
0010 = Reserved
0001 = Interrupt with a priority level of 3 uses Shadow Set 1
0000 = Interrupt with a priority level of 3 uses Shadow Set 0
bit 11-8 PRI2SS<3:0>: Interrupt with Priority Level 2 Shadow Set bits
(1)
1111 = Reserved
0010 = Reserved
0001 = Interrupt with a priority level of 2 uses Shadow Set 1
0000 = Interrupt with a priority level of 2 uses Shadow Set 0
bit 7-4 PRI1SS<3:0>: Interrupt with Priority Level 1 Shadow Set bits
(1)
1111 = Reserved
0010 = Reserved
0001 = Interrupt with a priority level of 1 uses Shadow Set 1
0000 = Interrupt with a priority level of 1 uses Shadow Set 0
bit 3-1 Unimplemented: Read as ‘0
bit 0 SS0: Single Vector Shadow Register Set bit
1 = Single vector is presented with a shadow set
0 = Single vector is not presented with a shadow set
REGISTER 7-2: PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED)
Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.
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REGISTER 7-3: INTSTAT: INTERRUPT STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
15:8
U-0 U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC
— — — SRIPL<2:0>
(1)
7:0
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
SIRQ<7:0>
Legend: HS = Hardware Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-11 Unimplemented: Read as0
bit 10-8 SRIPL<2:0>: Requested Priority Level for Single Vector Mode bits
(1)
111-000 = The priority level of the latest interrupt presented to the CPU
bit 7-0 SIRQ<7:0>: Last Interrupt Request Serviced Status bits
11111111-00000000 = The last interrupt request number serviced by the CPU
Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode.
REGISTER 7-4: IPTMR: INTERRUPT PROXIMITY TIMER REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IPTMR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IPTMR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IPTMR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IPTMR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IPTMR<31:0>: Interrupt Proximity Timer Reload bits
Used by the interrupt proximity timer as a reload value when the interrupt proximity timer is triggered by an
interrupt event.
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REGISTER 7-5: IFSx: INTERRUPT FLAG STATUS REGISTER x
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IFS<31:0>: Interrupt Flag Status bits
1 = Interrupt request has occurred
0 = No interrupt request has occurred
Note 1: This register represents a generic definition of the IFSx register. Refer to Table 7-3 for the exact bit
definitions.
REGISTER 7-6: IECx: INTERRUPT ENABLE CONTROL REGISTER x
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IEC<31-0>: Interrupt Enable bits
1 = Interrupt is enabled
0 = Interrupt is disabled
Note 1: This register represents a generic definition of the IECx register. Refer to Table 7-3 for the exact bit
definitions.
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REGISTER 7-7: IPCx: INTERRUPT PRIORITY CONTROL REGISTER x
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP3<2:0> IS3<1:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP2<2:0> IS2<1:0>
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP1<2:0> IS1<1:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP0<2:0> IS0<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0
bit 28-26 IP3<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 25-24 IS3<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 23-21 Unimplemented: Read as ‘0
bit 20-18 IP2<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 17-16 IS2<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 15-13 Unimplemented: Read as ‘0
Note 1: This register represents a generic definition of the IPCx register. Refer to Table 7-3 for the exact bit
definitions.
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DS60001324C-page 64 2015-2018 Microchip Technology Inc.
bit 12-10 IP1<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 9-8 IS1<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 7-5 Unimplemented: Read as0
bit 4-2 IP0<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 1-0 IS0<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
REGISTER 7-7: IPCx: INTERRUPT PRIORITY CONTROL REGISTER x
(1)
(CONTINUED)
Note 1: This register represents a generic definition of the IPCx register. Refer to Table 7-3 for the exact bit
definitions.
three differenl submodes (XT, HS and EC), which
2015-2018 Microchip Technology Inc. DS60001324C-page 65
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8.0 OSCILLATOR
CONFIGURATION
The PIC32MM0064GPL036 family oscillator system
has the following modules and features:
On-Chip PLL with User-Selectable Multiplier and
Output Divider to Boost Operating Frequency on
Select Internal and External Oscillator Sources
Primary High-Frequency Crystal Oscillator
Secondary Low-Frequency and Low-Power
Crystal Oscillator
On-Chip Fast RC (FRC) Oscillator with
User-Selectable Output Divider
Software-Controllable Switching between Various
Clock Sources
Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and Permits Safe Application
Recovery or Shutdown
Flexible Reference Clock Output (REFO)
A block diagram of the oscillator system is provided in
Figure 8-1. A block diagram of the REFO clock is
provided in Figure 8-2.
8.1 Fail-Safe Clock Monitor (FSCM)
The PIC32MM0064GPL036 family oscillator system
includes a Fail-Safe Clock Monitor (FSCM). The FSCM
monitors the SYSCLK for continuous operation. If it
detects that the SYSCLK has failed, it switches the
SYSCLK over to the FRC oscillator and triggers a Non-
Maskable Interrupt (NMI). When the NMI is executed,
software can attempt to restart the main oscillator or
shut down the system.
In Sleep mode, both the SYSCLK and the FSCM halt,
which prevents FSCM detection.
8.2 Clock Switching Operation
With few limitations, applications are free to switch
between any of the four clock sources (POSC, SOSC,
FRC and LPRC) under software control and at any
time. To limit the possible side effects that could result
from this flexibility, PIC32 devices have a safeguard
lock built into the switching process.
8.2.1 ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration
bit in FOSC must be programmed to ‘0’. (Refer to
Section 23.1 “Configuration Bits” for further details.)
If the FCKSM1 Configuration bit is unprogrammed (‘1’),
the clock switching function and Fail-Safe Clock
Monitor function are disabled; this is the default setting.
The NOSC<2:0> control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSC<2:0> bits
(OSCCON<14:12>) will reflect the clock source
selected by the FNOSC<2:0> Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled; it is held at ‘0’ at all
times.
Note: This data sheet summarizes the features
of the PIC32MM0064GPL036 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 59. “Oscillators
with DCO” (DS60001329) in the “PIC32
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com/PIC32). The infor-
mation in this data sheet supersedes the
information in the FRM.
Note: The Primary Oscillator mode has three
different submodes (XT, HS and EC), which
are determined by the POSCMOD<1:0>
Configuration bits. While an application
can switch to and from Primary Oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
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DS60001324C-page 66 2015-2018 Microchip Technology Inc.
8.2.2 OSCILLATOR SWITCHING
SEQUENCE
At a minimum, performing a clock switch requires this
basic sequence:
1. If desired, read the COSC<2:0> bits
(OSCCON<14:12>) to determine the current
oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register.
3. Write the appropriate value to the NOSC<2:0>
bits (OSCCON<10:8>) for the new oscillator
source.
4. Set the OSWEN bit to initiate the oscillator
switch.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSCx bits with the new value of the NOSCx
bits. If they are the same, then the clock switch
is a redundant operation. In this case, the
OSWEN bit is cleared automatically and the
clock switch is aborted.
2. If a valid clock switch has been initiated,
the SPLLRDY (CLKSTAT<7>) and CF
(OSCCON<3>) bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (SPLLRDY = 1).
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the
NOSC<2:0> bits values are transferred to the
COSC<2:0> bits.
6. The old clock source is turned off if it is not being
used by a peripheral, or enabled by device
configuration or a control register.
A recommended code sequence for a clock switch
includes the following:
1. Disable interrupts during the OSCCON register
unlock and write sequence.
2. Execute the unlock sequence for OSCCON by
writing 0xAA996655 and 0x556699AA to the
SYSKEY register.
3. Write the new oscillator source to the
NOSC<2:0> bits.
4. Set the OSWEN bit.
5. Relock the OSCCON register.
6. Continue to execute code that is not clock-sensitive
(optional).
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in Example 8-1.
EXAMPLE 8-1: BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
Note 1: The processor will continue to execute
code throughout the clock switching
sequence. Timing-sensitive code should
not be executed during this time.
2: Direct clock switches between any
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transi-
tional clock source between the two PLL
modes.
SYSKEY = 0x00000000; // force lock
SYSKEY = 0xAA996655; // unlock
SYSKEY = 0x556699AA;
OSCCONbits.NOSC = 3; // select the new
clock source
OSCCONSET = 1; //
set the OSWEN bit
SYSKEY = 0x00000000; // force lock
while (
OSCCONbits.OSWEN);
//
optional wait for
switch operation
cc
2015-2018 Microchip Technology Inc. DS60001324C-page 67
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FIGURE 8-1: PIC32MM0064GPL036 FAMILY OSCILLATOR DIAGRAM
Note 1: Refer to Table 26-18 in Section 26.0 “Electrical Characteristics” for frequency limitations.
To Timer1, RTCC, MCCP/SCCP and CLC
Clock Control Logic
Fail-Safe
Clock
Monitor
COSC<2:0>
NOSC<2:0>
OSWEN
FCKSM<1:0>
Secondary Oscillator (SOSC)
SOSCSEL
SOSCO/
SOSCI
POSC (HS, EC)
FRCDIV<2:0>
To Timer1, WDT, RTCC
FRC
Oscillator
LPRC
Oscillator
SOSC
LPRC
FRCDIV
TUN<5:0>
Postscaler

N
PLLICLK
F
IN(1)
PLLODIV<2:0>
32.768 kHz
PLLMULT<6:0>
SYSCLK (F
SYS
)
(N)
(N)
REFCLKO
OE
To MCCP, SCCP
Reference Clock
RODIV<14:0> (N)
ROTRIM<8:0> (M)

N
SPLL
REFCLKI
POSC
FRC
LPRC
SOSC
SYSCLK
ROSEL<3:0>
OSC2
OSC1/
Primary
(M)
PLL x M
F
PLL
(1)
To ADC, WDT, UART
Fvco
(1)
System PLL
REFO1CON REFO1TRIM
2N
M
512
----------+


8 MHz
Oscillator (POSC)
2 MHz F
IN
24 MHz
16 MHz F
VCO
96 MHz
SPLLVCO
and SPIx
POSCMOD<1:0>
and Flash Controller
PBCLK (F
PB
)
32 kHz
SOSCEN
FNOSC<2:0>
SCLKI
CLKI
PIC32MM0064GPL036 FAMILY
DS60001324C-page 68
2015-2018 Microchip Technology Inc.
FIGURE 8-2: REFERENCE OSCILLATOR CLOCK DIAGRAM
FRC
PLLMULT<6:0>
PLLODIV<2:0>
COSC<2:0>
SYSCLK
PBCLK
25 MHz Max
ROSEL<3:0>
RODIV<14:0>
ROTRIM<8:0>
OE
REFCLKO
50 MHz Max
SPI Module
SPI
Module
MCLKSEL
MCCP/SCCP
Module
CLKSEL<1:0>
N
N
(Note 1)
Note 1:
Support circuitry for crystal is not shown.
PLLICLK
UART
UART
Module
CLKSEL<1:0>
25 MHz Max
2015-2018 Microchip Technology Inc. DS60001324C-page 69
PIC32MM0064GPL036 FAMILY
8.3 Oscillator Control Registers
TABLE 8-1: OSCILLATOR CONFIGURATION REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(2)
Bit Range
Bits
All Resets
(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2000 OSCCON 31:16 — — FRCDIV<2:0> — — —
0000
15:0 COSC<2:0> NOSC<2:0> CLKLOCK SLPEN CF SOSCEN OSWEN
xx0x
2020 SPLLCON 31:16 — — PLLODIV<2:0> PLLMULT<6:0>
0001
15:0 PLLICLK — —
0000
20A0 REFO1CON 31:16 RODIV<14:0>
0000
15:0 ON SIDL OE RSLP DIVSWEN ACTIVE — — ROSEL<3:0>
0000
20B0 REFO1TRIM 31:16 ROTRIM<8:0> — —
0000
15:0 — — — —
0000
20F0 CLKSTAT 31:16 — —
0000
15:0 SPLLRDY LPRCRDY SOSCRDY POSCRDY SPDIVRDY FRCRDY
0000
2200 OSCTUN 31:16 — —
0000
15:0 — — — — TUN<5:0>
0000
Legend:
x
= unknown value on Reset; — = unimplemented, read as ‘
0
’. Reset values are shown in hexadecimal.
Note 1:
Reset values are dependent on the FOSCSEL Configuration bits and the type of Reset.
2:
All registers in this table have corresponding CLR, SET and INV registers at their virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively.
PIC32MM0064GPL036 FAMILY
DS60001324C-page 70
2015-2018 Microchip Technology Inc.
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — FRCDIV<2:0>
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — —
15:8
U-0 R-y, HS, HC R-y, HS, HC R-y, HS, HC U-0 R/W-y R/W-y R/W-y
—COSC<2:0>
(3)
—NOSC<2:0>
(3)
7:0
R/W-0 U-0 U-0 R/W-0 R/W-0, HS U-0 R/W-y R/W-y, HC
CLKLOCK SLPEN CF —SOSCEN
(4)
OSWEN
(2)
Legend:
HC = Hardware Clearable bit HS = Hardware Settable bit y = Value set from Configuration bits on Reset
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-27 Unimplemented: Read as0
bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default setting)
bit 23-15 Unimplemented: Read as0
bit 14-12 COSC<2:0>: Current Oscillator Selection bits
(3)
111 and 110 = Reserved (selects internal Fast RC (FRC) Oscillator divided by the FRCDIV<2:0> bits (FRCDIV))
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (XT, HS or EC)
001 = System PLL (SPLL)
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)
bit 11 Unimplemented: Read as0
Note 1: Writes to this register require an unlock sequence. Refer to Section 23.4 “System Registers Write
Protection” for details.
2: The Reset value for this bit depends on the setting of the IESO (FOSCSEL<7>) Configuration bit. When
IESO = 1, the Reset value is ‘1’. When IESO = 0, the Reset value is ‘0’.
3: The Reset value for these bits matches the setting of the FNOSC<2:0> (FOSCSEL<2:0>) Configuration bits.
4: The Reset value for this bit matches the setting of the SOSCEN (FOSCSEL<6>) Configuration bit.
2015-2018 Microchip Technology Inc. DS60001324C-page 71
PIC32MM0064GPL036 FAMILY
bit 10-8 NOSC<2:0>: New Oscillator Selection bits
(3)
111 and 110 = Reserved (selects internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV))
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (XT, HS or EC)
001 = System PLL (SPLL)
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)
On Reset, these bits are set to the value of the FNOSC<2:0> Configuration bits (FOSCSEL<2:0>).
bit 7 CLKLOCK: Clock Selection Lock Enable bit
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
bit 6-5 Unimplemented: Read as ‘0
bit 4 SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 2 Unimplemented: Read as0
bit 1 SOSCEN: Secondary Oscillator (SOSC) Enable bit
(4)
1 = Enables Secondary Oscillator
0 = Disables Secondary Oscillator
bit 0 OSWEN: Oscillator Switch Enable bit
(2)
1 = Initiates an oscillator switch to a selection specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER
(1)
(CONTINUED)
Note 1: Writes to this register require an unlock sequence. Refer to Section 23.4 “System Registers Write
Protection” for details.
2: The Reset value for this bit depends on the setting of the IESO (FOSCSEL<7>) Configuration bit. When
IESO = 1, the Reset value is ‘1’. When IESO = 0, the Reset value is0’.
3: The Reset value for these bits matches the setting of the FNOSC<2:0> (FOSCSEL<2:0>) Configuration bits.
4: The Reset value for this bit matches the setting of the SOSCEN (FOSCSEL<6>) Configuration bit.
PIC32MM0064GPL036 FAMILY
DS60001324C-page 72
2015-2018 Microchip Technology Inc.
REGISTER 8-2: SPLLCON: SYSTEM PLL CONTROL REGISTER
(1)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — PLLODIV<2:0>
23:16
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
— PLLMULT<6:0>
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — —
7:0
R/W-y U-0 U-0 U-0 U-0 U-0 U-0 U-0
PLLICLK — — —
Legend: y = Values set from Configuration bits on Reset
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0
bit 26-24 PLLODIV<2:0>: System PLL Output Clock Divider bits
111 = PLL divide-by-256