DS28EA00 Datasheet by Maxim Integrated

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19-7831; Rev 2; 6/19
General Description
The DS28EA00 is a digital thermometer with 9-bit (0.5°C)
to 12-bit (1/16°C) resolution and alarm function with non-
volatile (NV), user-programmable upper and lower trigger
points. Each DS28EA00 has its own unique 64-bit registra-
tion number that is factory programmed into the chip. Data
is transferred serially through the 1-Wire® protocol, which
requires only one data line and a ground reference for com-
munication. The improved 1-Wire front-end with hysteresis
and glitch filter enables the DS28EA00 to perform reliably
in large 1-Wire networks. Unlike other 1-Wire thermom-
eters, the DS28EA00 has two additional pins to implement
a sequence-detect function. This feature allows the user to
discover the registration numbers according to the physical
device location in a chain, e.g., to measure the temperature
in a storage tower at different height. If the sequence-detect
function is not needed, these pins can be used as general-
purpose input or output. The DS28EA00 can derive the
power for its operation directly from the data line (“parasite
power”), eliminating the need for an external power supply.
Applications
Data Communication Equipment
Process Temperature Monitoring
HVAC Systems
Features
Digital Thermometer Measures Temperatures
from -40°C to +85°C
Thermometer Resolution is User Selectable from
9 to 12 Bits
Unique 1-Wire Interface Requires Only One Port
Pin for Communication
Each Device Has a Unique 64-Bit, Factory-
Lasered Registration Number
Multidrop Capability Simplifies Distributed
Temperature-Sensing Applications
Improved 1-Wire Interface with Hysteresis and
Glitch Filter
User-Definable NV Alarm Threshold Settings/User
Bytes
Alarm Search Command to Quickly Identify
Devices Whose Temperature is Outside of
Programmed Limits
Standard and Overdrive 1-Wire Speed
Two General-Purpose Programmable IO (PIO) Pins
Chain Function Sharing the PIO Pins to Detect
Physical Sequence of Devices in Network
Operating Range: +3.0V to +5.5V, -40°C to +85°C
Can Be Powered from Data Line
8-Pin μSOP Package
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
Pin Configuration appears at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
PART TEMP RANGE PIN-PACKAGE
DS28EA00U+ -40°C to +85°C 8 µSOP
DS28EA00U+T&R -40°C to +85°C 8 µSOP
DS28EA00
IO
PIOB PIOA
GND
VDD
VDD
NOTE: SCHEMATIC SHOWS PIO PINS WIRED FOR SEQUENCE-DETECT FUNCTION.
1-Wire
MASTER
#1
DS28EA00
IO
PIOB
PX. Y
MICROCONTROLLER
PIOA
GND
VDD
#2
DS28EA00
IO
PIOB PIOA
GND
VDD
#3
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
Ordering Information
Typical Operating Circuit
Click here for production status of specific part numbers.
IO Voltage Range to GND ....................................... -0.5V to +6V
IO Sink Current...................................................................20mA
Maximum PIOA or PIOB Pin Current ................................. 20mA
Maximum Current Through GND Pin .................................40mA
Operating Temperature Range ........................... -40°C to +85°C
Junction Temperature ...................................................... +150°C
Storage Temperature Range ............................ -55°C to +125°C
Soldering Temperature ..........................Refer to the IPC/JEDEC
J-STD-020 Specification.
(TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Supply Voltage VDD (Note 2) 3.0 5.5 V
Supply Current (Note 3) IDD VDD = +5.5V 1.5 mA
Standby Current IDDS VDD = +5.5V 1.5 µA
IO PIN: GENERAL DATA
1-Wire Pullup Voltage (Note 2) VPUP
Local power 3.0 VDD V
Parasite power 3.0 5.5
1-Wire Pullup Resistance RPUP (Notes 2, 4) 0.3 2.2
Input Capacitance CIO (Notes 3, 5) 1000 pF
Input Load Current ILIO pin at VPUP 0.1 1.5 µA
High-to-Low Switching Threshold VTL (Notes 3, 6, 7) 0.46 VPUP -
1.9V V
Input Low Voltage (Notes 2, 8) VIL
Parasite powered 0.5 V
VDD powered (Note 3) 0.7
Low-to-High Switching Threshold
(Notes 3, 6, 9) VTH Parasite power 1.0 VPUP -
1.1V V
Switching Hysteresis
(Notes 3, 6, 10) VHY Parasite power 0.21 1.7 V
Output Low Voltage (Note 11) VOL At 4mA 0.4 V
Recovery Time
(Notes 2, 12) tREC
Standard speed, RPUP = 2.2kΩ 5
µs
Overdrive speed, RPUP = 2.2kΩ 2
Overdrive speed, directly prior to reset
pulse; RPUP = 2.2kΩ 5
Rising-Edge Hold-Off Time
(Notes 3, 13) tREH
Standard speed 0.5 5.0 µs
Overdrive speed Not applicable (0)
Time-Slot Duration
(Notes 2, 14) tSLOT
Standard speed 65 µs
Overdrive speed 8
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time (Note 2) tRSTL
Standard speed 480 640 µs
Overdrive speed 48 80
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings
Electrical Characteristics
(TA = -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Presence-Detect High Time tPDH
Standard speed 15 60 µs
Overdrive speed 2 6
Presence-Detect Fall Time
(Notes 3, 15) tFPD
Standard speed 1.125 8.1 µs
Overdrive speed 0 1.3
Presence-Detect Low Time tPDL
Standard speed 60 240 µs
Overdrive speed 8 24
Presence-Detect Sample Time
(Notes 2, 16) tMSP
Standard speed 68.1 75 µs
Overdrive speed 7.3 10
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 2, 17) tW0L
Standard speed 60 120 µs
Overdrive speed 6 16
Write-One Low Time
(Notes 2, 17) tW1L
Standard speed 5 15 µs
Overdrive speed 1 2
IO PIN: 1-Wire READ
Read Low Time (Notes 2, 18) tRL
Standard speed 5 15 - δ µs
Overdrive speed 1 2 - δ
Read Sample Time (Notes 2, 18) tMSR
Standard speed tRL + δ 15 µs
Overdrive speed tRL + δ 2
PIO PINS
Input Low Voltage VILP (Note 2) 0.3 V
Input High Voltage (Note 2) VIHP VX = Max(VPUP, VDD) VX - 1.6 V
Input Load Current (Note 19) ILP Pin at GND -1.1 µA
Output Low Voltage (Note 11) VOLP At 4mA 0.4 V
Chain-On Pullup Impedance RCO (Note 3) 20 40 60
EEPROM
Programming Current IPROG (Notes 3, 20) 1.5 mA
Programming Time tPROG (Note 21) 10 ms
Write/Erase Cycles (En durance)
(Notes 22, 23) NCY
At +25°C 200,000
-40°C to +85°C 50,000
Data Retention (Notes 24, 25) tDR At +85°C (worst case) 10 Years
TEMPERATURE CONVERTER
Conversion Current ICONV (Notes 3, 20) 1.5 mA
Conversion Time (Note 26) tCONV
12-bit resolution (1/16°C) 750
ms
11-bit resolution (1/8°C) 375
10-bit resolution (1/4°C) 187.5
9-bit resolution (1/2°C) 93.75
Conversion Error ΔJ-10°C to +85°C -0.5 +0.5 °C
Below -10°C (Note 3) -0.5 +2.0
Converter Drift JD(Note 27) -0.2 +0.2 °C
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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Electrical Characteristics (continued)
(TA = -40°C to +85°C.) (Note 1)
Note 1: Specifications at TA = -40°C are guaranteed by design and not production tested.
Note 2: System requirement.
Note 3: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 4: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to parasitically powered systems with only one device and with the minimum
1-Wire recovery times. For more heavily loaded systems, local power or an active pullup such as that found in the
DS2482-x00, DS2480B, or DS2490 may be required. If longer tREC is used, higher RPUP values may be tolerable.
Note 5: Value is 25pF maximum with local power. Maximum value represents the internal parasite capacitance when VPUP is
first applied. If RPUP = 2.2kΩ, 2.5μs after VPUP has been applied, the parasite capacitance does not affect normal
communications.
Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function VDD, VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VDD, VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower
values of VTL, VTH, and VHY.
Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8: The voltage on IO must be less than or equal to VILMAX at all times when the master drives the line to a logic 0.
Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.
Note 11: The I-V characteristic is linear for voltages less than +1V.
Note 12: Applies to a single parasitically powered DS28EA00 attached to a 1-Wire line. These values also apply to networks of
multiple DS28EA00 with local supply.
Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Note 14: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 15: Interval during the negative edge on IO at the beginning of a presence-detect pulse between the time at which the voltage
is 80% of VPUP and the time at which the voltage is 20% of VPUP.
Note 16: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28EA00 present.
Minimum limit is tPDHMAX + tFPDMAX; the maximum limit is tPDHMIN + tPDLMIN.
Note 17: ε in Figure 13 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 18: δ in Figure 13 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Note 19: This load current is caused by the internal weak pullup, which asserts a logic 1 to the PIOB and PIOA pins. The logical
state of PIOB must not change during the execution of the Conditional Read ROM command.
Note 20: Current drawn from IO during EEPROM programming or temperature conversion interval in parasite-powered mode. The
pullup circuit on IO during the programming or temperature conversion interval should be such that the voltage at IO is
greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, then a low-impedance bypass of RPUP,
which can be activated during programming or temperature conversions, may need to be added. The bypass must be acti-
vated within 10μs from the beginning of the tPROG or tCONV interval, respectively.
Note 21: The tPROG interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the command byte for a
valid Copy Scratchpad sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and
the current drawn by the device has returned from IPROG to IL (parasite power) or IDDS (local power).
Note 22: Write-cycle endurance is degraded as TA increases.
Note 23: Not 100% production tested. Guaranteed by reliability monitor sampling.
Note 24: Data retention is degraded as TA increases.
Note 25: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data
sheet limit at operating temperature range is established by reliability testing.
Note 26: The tCONV interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the command byte for a
valid convert temperature sequence. The interval ends once the device’s self-timed temperature conversion cycle is com-
plete and the current drawn by the device has returned from ICONV to IL (parasite power) or IDDS (local power).
Note 27: Drift data is preliminary and based on a 1000-hour stress test performed on another device with comparable design
and fabricated in the same manufacturing process. This test was performed at greater than +85°C with VDD = +5.5V.
Confirmed thermal drift results for this device are pending the completion of a new 1000-hour stress test.
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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Electrical Characteristics (continued)
Detailed Description
The Block Diagram shows the relationships between the
major function blocks of the DS28EA00. The device has
three main data components: 64-bit registration number,
64-bit scratchpad, and alarm and configuration registers.
The 1-Wire ROM function control unit processes the ROM
function commands that allow the device to function in a
networked environment. The device function control unit
implements the device-specific control functions, such
as read/write, temperature conversion, setting the chain
state for sequence detection, and PIO access. The cyclic
redundancy check (CRC) generator assists the master
verifying data integrity when reading temperatures and
memory data. In the sequence-detect process, PIOB
functions as an input, while PIOA provides the connection
to the next device. The power-supply sensor allows the
master to remotely read whether the DS28EA00 has local
power available.
Figure 1 shows the hierarchical structure of the 1-Wire
protocol. The bus master must first provide one of the
eight ROM function commands: Read ROM, Match
ROM, Search ROM, Conditional (Alarm) Search ROM,
Conditional Read ROM, Skip ROM, Overdrive-Skip ROM,
Overdrive-Match ROM.
Upon completion of an overdrive ROM command execut-
ed at standard speed, the device enters overdrive mode,
where all subsequent communication occurs at a higher
speed. The protocol required for these ROM function
commands is described in Figure 11. After a ROM func-
tion command is successfully executed, the device-spe-
cific control functions become accessible and the master
can provide any one of the nine available commands. The
protocol for these control function commands is described
in Figure 9. All data is read and written least signifi-
cant (LS) bit first.
64-Bit Registration Number
Each DS28EA00 contains a unique registration number
that is 64 bits long. The first 8 bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The
last 8 bits are a CRC of the first 56 bits (see Figure 2 for
details). The 1-Wire CRC is generated using a polynomial
generator consisting of a shift register and XOR gates as
shown in Figure 3. The polynomial is X8 + X5 + X4 + 1.
Additional information about the 1-Wire CRC is available
in Application Note 27: Understanding and Using Cyclic
Redundancy Checks with Maxim iButton® Products.
The shift register bits are initialized to 0. Then starting
with the least significant bit of the family code, one bit at a
time is shifted in. After the eighth bit of the family code has
been entered, then the 48-bit serial number is entered.
After the last byte of the serial number has been entered,
the shift register contains the CRC value. Shifting in the 8
bits of CRC returns the shift register to all 0s.
iButton is a registered trademark of Maxim Integrated Products, Inc.
PIN NAME FUNCTION
1 IO 1-Wire Bus Interface and Parasitic Power Supply. Open-drain pin that requires external pullup resistor.
2, 3, 5 N.C. No Connection
4 GND Ground Supply
6 PIOA (DONE)Open-Drain PIOA Channel and Chain Output. For sequence detection, PIOA must be connected to
PIOB of the next device in the chain; leave open or connect to GND for the last device in the chain.
7 PIOB (EN)Open-Drain PIOB Channel and Chain Input. For sequence detection, PIOB of the first device in the
chain must be connected to GND.
8 VDD Power Supply. Must be connected to GND for operation in parasite-power mode.
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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Pin Description
Figure 1. Hierarchical Structure for 1-Wire Protocol
DS28EA00
POWER-SUPPLY
SENSOR
64-BIT
SCRATCHPAD
TEMPERATURE
SENSOR
8-BIT CRC
GENERATOR
1-Wire ROM
FUNCTION
CONTROL
DEVICE
FUNCTION
CONTROL
ALARM AND
CONFIGURATION
REGISTERS
64-BIT
REGISTRATION
NUMBER
PIOB (EN) PIOA (DONE)
IO
VDD
(ON)
INTERNAL VDD
RCO
AVAILABLE COMMANDS: DATA FIELD AFFECTED:
READ ROM
MATCH ROM
SEARCH ROM
CONDITIONAL SEARCH ROM
CONDITIONAL READ ROM
SKIP ROM
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
64-BIT ROM
64-BIT ROM
64-BIT ROM
64-BIT ROM, TEMPERATURE ALARM REGISTERS, SCRATCHPAD
64-BIT ROM, PIOB PIN STATE, CHAIN STATE
(NONE)
64-BIT ROM, OD-FLAG
64-BIT ROM, OD-FLAG
1-Wire ROM
FUNCTION COMMANDS
(SEE FIGURE 11)
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
CONVERT TEMPERATURE
READ POWER MODE
RECALL EEPROM
PIO ACCESS READ
PIO ACCESS WRITE
CHAIN
SCRATCHPAD
SCRATCHPAD
TEMPERATURE ALARM AND CONFIGURATION REGISTERS
SCRATCHPAD, TEMPERATURE ALARM REGISTERS
VDD PIN VOLTAGE
SCRATCHPAD, TEMPERATURE ALARM, AND CONFIGURATION REGISTERS
PIO PINS
PIO PINS
CHAIN STATE, PIOA PIN STATE
DS28EA00-SPECIFIC
CONTROL FUNCTION COMMANDS
(SEE FIGURE 9)
COMMAND LEVEL:
DS28EA00
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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Block Diagram
L} 5 QB
Memory Description
The memory map of the DS28EA00 is shown in Figure 4.
It consists of an 8-byte scratchpad and 3 bytes of back-
up EEPROM. The first 2 bytes form the Temperature
Readout register, which is updated after a temperature
conversion and is read only. The next 3 bytes are user-
writable; they contain the Temperature High (TH) and the
Temperature Low (TL) Alarm register and a Configuration
register. The remaining 3 bytes are “reserved.” They
power up with constant data and cannot be written by the
user. The TH, TL, and Configuration register data in the
scratchpad control the resolution of a temperature con-
version and decide whether a temperature is considered
as “alarming.” TH, TL, and Configuration can be copied
to the EEPROM to become nonvolatile. The scratchpad
is automatically loaded with EEPROM data when the
DS28EA00 powers up.
Figure 2. 64-Bit Registration Number
Figure 3. 1-Wire CRC Generator
Figure 4. Memory Map
MSB
8-BIT
CRC CODE 48-BIT SERIAL NUMBER
MSB MSBLSB
LSB
LSB
8-BIT FAMILY CODE
(42h)
MSBLSB
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
7TH
STAGE
8TH
STAGE
6TH
STAGE
5TH
STAGE
X0X1X2X3X4
POLYNOMIAL = X8 + X5 + X4 + 1
INPUT DATA
X5X6X7X8
SCRATCHPAD (POWER-UP STATE)
BYTE
ADDRESS
TEMPERATURE LSB (50h)0
TEMPERATURE MSB (05h)1
TH REGISTER OR USER BYTE 1*2
TL REGISTER OR USER BYTE 2*
*POWER-UP STATE DEPENDS ON VALUE(S) STORED IN EEPROM.
3
CONFIGURATION REGISTER*4
RESERVED (FFh)5
RESERVED (0Ch)6
RESERVED (10h)
BACKUP EEPROM
N/A
N/A
TH REGISTER OR USER BYTE 1
TL REGISTER OR USER BYTE 2
CONFIGURATION REGISTER
N/A
N/A
N/A7
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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7
The temperature reading is in °C using a 16-bit sign-
extended two’s complement format. Table 1 shows exam-
ples of temperature and the corresponding data for 12-bit
resolution. With two’s complement, the sign bit(s) is set if
the value is negative. If the device is configured for 12-bit
resolution, all bits in the LS byte are valid; for a reduced
resolution, bit 0 (11-bit mode), bits 0 to 1 (10-bit mode),
and bits 0 to 2 (9-bit mode) are undefined.
The result of a temperature conversion is automatically
compared to the values in the alarm registers to determine
whether an alarm condition exists. Alarm thresholds are
represented as two’s complement number. With 8 bits
available for sign and value, alarm thresholds can be set in
increments of 1°C. An alarm condition exists if a tempera-
ture conversion results in a value that is either higher than
or equal to the value stored in the TH register or lower
than or equal to the value stored in the TL register. If a
temperature alarm condition exists, the device responds to
the Conditional Search ROM command. The alarm condi-
tion is cleared if a subsequent temperature conversion
results in a temperature reading within the boundaries
defined by the data in the TH and TL registers.
Table 1. Temperature/Data Relationship
*The power-on reset value of the Temperature Readout register is +85°C.
ADDRRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0h 232221202-1 2-2 2-3 2-4 LS BYTE
1h S S S S S 262524MS BYTE
ADDRRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
2h S 26252423222120HIGH ALARM (TH)
3h S 26252423222120LOW ALARM (TL)
TEMPERATURE
(°C)
DIGITAL OUTPUT
(BINARY)
DIGITAL OUTPUT
(HEX)
+85* 0000 0101 0101 0000 0550h
+25.0625 0000 0001 1001 0001 0191h
+10.125 0000 0000 1010 0010 00A2h
+0.5 0000 0000 0000 1000 0008h
0 0000 0000 0000 0000 0000h
-0.5 1111 1111 1111 1000 FFF8h
-10.125 1111 1111 0101 1110 FF5Eh
-25.0625 1111 1110 0110 1111 FE6Fh
-40 1111 1101 1000 0000 FD80h
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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Register Detailed Descriptions
Temperature Readout Register Bitmap
Temperature Alarm Registers Bitmap
PIO Structure
Each PIO consists of an open-drain pulldown transistor
and an input path to read the pin state. The transistor is
controlled by the PIO output latch, as shown in Figure 5.
The device function control unit connects the PIO pins
logically to the 1-Wire interface. PIOA has a pullup path
to internal VDD to facilitate the sequence-detect function
(see the Block Diagram) in conjunction with the Chain
command; PIOB is truly an open-drain structure. The
power-on default state of the PIO output transistors is off;
high-impedance, on-chip resistors (not shown in Figure 5)
pull the PIO pins to internal VDD.
Chain Function
The chain function is a feature that allows the 1-Wire
master to discover the physical sequence of devices that
are wired as a linear network (chain). This is particularly
convenient for devices that are installed at equal spacing
along a long cable (e.g., to measure temperatures at dif-
ferent locations inside a storage tower or tank). Without
chain function, the master needs a lookup table to corre-
late the registration number to the physical location.
The chain function requires two pins: an input (EN) to
enable a device to respond during the discovery and an
output (DONE) to inform the next device in the chain that
the discovery of its neighbor is done. The two general-
purpose ports of the DS28EA00 are reused for the chain
function. PIOB functions as an EN input and PIOA gener-
ates the DONE signal, which is connected to the EN input
of the next device, as shown in the Typical Operating
Circuit. The EN input of the first device in the chain needs
to be hardwired to GND or logic 0 must be applied for the
duration of the sequence discovery process. Besides the
two pins, the sequence discovery relies on the Conditional
Read ROM command.
For the chain function and normal PIO operation to coex-
ist, the DS28EA00 distinguishes three chain states: OFF,
ON, and DONE. The transition from one chain state to
another is controlled through the Chain command. Table 2
summarizes the chain states and the specific behavior of
the PIO pins.
The functional assignments of the individual bits are
explained in the table below. Bits [4:0] and bit 7 have no
function and cannot be changed by the user. As a factory
default, the device operates in 12-bit resolution.
Table 2. Chain States
Figure 5. PIO Simplified Logic Diagram
ADDRRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
4h 0 R1 R0 1 1 1 1 1
BIT DESCRIPTION BIT(S) DEFINITION
R1, R0: Temperature
Converter Resolution [6:5]
These bits control the resolution of the temperature converter. The codes are as follows:
R1 R0
0 0 9 bits
0 1 10 bits
1 0 11 bits
1 1 12 bits
CHAIN STATE DEVICE BEHAVIOR
PIOB (EN) PIOA (DONE) CONDITIONAL READ ROM
OFF (Default) PIO (High Impedance) PIO (High Impedance) Not Recognized
ON EN Input Pullup On Recognized if EN is 0
DONE No Function Pulldown On (DONE Logic 0) Not Recognized
D Q
Q
PIO OUTPUT LATCH
CLOCK
PIO PINPIO PIN STATE
PIO OUTPUT LATCH STATE
PIO DATA
PIO CLOCK
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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9
Configuration Register
The power-on default chain state is OFF, where PIOA
and PIOB are solely controlled through the PIO Access
Read and Write commands. In the chain ON state, PIOA
is pulled high to the device’s internal VDD supply through
an approximately 40kΩ resistor, applying a logic 1 to the
PIOB (EN) pin of the next device. Only in the ON state
does a DS28EA00 respond to the Conditional Read ROM
command, provided its EN is at logic 0. After a device’s
ROM registration number is read, it is put into the chain
DONE state, which enables the next device in the chain to
respond to the Conditional Read ROM command.
At the beginning of the sequence discovery process, all
devices are put into the chain ON state. As the discovery
progresses, one device after another is transitioned into
the DONE state until all devices are identified. Finally, all
devices are put into the chain OFF state, which releases
the PIO pins and restores their poweron default state.
Control Function Commands
Figure 9 shows the protocols necessary for measur-
ing temperatures, accessing the memory and PIO pins,
and changing the chain state. Examples on how to use
these and other functions are included at the end of this
document. The communication between master and
DS28EA00 takes place either at standard speed (default,
OD = 0) or at overdrive speed (OD = 1). If not explicitly set
into the overdrive mode after power-up, the DS28EA00
communicates at standard speed.
Write Scratchpad [4Eh]
This command allows the master to write 3 bytes of data
to the scratchpad of the DS28EA00. The first data byte is
associated with the TH register (byte address 2), the sec-
ond byte is associated with the TL register (byte address
3), and the third byte is associated with the Configuration
register (byte address 4). Data must be transmitted least
significant bit first. All 3 bytes must be written before the
master issues a reset, or the data can be corrupted.
Read Scratchpad [BEh]
This command allows the master to read the contents
of the scratchpad. The data transfer starts with the least
significant bit of the Temperature Readout register at byte
address 0 and continues through the remaining 7 bytes
of the scratchpad. If the master continues reading, it gets
a ninth byte, which is an 8-bit CRC of all the data in the
scratchpad. This CRC is generated by the DS28EA00 and
uses the same polynomial function as is used with the
ROM registration number. The CRC is transmitted in its
true (noninverted) form. The master can issue a reset to
terminate the reading early if only part of the scratchpad
data is needed.
Copy Scratchpad [48h]
This command copies the contents of the scratchpad byte
addresses 2 to 4 (TH, TL, and Configuration registers) to
the backup EEPROM. If the device has no VDD power,
the master must enable a strong pullup on the 1-Wire bus
for the duration of tPROGMAX within 10μs after this com-
mand is issued. If the device is powered through the VDD
pin, the master can generate read time slots to monitor
the copy process. Copy is completed when the master
reads 1 bits instead of 0 bits.
Convert Temperature [44h]
This command initiates a temperature conversion.
Following the conversion, the resulting thermal data is
found in the Temperature Readout register in the scratch-
pad and the DS28EA00 returns to its low-power idle state.
If the device has no VDD power, the master must enable
a strong pullup on the 1-Wire bus for the duration of the
applicable resolution-dependent tCONVMAX within 10μs
after this command is issued. If the device is powered
through the VDD pin, the master can generate read time
slots to monitor the conversion process. The conversion is
completed when the master reads 1 bits instead of 0 bits.
Read Power Mode [B4h]
For Copy Scratchpad and Convert Temperature, the
master needs to know whether the DS28EA00 has VDD
power available. The Read Power Mode command is
implemented to provide the master with this information.
After the command code, master issues read time slots.
If the master reads 1s, the device is powered through the
VDD pin. If the device is powered through the 1-Wire line,
the master read 0s. The power-supply sensor samples
the state of the VDD pin for every time slot that the master
generates after the command code.
Recall EEPROM [B8h]
This command recalls the TH and TL alarm trigger values
and configuration data from backup EEPROM into their
respective locations in the scratchpad. After having trans-
mitted the command code, the master can issue read
time slots to monitor the completion of the recall process.
Recall is completed when the master reads 1 bits instead
of 0 bits. The recall occurs automatically at power-up, not
requiring any activity by the master.
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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10
PIO Access Read [F5h]
This command reads the PIO logical status and reports
it together with the state of the PIO output latch in an
endless loop. A PIO Access Read can be terminated at
any time with a 1-Wire reset. PIO Access Read can be
executed in the Chain ON and Chain DONE state. While
the device is in the Chain ON or Chain DONE state, the
PIO output latch states always read out as 1s; the PIO pin
state may not be reported correctly.
The state of both PIO channels is sampled at the same
time. The first sampling occurs during the last (most sig-
nificant) bit of the command code F5h. The PIO status
is then reported to the bus master. While the master
receives the last (most significant) bit of the PIO status
byte, the next sampling occurs and so on until the master
generates a 1-Wire reset. The sampling occurs with a
delay of tREH + x from the rising edge of the MS bit of the
previous byte, as shown in Figure 6. The value of “x” is
approximately 0.2μs.
PIO Access Write [A5h]
The PIO Access Write command writes to the PIO output
latches, which control the pulldown transistors of the PIO
channels. In an endless loop, this command first writes
new data to the PIO and then reads back the PIO status.
This implicit read-after-write can be used by the master
for status verification. A PIO Access Write can be termi-
nated at any time with a 1-Wire reset. The PIO Access
Write command is ignored by the device while in Chain
ON or Chain DONE state.
After the command code, the master transmits a PIO
output data byte that determines the new state of the
PIO output transistors. The first (least significant) bit is
associated to PIOA; the next bit affects PIOB. The other
6 bits of the new state byte do not have corresponding
PIO pins. These bits should always be transmitted as 1s.
To switch the output transistor on, the corresponding bit
value is 0. To switch the output transistor off (non-con-
ducting), the bit must be 1. This way the bit transmitted
Figure 6. PIO Access Read Timing Diagram
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
COMPLEMENT OF B3 TO B0 PIOB OUTPUT
LATCH STATE
PIOB PIN
STATE
PIOA OUTPUT
LATCH STATE
PIOA PIN
STATE
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
X X X X X X PIOB PIOA
SAMPLING POINT**
tREH + X
VTH
IO
*THE "PREVIOUS BYTE" COULD BE THE COMMAND CODE OR THE DATA BYTE RESULTING FROM THE PREVIOUS PIO SAMPLE.
**THE SAMPLE POINT TIMING ALSO APPLIES TO THE PIO ACCESS WRITE COMMAND, WITH THE "PREVIOUS BYTE" BEING THE WRITE CONFIRMATION BYTE (AAh).
MOST SIGNIFICANT 2 BITS OF PREVIOUS BYTE* LEAST SIGNIFICANT 2 BITS OF PIO STATUS BYTE
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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11
PIO Status Bit Assignment
PIO Output Data Bit Assignment
CHA‘N UN cHAw DO SHAW u or/—> 777777777777
as the new PIO output state arrives in its true form at the
PIO pin. To protect the transmission against data errors,
the master must repeat the PIO output data byte in its
inverted form. Only if the transmission was error-free can
the PIO status change. The actual PIO transition to the
new state occurs with a delay of tREH + x from the rising
edge of the MS bit of the inverted PIO byte, as shown
in Figure 7. The value of “x” is approximately 0.2μs. To
inform the master about the successful communication
of the PIO byte, the DS28EA00 transmits a confirmation
byte with the data pattern AAh. While the MS bit of the
confirmation byte is transmitted, the DS28EA00 samples
the state of the PIO pins, as shown in Figure 6, and sends
it to the master. The master can either continue writing
more data to the PIO or issue a 1-Wire reset to end the
command.
Chain [99h]
This command allows the master to put the DS28EA00
into one of the three chain states, as shown in Figure 8.
The device powers up in the chain OFF state. To transi-
tion a DS28EA00 from one state to another, the master
must send a suitable chain control byte after the Chain
command code. Only the codes 3Ch, 5Ah, and 96h (true
form) are valid, assigned to OFF, ON, and DONE, in
this sequence. This control byte is first transmitted in its
true form and then in its inverted form. If the chain state
change was successful, the master receives AAh confir-
mation bytes. If the change was not successful (control
byte transmission error, invalid control byte), the master
reads 00h bytes instead.
Figure 7. PIO Access Write Timing Diagram
Figure 8. Chain State Transition Diagram
tREH + X
VTH
IO
PIO
MOST SIGNIFICANT 2 BITS OF INVERTED PIO OUTPUT DATA BYTE LEAST SIGNIFICANT 2 BITS OF CONFIRMATION BYTE (AAh)
THESE TRANSITIONS ARE PERMISSIBLE, BUT DO NOT
OCCUR DURING NORMAL OPERATION.
OFFPOWER-ON RESET (POR)
CHAIN DONE
CHAIN ON
CHAIN ON CHAIN DONE
CHAIN OFF
OR POR
DONEON
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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12
FRDM RuM EUNcTToMs FLOWCHART (ETGURE H oEn WRTTE SCRATCHPAD'Y MW POWERED" v y (:on Vi MASTERTXRESET" 7 MASTERTxREsET7 7 CDMPLETEW BYTE v BVTE v E: ADDREss:w ADDRESS:7" MASTER TX RESETw MASTER Tx RESET7 j: MASTER TX RESET”
Figure 9a. Control Function Flowchart
BUS MASTER Tx CONTROL
FUNCTION COMMAND
DS28EA00 SETS
BYTE ADDRESS = 2
4Eh
WRITE SCRATCHPAD? N
Y
Y
N
N
Y
N
MASTER Tx RESET?
BYTE
ADDRESS = 4?
MASTER Tx RESET?
MASTER Tx DATA
BYTE TO SCRATCHPAD
DS28EA00 INCREMENTS
BYTE ADDRESS
FROM ROM FUNCTIONS
FLOWCHART (FIGURE 11)
TO ROM FUNCTIONS
FLOWCHART (FIGURE 11)
Y
TO FIGURE 9b
FROM FIGURE 9b
DS28EA00 SETS
BYTE ADDRESS = 0
DS28EA00 STARTS
COPY TO EEPROM
BEh
READ SCRATCHPAD? N
Y
MASTER Rx BYTE
FROM SCRATCHPAD
MASTER ACTIVATES STRONG
PULLUP FOR tPROG
MASTER DEACTIVATES
STRONG PULLUP
DS28EA00 COPIES
SCRATCHPAD DATA
TO EEPROM
48h
COPY SCRATCHPAD?
MASTER DECISION.
THE MASTER NEEDS TO
KNOW WHETHER VDD
POWER IS AVAILABLE.
N
Y
Y
NY VDD POWERED?
COPY
COMPLETED?
MASTER Rx "0"s
MASTER Rx "1"s
Y
N
N
MASTER Tx RESET?
BYTE
ADDRESS = 7?
DS28EA00 INCREMENTS
BYTE ADDRESS
MASTER Rx 8-BIT
CRC OF DATA
N
Y
N
MASTER Tx RESET? Y
MASTER Rx "1"s
N
MASTER Tx RESET? Y
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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13
Vuu POWERED" VDu PDWERED" |::| soNvERsToN v COMPLETEDw j: MASTER TX RESET” E MASTER Tx RESET7
Figure 9b. Control Function Flowchart
TO FIGURE 9c
FROM FIGURE 9c
FROM FIGURE 9a
TO FIGURE 9a
DS28EA00 STARTS
TEMPERATURE CONVERSION
MASTER ACTIVATES STRONG
PULLUP FOR tCONV
MASTER DEACTIVATES
STRONG PULLUP
DS28EA00 CONVERTS
TEMPERATURE
44h
CONVERT
TEMPERATURE
N
Y
Y
B4h
READ POWER
MODE?
N
Y
N
NY NY
VDD POWERED? VDD POWERED?
CONVERSION
COMPLETED?
MASTER Rx "0"s
MASTER Rx "1"s MASTER Rx "0"s
MASTER Rx "1"s
N
MASTER Tx RESET? Y
N
MASTER Tx RESET? Y
MASTER DECISION.
THE MASTER NEEDS TO
KNOW WHETHER VDD
POWER IS AVAILABLE.
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
www.maximintegrated.com Maxim Integrated
14
an MASTER TX RESET” j: MASTER Tx RESET7 MASTER TX RESET”
Figure 9c. Control Function Flowchart
TO FIGURE 9d
FROM FIGURE 9d
FROM FIGURE 9b
TO FIGURE 9b
DS28EA00 STARTS RECALL
EEPROM TO SCRATCHPAD
DS28EA00 SAMPLES
PIO PIN
*
*SEE THE COMMAND DESCRIPTION FOR THE EXACT TIMING OF THE PIO PIN SAMPLING AND UPDATING.
DS28EA00 UPDATES
PIO
*
*
BUS MASTER Tx NEW PIO
OUTPUT DATA BYTE
BUS MASTER Tx INVERTED NEW
PIO OUTPUT DATA BYTE
BUS MASTER Rx
PIO PIN STATUS
B8h
RECALL EEPROM? N
Y
F5h
PIO ACCESS
READ?
A5h
PIO ACCESS
WRITE?
NN
Y
RECALL
COMPLETED?
Y
N
N
MASTER Rx "0"s
MASTER Rx "1"s
MASTER Rx "1"s
N
MASTER Tx RESET? Y N
N
Y
MASTER Tx RESET? NMASTER Tx RESET?
Y
TRANSMISSION
OK?
MASTER Tx RESET?
BUS MASTER Rx
CONFIRMATION AAh
BUS MASTER Rx "1"s
BUS MASTER Rx
PIO PIN STATUS
DS28EA00 SAMPLES
PIO PIN
Y
Y
Y
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
www.maximintegrated.com Maxim Integrated
15
Figure 9d. Control Function Flowchart
FROM FIGURE 9c
TO FIGURE 9c
99h
CHAIN COMMAND? N
Y
MASTER Rx "1"s
N
MASTER Tx RESET? Y
N
MASTER Tx CHAIN
CONTROL BYTE
DS28EA00 UPDATES
CHAIN STATE
MASTER Rx CONFIRMATION
CODE AAh
MASTER Tx INVERTED
CHAIN CONTROL BYTE
TRANSMISSION
ERROR?
CONTROL BYTE
VALID?
Y
N
N
Y
MASTER Tx RESET?
Y
N
MASTER Rx INVERTED CHAIN
CONTROL BYTE
MASTER Tx RESET?
Y
N
MASTER Rx ERROR
CODE 00h
MASTER Tx RESET?
Y
ERROR DEFINED AS:
REPEATED CONTROL BYTE
NOT EQUAL TO INVERTED
CONTROL BYTE
VALID CHAIN CONTROL
BYTE CODES:
3Ch OFF
5Ah ON
96h DONE
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
www.maximintegrated.com Maxim Integrated
16
if:
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances the DS28EA00
is a slave device. The bus master is typically a micro-con-
troller. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing).
The 1-Wire protocol defines bus transactions in terms of
the bus state during specific time slots, which are initiated
on the falling edge of sync pulses from the bus master.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or three-
state outputs. The 1-Wire port of the DS28EA00 is open
drain with an internal circuit equivalent to that shown in
Figure 10.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28EA00 supports both a stan-
dard and overdrive communication speed of 15.3kbps
(max) and 125kbps (max), respectively. Note that lega-
cy 1-Wire products support a standard communication
speed of 16.3kbps and overdrive of 142kbps. The slightly
reduced rates for the DS28EA00 are a result of additional
recovery times, which in turn are driven by a 1-Wire physi-
cal interface enhancement to improve noise immunity.
The value of the pullup resistor primarily depends on
the network size and load conditions. The DS28EA00
requires a pullup resistor of 2.2kΩ (max) at any speed.
The idle state for the 1-Wire bus is high. If for any reason
a transaction needs to be suspended, the bus must be
left in the idle state if the transaction is to resume. If this
does not occur and the bus is left low for more than 16μs
(overdrive speed) or more than 120μs (standard speed),
one or more devices on the bus could be reset.
Transaction Sequence
The protocol for accessing the DS28EA00 through the
1-Wire port is as follows:
Initialization
ROM Function Command
Control Function Command
Transaction/Data
Initialization
All transactions on the 1-Wire bus begin with an initializa-
tion sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by
presence pulse(s) transmitted by the slave(s). The pres-
ence pulse lets the bus master know that the DS28EA00
is on the bus and is ready to operate. For more details,
see the 1-Wire Signaling section.
Figure 10. Hardware Configuration
Rx
RPUP
IL
VPUP
BUS MASTER
OPEN-DRAIN
PORT PIN 100 MOSFET
Tx
Rx
Tx
DATA
DS28EA00 1-Wire PORT
Rx = RECEIVE
Tx = TRANSMIT
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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17
1-Wire ROM Function Commands
Once the bus master has detected a presence, it can
issue one of the eight ROM function commands that the
DS28EA00 supports. All ROM function commands are 8
bits long. A list of these commands follows (refer to the
flowchart in Figure 11).
Read ROM [33h]
This command allows the bus master to read the
DS28EA00’s 8-bit family code, unique 48-bit serial num-
ber, and 8-bit CRC. This command can only be used if
there is a single slave on the bus. If more than one slave
is present on the bus, a data collision occurs when all
slaves try to transmit at the same time (open drain pro-
duces a wired-AND result). The resultant family code and
48-bit serial number result in a mismatch of the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS28EA00 on a multidrop bus. Only the DS28EA00 that
exactly matches the 64-bit ROM sequence responds to
the following Control Function command. All other slaves
wait for a reset pulse. This command can be used with a
single device or multiple devices on the bus.
Search ROM [F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire
bus or their registration numbers. By taking advantage
of the wired-AND property of the bus, the master can
use a process of elimination to identify the registration
numbers of all slave devices. For each bit of the registra-
tion number, starting with the least significant bit, the bus
master issues a triplet of time slots. On the first slot, each
slave device participating in the search outputs the true
value of its registration number bit. On the second slot,
each slave device participating in the search outputs the
complemented value of its registration number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choosing
which state to write, the bus master branches in the ROM
code tree. After one complete pass, the bus master knows
the registration number of a single device. Additional
passes identify the registration numbers of the remaining
devices. Refer to Application Note 187: 1-Wire Search
Algorithm for a detailed discussion, including an example.
The Search ROM command does not reveal any informa-
tion about the location of a device in a network. If multiple
DS28EA00 are wired as a linear network (“chain”), the
device location can be detected using Conditional Read
ROM in conjunction with the Chain function.
Conditional Search ROM [ECh]
The Conditional Search ROM command operates simi-
larly to the Search ROM command except that only those
devices which fulfill certain conditions, participate in the
search. This function provides an efficient means for the
bus master to identify devices on a multidrop system that
have to signal an important event. After each pass of the
conditional search that successfully determined the 64-bit
ROM code for a specific device on the multidrop bus,
that particular device can be individually accessed as if a
Match ROM had been issued, since all other devices have
dropped out of the search process and are waiting for a
reset pulse. The DS28EA00 responds to the Conditional
Search ROM command if a temperature alarm condi-
tion exists. For more details see the Temperature Alarm
Registers Bitmap section.
Conditional Read ROM [0Fh]
This command is used in conjunction with the Chain
function to detect the physical sequence of devices
in a linear network (chain). A DS28EA00 responds to
Conditional Read ROM if two conditions are met: a) the
device is in chain ON state, and b) the EN input (PIOB)
is at logic 0. This condition is met by exactly one device
during the sequence discovery process. Upon receiv-
ing the Conditional Read ROM command, this particular
device transmits its 64-bit registration number. A device
in chain ON state, but with a logic 1 level at EN does not
respond to Conditional Read ROM. See the Sequence
Discovery Procedure section for more details on the use
of Conditional Read ROM and the Chain commands.
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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18
Skip ROM [CCh]
This command can save time in a single-drop bus system
by allowing the bus master to access the control functions
without providing the 64-bit ROM code. If more than one
slave is present on the bus and, for example, a read com-
mand is issued following the Skip ROM command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wired-
AND result).
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the control functions
without providing the 64-bit ROM code. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM sets the
DS28EA00 in the overdrive mode (OD = 1). All communi-
cation following this command has to occur at overdrive
speed until a reset pulse of minimum 480μs duration
resets all devices on the bus to standard speed (OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed has to be issued
followed by a Match ROM or Search ROM command
sequence. This speeds up the time for the search pro-
cess. If more than one slave supporting overdrive is pres-
ent on the bus and the Overdrive-Skip ROM command is
followed by a Read command, data collision occurs on
the bus as multiple slaves transmit simultaneously (open-
drain pulldowns produce a wired-AND result).
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64-bit
ROM sequence transmitted at overdrive speed allows the
bus master to address a specific DS28EA00 on a multi-
drop bus and to simultaneously set it in over-drive mode.
Only the DS28EA00 that exactly matches the 64-bit ROM
sequence responds to the subsequent control function
command. Slaves already in overdrive mode from a previ-
ous Overdrive-Skip ROM or successful Overdrive-Match
ROM command remain in overdrive mode. All over-drive-
capable slaves return to standard speed at the next reset
pulse of minimum 480μs duration. The Overdrive-Match
ROM command can be used with a single device or mul-
tiple devices on the bus.
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
www.maximintegrated.com Maxim Integrated
19
ROM conoL FUNCHON wch meuRE 9‘ on my msy 4» 33h 5» ran 7:% EC» ma ROM wen ROM semen ROM mm mm mm commum mwmm common v v v aw n Mmm aw n Mum ma wcm aw ‘ Mmm v v v was Mmm 4» W as wcm aw 31 wow m coMRm mucnons no Hm mews 9‘
Figure 11a. ROM Functions Flowchart
DS28EA00 Tx
PRESENCE PULSE
BUS MASTER Tx
RESET PULSE
BUS MASTER Tx ROM
FUNCTION COMMAND
DS28EA00 Tx
CRC BYTE
DS28EA00 Tx
FAMILY CODE
(1 BYTE)
DS28EA00 Tx
SERIAL NUMBER
(6 BYTES)
OD = 0
MASTER Tx BIT 0
Y
OD
RESET PULSE?
YY
Y
Y
Y
Y
N
33h
READ ROM
COMMAND?
N
55h
MATCH ROM
COMMAND?
BIT 0 MATCH? BIT 0 MATCH?
N
N N
N N
N N
F0h
SEARCH ROM
COMMAND?
N
ECh
CONDITIONAL SEARCH
COMMAND?
N
Y
MASTER Tx BIT 1
MASTER Tx BIT 63
BIT 1 MATCH?
BIT 63 MATCH?
Y
Y
FROM CONTROL FUNCTIONS
FLOWCHART (FIGURE 9)
TO CONTROL FUNCTIONS
FLOWCHART (FIGURE 9)
DS28EA00 Tx BIT 0
DS28EA00 Tx BIT 0
MASTER Tx BIT 0
BIT 1 MATCH?
BIT 63 MATCH?
DS28EA00 Tx BIT 1
DS28EA00 Tx BIT 1
MASTER Tx BIT 1
DS28EA00 Tx BIT 63
DS28EA00 Tx BIT 63
MASTER Tx BIT 63
Y
BIT 0 MATCH?
N
N
N
Y
Y
DS28EA00 Tx BIT 0
DS28EA00 Tx BIT 0
MASTER Tx BIT 0
TEMPERATURE
ALARM?
N
Y
BIT 1 MATCH?
BIT 63 MATCH?
DS28EA00 Tx BIT 1
DS28EA00 Tx BIT 1
MASTER Tx BIT 1
DS28EA00 Tx BIT 63
DS28EA00 Tx BIT 63
MASTER Tx BIT 63
Y
FROM FIGURE 11b
TO FIGURE 11b
TO FIGURE 11b
FROM FIGURE 11b
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
www.maximintegrated.com Maxim Integrated
20
m cc» 3cm an CoNDmoNAL N 5ka ROM DvERDmvE ovERDRwE READ new mwmm smp new MAYCH now own : ow |::| N mm n RESEW BWHMAYCM |::| mm *4. am wow D mm
Figure 11b. ROM Functions Flowchart
MASTER Tx BIT 0
OD = 1 OD = 1
OD = 0
*
*THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED.
*
*
CHAIN = ON?
Y
N
Y
CCh
SKIP ROM
COMMAND?
N
Y
3Ch
OVERDRIVE-
SKIP ROM?
N
Y
EN = LOW?
Y
Y
0Fh
CONDITIONAL
READ ROM?
Y
69h
OVERDRIVE-
MATCH ROM?
N
N
N
N
OD = 0
N
OD = 0
N
MASTER Tx BIT 1
MASTER Tx BIT 63
Y
Y
Y
BIT 0 MATCH?
MASTER Tx
RESET?
BIT 63 MATCH?
BIT 1 MATCH?
N
Y
MASTER Tx
RESET?
N
TO FIGURE 11a
FROM FIGURE 11a
FROM FIGURE 11a
TO FIGURE 11a
DS28EA00 Tx
FAMILY CODE
(1 BYTE)
DS28EA00 Tx
SERIAL NUMBER
(6 BYTES)
DS28EA00 Tx
CRC BYTE
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
www.maximintegrated.com Maxim Integrated
21
1-Wire Signaling
The DS28EA00 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and presence
pulse, write-zero, write-one, and read-data. Except for the
presence pulse, the bus master initiates all falling edges.
The DS28EA00 can communicate at two different speeds,
standard speed and overdrive speed. If not explicitly set
into the overdrive mode, the DS28EA00 communicates at
standard speed. While in overdrive mode the fast timing
applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from VPUP below the threshold VTL. To get
from active to idle, the voltage needs to rise from VILMAX
past the threshold VTH. The time it takes for the voltage
to make this rise is seen in Figure 12 as “ε” and its dura-
tion depends on the pullup resistor (RPUP) used and the
capacitance of the 1-Wire network attached. The voltage
VILMAX is relevant for the DS28EA00 when determining
a logical level, not triggering any events.
Figure 12 shows the initialization sequence required
to begin any communication with the DS28EA00. A
reset pulse followed by a presence pulse indicates the
DS28EA00 is ready to receive data, given the correct
ROM and control function command. If the bus master
uses slew-rate control on the falling edge, it must pull
down the line for tRSTL + tF to compensate for the edge.
A tRSTL duration of 480μs or longer exits the overdrive
mode, returning the device to standard speed. If the
DS28EA00 is in overdrive mode and tRSTL is no longer
than 80μs, the device remains in overdrive mode. If the
device is in overdrive mode and tRSTL is between 80μs
and 480μs, the device resets, but the communication
speed is undetermined.
After the bus master has released the line, it goes into
receive mode. Now the 1-Wire bus is pulled to VPUP
through the pullup resistor, or in the case of a DS2482-x00
or DS2480B driver, by active circuitry. When the threshold
VTH is crossed, the DS28EA00 waits for tPDH and then
transmits a presence pulse by pulling the line low for tPDL.
To detect a presence pulse, the master must test the logi-
cal state of the 1-Wire line at tMSP.
The tRSTH window must be at least the sum of tPDH-
MAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is
expired, the DS28EA00 is ready for data communication.
In a mixed population network, tRSTH should be extended
to minimum 480μs at standard speed and 48μs at over-
drive speed to accommodate other 1-Wire devices.
Read/Write Time Slots
Data communication with the DS28EA00 takes place in
time slots, which carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 13 illustrates
the definitions of the write and read time slots.
All communication begins with the master pulling the data
line low. As the voltage on the 1-Wire line falls below the
threshold VTL, the DS28EA00 starts its internal timing
generator that determines when the data line is sampled
during a write time slot and how long data is valid during
a read time slot.
Figure 12. Initialization Procedure “Reset and Presence Pulses”
RESISTOR MASTER DS28EA00
tRSTL tPDL
tRSTH
tPDH
MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE"
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tREC
tMSP
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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22
Figure 13. Read/Write Timing Diagram
RESISTOR MASTER
RESISTOR MASTER
RESISTOR MASTER DS28EA00
ε
ε
δ
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tF
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tF
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tF
tSLOT
tW1L
tREC
tSLOT
tSLOT
tW0L
tREC
MASTER
SAMPLING
WINDOW
tRL
tMSR
WRITE-ONE TIME SLOT
WRITE-ZERO TIME SLOT
READ-DATA TIME SLOT
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the VTH threshold before the writeone
low time tW1LMAX is expired. For a write-zero time slot,
the voltage on the data line must stay below the VTH
threshold until the write-zero low time tW0LMIN is expired.
For the most reliable communication, the voltage on the
data line should not exceed VILMAX during the entire
tW0L or tW1L window. After the VTH threshold has been
crossed, the DS28EA00 needs a recovery time tREC
before it is ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below VTL until
the read low time tRL is expired. During the tRL window,
when responding with a 0, the DS28EA00 starts pulling
the data line low; its internal timing generator determines
when this pulldown ends and the voltage starts rising
again. When responding with a 1, the DS28EA00 does
not hold the data line low at all, and the voltage starts ris-
ing as soon as tRL is over.
The sum of tRL + δ (rise time) on one side and the inter-
nal timing generator of the DS28EA00 on the other side
define the master sampling window (tMSRMIN to tMSR-
MAX) in which the master must perform a read from the
data line. For the most reliable communication, tRL should
be as short as permissible, and the master should read
close to but no later than tMSRMAX. After reading from
the data line, the master must wait until tSLOT is expired.
This guarantees sufficient recovery time tREC for the
DS28EA00 to get ready for the next time slot. Note that
tREC specified herein applies only to a single DS28EA00
attached to a 1-Wire line. For multidevice configurations,
tREC needs to be extended to accommodate the addi-
tional 1-Wire device input capacitance. Alternatively, an
interface that performs active pullup during the 1-Wire
recovery time such as the DS2482-x00 or DS2480B
1-Wire line drivers can be used.
Improved Network Behavior
(Switchpoint Hysteresis)
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to
noise of various origins. Depending on the physical size
and topology of the network, reflections from end points
and branch points can add up, or cancel each other to
some extent. Such reflections are visible as glitches or
ringing on the 1-Wire communication line. Noise coupled
onto the 1-Wire line from external sources can also result
in signal glitching. A glitch during the rising edge of a time
slot can cause a slave device to lose synchronization with
the master and, consequently, result in a Search ROM
command coming to a dead end or cause a device-spe-
cific function command to abort. For better performance in
network applications, the DS28EA00 uses a new 1-Wire
front-end, which makes it less sensitive to noise and also
reduces the magnitude of noise injected by the slave
device itself.
The 1-Wire front-end of the DS28EA00 differs from tradi-
tional slave devices in four characteristics:
1) The falling edge of the presence pulse has a con-
trolled slew rate. This provides a better match to the
line impedance than a digitally switched transistor,
converting the high-frequency ringing known from
traditional devices into a smoother low-bandwidth
transition. The slew-rate control is specified by the
parameter tFPD, which has different values for stan-
dard and overdrive speed.
2) There is additional lowpass filtering in the circuit that
detects the falling edge at the beginning of a time
slot. This reduces the sensitivity to high-frequency
noise. This additional filtering does not apply at over-
drive speed.
3) There is a hysteresis at the low-to-high switching
threshold VTH. If a negative glitch crosses VTH but
does not go below VTH - VHY, it is not recognized
(Figure 14, Case A). The hysteresis is effective at
any 1-Wire speed.
4) There is a time window specified by the rising edge
hold-off time tREH during which glitches are ignored,
even if they extend below VTH - VHY threshold
(Figure 14, Case B, tGL < tREH). Deep voltage
droops or glitches that appear late after crossing the
VTH threshold and extend beyond the tREH window
cannot be filtered out and are taken as the beginning
of a new time slot (Figure 14, Case C, tGL ≥ tREH).
Devices that have the parameters VHY and tREH speci-
fied in their electrical characteristics use the improved
1-Wire front-end.
Sequence Discovery Procedure
Precondition: The PIOB pin (EN) of the first device in
the chain is at logic 0. The PIOA pin (DONE) of the first
device connects to the PIOB of the second device in the
chain, etc., as shown in Figure 15. The 1-Wire master
detects the physical sequence of the devices in the chain
by performing the following procedure.
Starting Condition: The master issues a Skip ROM
command followed by a Chain ON command, which
puts all devices in the chain ON state. The pullup
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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24
’ ? + ‘f I ~~~~~ / ~V~ ~~~~~~~~~~~~~~~~~~~~ [K ~~~~~~~~~~~~~~~~~~~~~~~~ [\C ~~~~~~~~~~~~~~~~~~~~~~~~
through RCO of the PIOA pin charges the PIOA/PIOB con-
nections to logic 1 level at all devices except for the first
device in the chain. If a local VDD supply is not available,
the master needs to activate a low-impedance bypass to
the 1-Wire pullup resistor immediately after the inverted
chain control byte until the PIOA/PIOB connections have
reached a voltage equivalent to the logic 1 level.
First Cycle: The master sends a Conditional Read ROM
command, which causes the first device in the chain to
respond with its 64-bit registration number. The master
memorizes the registration number and the fact that this is
the first device in the chain. Next, the master transmits a
Chain DONE command. Through the PIOA pin of the just
discovered device, this asserts logic 0 at the PIOB pin of
the second device in the chain and also prevents the just
discovered device from responding again.
Second Cycle: The master sends a Conditional Read
ROM command. Since the second DS28EA00 is the only
device in the chain with a low level at PIOB, it responds
with its registration number. The master stores the regis-
tration number with the sequence number of 2. The first
device cannot respond since it is in chain DONE state.
Next, the master transmits a Chain DONE command.
Additional Cycles: To identify the registration numbers
of the remaining devices and their physical sequence, the
master repeats the steps of Conditional Read ROM and
Chain DONE. If there is no response to Conditional Read
ROM, all devices in the chain are identified.
Ending Condition: At the end of the discovery process
all devices in the chain are in the chain DONE state. The
master should end the sequence discovery by issuing a
Skip ROM command followed by a Chain OFF command.
This puts all the devices into the chain OFF state and
transfers control of the PIOB and PIOA pins to the PIO
Access Read and Write function commands.
Figure 14. Noise Suppression Scheme
Figure 15. DS28EA00 Wired for Sequence Discovery (“Chain Function”)
VPUP
VTH VHY
0V
tREH
tGL
tREH
tGL
CASE A CASE CCASE B
DS28EA00
IO
PIOB PIOA
GND
VDD
VDD
*CAPACITANCE OF THE CABLING BETWEEN ADJACENT DEVICES IN THE CHAIN.
* *
1-Wire
MASTER
#1
DS28EA00
IO
PIOB
PX. Y
MICROCONTROLLER
PIOA
GND
VDD
#2
DS28EA00
IO
PIOB PIOA
GND
VDD
#3
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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25
SYMBOL DESCRIPTION
RST 1-Wire reset pulse generated by master
PD 1-Wire presence pulse generated by slave
SELECT Command and data to satisfy the ROM function protocol
SKIPR ROM function command: “Skip ROM”
CDRR ROM function command: “Conditional Read ROM”
MR ROM function command: “Match ROM”
WSP Command: “Write Scratchpad”
RSP Command: “Read Scratchpad”
CPSP Command: “Copy Scratchpad”
CTEMP Command: “Convert Temperature”
RPM Command: “Read Power Mode”
RCLE Command: “Recall EEPROM”
PIOR Command: “PIO Access Read”
PIOW Command: “PIO Access Write”
CHAIN Command : “Chain”
<n bytes> Transfer of n bytes
CRC Transfer of a CRC byte
<xxh> Transfer of a specific byte value “xx” (hexadecimal notation)
00 loop Indefinite loop where the master reads 00 bytes
FF loop Indefinite loop where the master reads FF bytes
AA loop Indefinite loop where the master reads AA bytes
xx loop Indefinite loop where the slave transmits the inverted invalid control byte
CONVERSION A temperature conversion takes place; activity on the 1-Wire bus is permitted only with local VDD supply
PROGRAMMING Data transfer to backup EEPROM; activity on the 1-Wire bus is permitted only with local VDD supply
Master-to-Slave Slave-to-Master Programming Conversion
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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Command-Specific 1-Wire Communication Protocol—Legend
Command-Specific 1-Wire Communication Protocol—Color Codes
RST WSP
Write Scratchpad
PD RST PDSELECT <3 Bytes>
<8 Bytes> FF LoopRST RSP
RPM
CRC
Read Scratchpad
PD SELECT
RST
Convert Temperature (Parasite Powered)
PD SELECT
FF Loop
RST
Convert Temperature (Local VDD Powered)
PD SELECT
FF Loop During the wait, the master should activate a low-impedance
bypass to the 1-Wire pullup resistor.
During the wait, the master should activate a low-impedance
bypass to the 1-Wire pullup resistor.
See the command description for behavior if the device is in chain
ON or chain DONE state.
RST
Copy Scratchpad (Parasite Powered)
PD CPSSELECT
Wait tPROGMAX
FF Loop
Wait tCONVMAX
FF Loop
The master reads 00h bytes until the write cycle is completed.
RST
Copy Scratchpad (Local VDD Powered)
PD CPS <00h>
<00h>
<00h>
RPM <FFh>
<AAh>
SELECT
RST
PIO Access Write (Success)
PD SELECT
The master reads 00h bytes until the conversion is completed.
CTEMP
CTEMP
FF Loop
RST
Recall EEPROM
PD SELECT <00h>
The master reads 00h bytes until the recall is completed.
Continues until master sends reset pulse.
Loop until master sends reset pulse.
RCLE
PIOW <PIO Output Data> <PIO Status Byte>
<PIO Status Byte>PIOR
RST
Read Power Mode (Parasite Powered)
PD SELECT
RST
PIO Access Read
PD SELECT
RST
Read Power Mode (Local VDD Powered)
PD SELECT
<PIO Output Data>
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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1-Wire Communication Examples
PACKAGE TYPE PACKAGE CODE OUTLINE NO.
8 µSOP U8+1 21-0036
RST
PIO Access Write (Invalid Data Byte)
PD SELECT FF Loop
AA Loop
00 Loop
xx Loop
RST
Change Chain State (Success)
PD SELECT CHAIN
CHAIN
CHAIN
CHAIN
CHAIN
RST
Change Chain State (Transmission Error)
PD SELECT
The PIO Access Write command is ignored by the device while in chain ON or chain DONE state.
RST
Change Chain State (Invalid Control Byte)
PD SELECT
RST PD
<5Ah> <A5h>
<96h> <69h>
<AAh>
<Registration Number>
Wait for chain to charge Put all devices into
chain ON state.
No response: all devices have
been discovered
Put all devices into chain OFF state.
For the sequence discovery to function properly, the logic state at PIOB (EN) must not change during the transmission of
the Conditional Read ROM command code, and, if the device responds, must stay at logic 0 until the entire 64-bit registration
number is transmitted.
<AAh>
Chain <3Ch> <C3h> <AAh>
Identify the first device and
put it into chain DONE state.
Identify the next device and
put it into chain DONE state.
Repeat this sequence until
no device responds.
SKIPR
CDRR
CHAIN <96h> <69h><Registration Number> <AAh>CDRR
RST
Sequence Discovery Example
PD
RST PD
RST PD
<Registration Number>
<Registration Number>
RST PD
MR
MR
RST PD
<8 Bytes FFh>CDRR
SKIPR
RST PD
PIOW <PIO Output Data> <Invalid Data Byte>
<Chain Control Byte>
<Invalid Control Byte> <Inverted Previous Byte>
<Any Byte> <Byte Inverted Previous Byte>
<Chain Control Byte>
µSOP
2 7 PIOBN.C.
1 8 VDD
IO
PIOAN.C. 3 6
N.C.GND 4 5
DS28EA00
+
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
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28
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Pin Configuration
1-Wire Communication Examples (continued)
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/07 Initial release
1 6/07 Changed the storage temperature range in the Absolute Maximum Ratings
section from -40°C to +85°C to -55°C to +125°C 2
1.1 Created newer template-style data sheet 1—29
2 6/19 Updated the Command-Specific 1-Wire Communication Protocol—Legend and
1-Wire Communication Examples sections 26, 28
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
DS28EA00 1-Wire Digital Thermometer with
Sequence Detect and PIO
© 2019 Maxim Integrated Products, Inc.
29
Revision History
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