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eGaN® FET DATASHEET EPC2029
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EPC2029 – Enhancement Mode Power Transistor
VDS , 80 V
RDS(on) , 3.2 mΩ
ID , 48 A
EPC2029 eGaN® FETs are supplied only in
passivated die form with solder bumps.
Die Size: 4.6 mm x 2.6 mm
High Speed DC-DC Conversion
Motor Drive
Industrial Automation
Synchronous Rectification
Class-D Audio
EFFICIENT POWER CONVERSION
G
D
SHAL
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous) 80 V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 96
ID
Continuous (TA = 25°C, RθJA = 9°C/W) 48 A
Pulsed (25°C, TPULSE = 300 µs) 360
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature -40 to 150 °C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC Thermal Resistance, Junction-to-Case 0.45
°C/W RθJB Thermal Resistance, Junction-to-Board 3.9
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 45
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
All measurements were done with substrate connected to source.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.9 mA 80 V
IDSS Drain-Source Leakage VGS = 0 V, VDS = 64 V 0.1 0.6 mA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 1 9 mA
Gate-to-Source Reverse Leakage VGS = -4 V 0.1 0.6 mA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 12 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 30 A 2.5 3.2 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.6 V
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
eGaN® FET DATASHEET EPC2029
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350
300
250
200
150
100
50
00 0.5 1.0 1.5 2.0 2.5 3.0
ID – Drain Current (A)
Figure 1: Typical Output Characteristics at 25°C
VDS – Drain-to-Source Voltage (V)
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
10
8
6
4
2
02.52.0 3.0 3.5 4.0 4.5 5.0
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
I
D
= 15 A
I
D
= 30 A
I
D
= 60 A
I
D
= 120 A
Figure 3: R
DS(on)
vs. V
GS
for Various Drain Currents
ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
350
300
250
200
150
100
50
0
25˚C
125˚C
VDS = 3 V
25˚C
125˚C
VDS = 3 V
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
25˚C
125˚C
VDS = 3 V
25˚C
125˚C
ID = 30 A
10
8
6
4
2
0
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS
Input Capacitance
VDS = 40 V, VGS = 0 V
1410 1690
pF
CRSS
Reverse Transfer Capacitance
17
COSS
Output Capacitance
820 1230
COSS(ER)
Effective Output Capacitance, Energy Related (Note 2)
VDS = 0 to 40 V, VGS = 0 V 1090
COSS(TR)
Effective Output Capacitance, Time Related (Note 3)
1310
RG
Gate Resistance
0.4 Ω
QG
Total Gate Charge
VDS = 40 V, VGS = 5 V, ID = 30 A 13 16
nC
QGS
Gate-to-Source Charge
VDS = 40 V, ID = 30 A
3.4
QGD
Gate-to-Drain Charge
1.9
QG(TH)
Gate Charge at Threshold
2.5
QOSS
Output Charge
VDS = 40 V, VGS = 0 V 53 80
QRR
Source-Drain Recovery Charge
0
All measurements were done with substrate connected to source.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
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All measurements were done with substrate shortened to source.
Capacitance (pF)
1000
100
10
0 20 40 60 80
Figure 5b: Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ISD Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
Figure 7: Reverse Drain-Source Characteristics
350
300
250
200
150
100
50
0
25˚C
125˚C
Figure 9: Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 11 mAID = 12 mA
Capacitance (pF)
0 20 40 60 80
Figure 5a: Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
2500
2000
1500
1000
500
0
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Figure 6: Gate Charge
VGS Gate-to-Source Voltage (V)
5
4
3
2
1
00 15 10 5
QG – Gate Charge (nC)
ID = 30 A
VDS = 40 V
Figure 8: Normalized On-State Resistance vs. Temperature
ID = 30 A
VGS = 5 V
Normalized On-State Resistance RDS(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.8 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 30 A
VGS = 5 V
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Figure 12: Transient Thermal Response Curves
0.1
1
10
100
1000
0.1 1 10 100
ID Drain Current (A)
VDS - Drain-Source Voltage (V)
Limited by RDS(on)
Pulse Width
100 ms
10 ms
1 ms
100 µs
Figure 11: Safe Operating Area
IG Gate Current (mA)
VGS – Gate-to-Source Voltage (V)
Figure 10: Gate Leakage Current
25˚C
125˚C
50
40
30
20
10
00 1 2 3 4 5 6
tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
0.5
0.05
0.02
Single Pulse
0.01
0.1
Duty Cycle:
Junction-to-Board
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 10+1
1
0.1
0.01
0.001
0.0001
tp, Rectangular Pulse Duration, seconds
ZθJC, Normalized Thermal Impedance
0.5
0.1
0.02
0.05
Single Pulse
0.01
0.2
Duty Cycle:
Junction-to-Case
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
10-6 10-5 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.0001
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eGaN® FET DATASHEET EPC2029
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DIE MARKINGS
Pads 1 and 2 are Gate;
Pads 5, 6, 7, 8, 9, 15, 16, 17, 18, 19 are Drain;
Pads 3, 4, 10, 11, 13, 14, 20, 21, 22, 23, 24 are
Source;
Pad 12 is Substrate*
*Substrate pin should be connected to Source
DIE OUTLINE
Solder Bump View
Side View
DIM Micrometers
MIN Nominal MAX
A4570 4600 4630
B2570 2600 2630
c1000 1000 1000
d500 500 500
e285 300 315
f332 369 406
510 typ
Seating plane
790 typ
280+/−28 B
A
c
X4
e
e
155 10 20
d
X4
f
1
166 11 21
2
177 12 22
188 13 23
3
199 14 24
4
YYYY
2029
ZZZZ
TAPE AND REEL CONFIGURATION
Die
orientation
dot
Gate
solder bump is
under this
corner
Die is placed into pocket
solder bump side down
(face side down)
Loaded Tape Feed Direction
a
d
e
f g
c b
8 mm pitch, 12 mm wide tape on 7” reel
7” inch reel
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
DIM Dimension (mm)
EPC2029 (Note 1) Target MIN MAX
a12.00 11.90 12.30
b1.75 1.65 1.85
c (Note 2) 5.50 5.45 5.55
d4.00 3.90 4.10
e8.00 7.90 8.10
f (Note 2) 2.00 1.95 2.05
g1.50 1.50 1.60
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
EPC2029 2029 YYYY ZZZZ
2029
YYYY
ZZZZ
Die orientation dot
Gate Pad bump is
under this corner
two 4 we 1nnn x4 wu um 1uuu x4 ‘Mn \ um 4 we 1uuu W I"
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RECOMMENDED
LAND PATTERN
(units in µm)
Pads 1 and 2 are Gate;
Pads 5, 6, 7, 8, 9, 15, 16, 17, 18, 19 are Drain;
Pads 3, 4, 10, 11, 13, 14, 20, 21, 22, 23, 24 are Source;
Pad 12 is Substrate*
*Substrate pin should be connected to Source
Land pattern is solder mask defined
Solder mask opening is 330 µm
It is recommended to have on-Cu trace PCB vias
2600
4600
1000
X4
300
300
500
X4
330
155 10 20
1
166 11 21
2
177 12 22
188 13 23
3
199 14 24
4
RECOMMENDED
STENCIL DRAWING
(units in µm)
RECOMMENDED
STENCIL DRAWING
(units in µm)
2600
4600
1000
X4
300
300
500
X4
330
155 10 20
1
166 11 21
2
177 12 22
188 13 23
3
199 14 24
4
2600
4600
1000
300
300
500300
350
155 10 20
1
166 11 21
2
177 12 22
188 13 23
3
199 14 24
4
Option 1 : Intended for use with SAC305 Type 4 solder.
Option 2 : Intended for use with SAC305 Type 3 solder.
Information subject to
change without notice.
Revised June, 2020
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
Recommended stencil should be 4 mil (100 µm) thick,
must be laser cut, openings per drawing.
Additional assembly resources available at
https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
Recommended stencil should be 4 mil (100 µm) thick,
must be laser cut, openings per drawing.
Additional assembly resources available at
https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

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