EFM8UB1 Datasheet by Silicon Labs

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i” i@ SILIEEIN LABS D I I I I
EFM8 Universal Bee Family
EFM8UB1 Data Sheet
The EFM8UB1, part of the Universal Bee family of MCUs, is a
multi-purpose line of 8-bit microcontrollers with USB feature set in
small packages.
These devices offer high value by integrating an innovative energy-smart USB peripheral
interface, charger detect circuit, 8 kV ESD protection, and enhanced high speed commu-
nication interfaces into small packages, making them ideal for space-constrained USB
applications. With an efficient 8051 core and precision analog, the EFM8UB1 family is
also optimal for embedded applications.
EFM8UB1 applications include the following:
KEY FEATURES
Pipelined 8-bit C8051 core with 50 MHz
maximum operating frequency
Up to 22 multifunction, 5 V tolerant I/O
pins
Low Energy USB with full- and low-speed
support saves up to 90% of the USB
energy
USB charger detect circuit (USB-BCS 1.2
compliant)
One 12-bit ADC and two analog
comparators with internal voltage DAC as
reference input
Five 16-bit timers
Two UARTs, SPI, SMBus/I2C master/
slave and I2C slave
Priority crossbar for flexible pin mapping
USB I/O controls, dongles
High-speed communication bridge
Consumer electronics
Medical equipment
SecurityI/O Ports
Core / Memory Clock Management
CIP-51 8051 Core
(50 MHz)
High Frequency
48 MHz RC
Oscillator
Energy Management
Internal LDO
Regulator
Brown-Out
Detector
Power-On Reset
8-bit SFR bus
Serial Interfaces Timers and Triggers Analog Interfaces
SPI Pin Reset Timer
0/1/2 PCA/PWM
Watchdog
Timer
ADC Comparator 0
Internal
Voltage
Reference
16-bit CRC
Flash Program
Memory
(up to 16 KB)
RAM Memory
(2304 bytes)
Debug Interface
with C2
Lowest power mode with peripheral operational:
IdleNormal ShutdownSuspend Snooze
5 V-to 3.3 V LDO
Regulator
Timer 3/4 Comparator 1
USB
High Frequency
24.5 MHz RC
Oscillator
Pin Wakeup
External
Interrupts
General
Purpose I/O
I2C / SMBus
2 x UART
High-Speed I2C Slave
External CMOS
Oscillator
Low Frequency
RC Oscillator
silabs.com | Building a more connected world. Rev. 1.3
1. Feature List
The EFM8UB1 highlighted features are listed below.
Core
Pipelined CIP-51 Core
Fully compatible with standard 8051 instruction set
70% of instructions execute in 1-2 clock cycles
50 MHz maximum operating frequency
Memory
Up to 16 KB flash memory, in-system re-programmable
from firmware, including 1 KB of 64-byte sectors and 15
KB of 512-byte sectors.
Up to 2304 bytes RAM (including 256 bytes standard 8051
RAM, 1024 bytes on-chip XRAM, and 1024 bytes of USB
buffer)
Power
5 V-input LDO regulator for direct connection to USB sup-
ply
Internal LDO regulator for CPU core voltage
Power-on reset circuit and brownout detectors
I/O: Up to 22 total multifunction I/O pins
All pins 5 V tolerant under bias
Flexible peripheral crossbar for peripheral routing
5 mA source, 12.5 mA sink allows direct drive of LEDs
Clock Sources
Internal 48 MHz oscillator with accuracy of ±1.5% stand-
alone and ±0.25% using USB clock recovery
Internal 24.5 MHz oscillator with ±2% accuracy
Internal 80 kHz low-frequency oscillator
External CMOS clock option
Timers/Counters and PWM
3-channel Programmable Counter Array (PCA) supporting
PWM, capture/compare, and frequency output modes
5 x 16-bit general-purpose timers
Independent watchdog timer, clocked from the low frequen-
cy oscillator
Communications and Digital Peripherals
USB 2.0-compliant full speed with integrated low-power
transceiver, 4 bidirectional endpoints, and dedicated 1 KB
buffer
2 x UART, up to 3 Mbaud
SPI™ Master / Slave, up to 12 Mbps
SMBus™/I2C™ Master / Slave, up to 400 kbps
I2C High-Speed Slave, up to 3.4 Mbps
16-bit CRC unit, supporting automatic CRC of flash at 256-
byte boundaries
Analog
12-Bit Analog-to-Digital Converter (ADC)
2 x Low-current analog comparators with adjustable refer-
ence
On-Chip, Non-Intrusive Debugging
Full memory and register inspection
Four hardware breakpoints, single-stepping
Pre-loaded USB bootloader
Temperature range -40 to 85 ºC
Single power supply of 2.2 to 3.6 V or 3.0 to 5.25 V
QSOP24, QFN28, and QFN20 packages
With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8UB1 devices are truly standalone
system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing nonvolatile data storage and allowing field up-
grades of the firmware. The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory
and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional
while debugging. The on-chip 5V-to-3.3V regulator enables operation from 2.2 V up to a 5.25 V supply. Devices are available in 28-pin
QFN, 20-pin QFN, or 24-pin QSOP packages. All package options are lead-free and RoHS compliant.
EFM8UB1 Data Sheet
Feature List
silabs.com | Building a more connected world. Rev. 1.3 | 2
2. Ordering Information
EFM8 UB1 0 F 16 G A QFN28 R
Tape and Reel (Optional)
Package Type
Revision
Temperature Grade G (-40 to +85)
Flash Memory Size – 16 KB
Memory Type (Flash)
Family Feature Set
Universal Bee 1 Family
Silicon Labs EFM8 Product Line
Figure 2.1. EFM8UB1 Part Numbering
All EFM8UB1 family members have the following features:
CIP-51 Core running up to 50 MHz
Three Internal Oscillators (48 MHz, 24.5 MHz and 80 kHz)
USB Full/Low speed Function Controller
• SMBus
I2C Slave
• SPI
2 UARTs
3-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)
5 16-bit Timers
2 Analog Comparators
12-bit Analog-to-Digital Converter with integrated multiplexer, voltage reference, and temperature sensor
16-bit CRC Unit
Pre-loaded USB bootloader
In addition to these features, each part number in the EFM8UB1 family has a set of features that vary across the product line. The
product selection guide shows the features available on each family member.
Table 2.1. Product Selection Guide
Ordering
Part Number
Flash Memory (kB)
RAM (Bytes)
Digital Port
I/Os (Total)
ADC0 Channels
Comparator 0 Inputs
Comparator 1 Inputs
Pb-free
(RoHS Compliant)
Separate VIO
and VDD Pins
Temperature Range
Package
EFM8UB10F16G-C-QFN28 16 2304 22 20 10 12 Yes -40 to +85 °C QFN28
EFM8UB11F16G-C-QSOP24 16 2304 17 15 8 9 Yes Yes -40 to +85 °C QSOP24
EFM8UB10F16G-C-QFN20 16 2304 13 11 8 5 Yes -40 to +85 °C QFN20
EFM8UB10F8G-C-QFN20 8 2304 13 11 8 5 Yes -40 to +85 °C QFN20
EFM8UB1 Data Sheet
Ordering Information
silabs.com | Building a more connected world. Rev. 1.3 | 3
Table of Contents
1. Feature List ................................2
2. Ordering Information ............................3
3. System Overview ..............................6
3.1 Introduction...............................6
3.2 Power ................................7
3.3 I/O..................................7
3.4 Clocking ................................8
3.5 Counters/Timers and PWM .........................8
3.6 Communications and Other Digital Peripherals ...................9
3.7 Analog ................................12
3.8 Reset Sources .............................13
3.9 Debugging ...............................13
3.10 Bootloader ..............................14
4. Electrical Specifications ..........................16
4.1 Electrical Characteristics ..........................16
4.1.1 Recommended Operating Conditions ....................16
4.1.2 Power Consumption..........................17
4.1.3 Reset and Supply Monitor ........................19
4.1.4 Flash Memory ............................20
4.1.5 Power Management Timing .......................20
4.1.6 Internal Oscillators ..........................21
4.1.7 External Clock Input ..........................21
4.1.8 ADC ...............................22
4.1.9 Voltage Reference ..........................23
4.1.10 Temperature Sensor .........................24
4.1.11 1.8 V Internal LDO Voltage Regulator ...................24
4.1.12 5 V Voltage Regulator.........................24
4.1.13 Comparators ............................25
4.1.14 Port I/O .............................26
4.1.15 USB Transceiver ..........................27
4.1.16 SMBus ..............................28
4.2 Thermal Conditions ............................30
4.3 Absolute Maximum Ratings .........................30
4.4 Typical Performance Curves .........................31
5. Typical Connection Diagrams ........................35
5.1 Power ................................35
5.2 USB .................................37
5.3 Debug ................................39
5.4 Other Connections ............................39
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6. Pin Definitions ..............................40
6.1 EFM8UB1x-QFN28 Pin Definitions .......................40
6.2 EFM8UB1x-QSOP24 Pin Definitions ......................44
6.3 EFM8UB1x-QFN20 Pin Definitions .......................47
7. QFN28 Package Specifications........................ 50
7.1 QFN28 Package Dimensions ........................50
7.2 QFN28 PCB Land Pattern .........................52
7.3 QFN28 Package Marking ..........................53
8. QSOP24 Package Specifications .......................54
8.1 Package Dimensions ...........................54
8.2 PCB Land Pattern ............................56
8.3 Package Marking .............................57
9. QFN20 Package Specifications........................ 58
9.1 QFN20 Package Dimensions ........................58
9.2 QFN20 PCB Land Pattern .........................60
9.3 QFN20 Package Marking ..........................61
10. Revision History............................. 62
silabs.com | Building a more connected world. Rev. 1.3 | 5
cMos ascinzxor Inpm
3. System Overview
3.1 Introduction
System Clock
Configuration
24.5 MHz 2%
Oscillator
CIP-51 8051 Controller
Core
16 KB ISP Flash
Program Memory
256 Byte SRAM
SFR
Bus
1024 Byte XRAM
SYSCLK
Independent
Watchdog
Timer
Power
Net
Voltage
Regulators
VDD
VREGIN
GND
CMOS Oscillator
Input
48 MHz 1.5%
Oscillator
Clock
Recovery
D+
D-
VBUS
USB Peripheral
Controller
1 KB RAM
Full / Low
Speed
Transceiver
Low Freq.
Oscillator
Charge
Detection
Low Power
EXTCLK
Power-On
Reset
Supply
Monitor
C2CK/RSTb Reset
Debug /
Programming
Hardware
C2D
Analog Peripherals
Digital Peripherals
AMUX
Priority
Crossbar
Decoder
Crossbar Control
Port I/O Configuration
CRC
2 Comparators
12/10 bit
ADC Temp
Sensor
VREFVDD
VDD
Internal
Reference
+
-
+
-
UART1
Timers 0,
1, 2, 3, 4
3-ch PCA
I2C /
SMBus
SPI
Port 0
Drivers
Port 1
Drivers
P0.n
Port 2
Drivers P2.n
P1.n
Port 3
Drivers P3.n
UART0
I2C Slave
Figure 3.1. Detailed EFM8UB1 Block Diagram
This section describes the EFM8UB1 family at a high level.
For more information on the device packages and pinout, electrical specifications, and typical connection diagrams, see the EFM8UB1
Data Sheet. For more information on each module including register definitions, see the EFM8UB1 Reference Manual. For more infor-
mation on any errata, see the EFM8UB1 Errata.
EFM8UB1 Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.3 | 6
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode Details Mode Entry Wake-Up Sources
Normal Core and all peripherals clocked and fully operational
Idle Core halted
All peripherals clocked and fully operational
Code resumes execution on wake event
Set IDLE bit in PCON0 Any interrupt
Suspend Core and peripheral clocks halted
HFOSC0 and HFOSC1 oscillators stopped
Regulators in normal bias mode for fast wake
Timer 3 and 4 may clock from LFOSC0
Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0
2. Set SUSPEND bit in
PCON1
USB0 Bus Activity
Timer 4 Event
SPI0 Activity
I2C0 Slave Activity
Port Match Event
Comparator 0 Falling
Edge
Stop All internal power nets shut down
5V regulator remains active (if enabled)
Internal 1.8 V LDO on
Pins retain state
Exit on any reset source
1. Clear STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
Any reset source
Snooze Core and peripheral clocks halted
HFOSC0 and HFOSC1 oscillators stopped
Regulators in low bias current mode for energy sav-
ings
Timer 3 and 4 may clock from LFOSC0
Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0
2. Set SNOOZE bit in
PCON1
USB0 Bus Activity
Timer 4 Event
SPI0 Activity
I2C0 Slave Activity
Port Match Event
Comparator 0 Falling
Edge
Shutdown All internal power nets shut down
5V regulator remains active (if enabled)
Internal 1.8 V LDO off to save energy
Pins retain state
Exit on pin or power-on reset
1. Set STOPCF bit in
REG0CN
2. Set STOP bit in
PCON0
RSTb pin reset
Power-on reset
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.3 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P3.0 and P3.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P3.0.
The port control block offers the following features:
Up to 22 multi-functions I/O pins, supporting digital and analog functions.
Flexible priority crossbar decoder for digital peripheral assignment.
Two drive strength settings for each port.
Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
Up to 20 direct-pin interrupt sources with shared interrupt vector (Port Match).
EFM8UB1 Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.3 | 7
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 24.5 MHz oscillator divided by 8.
The clock control system offers the following features:
Provides clock to core and peripherals.
24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.
48 MHz internal oscillator (HFOSC1), accurate to ±1.5% over supply and temperature corners.
80 kHz low-frequency oscillator (LFOSC0).
External CMOS clock input (EXTCLK).
Clock divider with eight settings for flexible clock scaling:
Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
HFOSC0 and HFOSC1 include 1.5x pre-scalers for further flexibility.
3.5 Counters/Timers and PWM
Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU
intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare mod-
ule for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.
Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software
Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own
associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.
16-bit time base
Programmable clock divisor and clock source selection
Up to three independently-configurable channels
8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation)
Output polarity control
Frequency output mode
Capture on rising, falling or any edge
Compare function for arbitrary waveform generation
Software timer (internal compare) mode
Can accept hardware “kill” signal from comparator 0
EFM8UB1 Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.3 | 8
Timers (Timer 0, Timer 1, Timer 2, Timer 3, and Timer 4)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time inter-
vals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.
Timer 0 and Timer 1 include the following features:
Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.
Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.
8-bit auto-reload counter/timer mode
13-bit counter/timer mode
16-bit counter/timer mode
Dual 8-bit counter/timer mode (Timer 0)
Timer 2, Timer 3 and Timer 4 are 16-bit timers including the following features:
Clock sources for all timers include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8.
LFOSC0 divided by 8 may be used to clock Timer 3 and Timer 4 in active or suspend/snooze power modes.
Timer 4 is a low-power wake source, and can be chained together with Timer 3.
16-bit auto-reload timer mode.
Dual 8-bit auto-reload timer mode.
External pin capture.
LFOSC0 capture.
Comparator 0 capture.
USB Start-of-Frame (SOF) capture.
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) running off the low-frequency oscillator. A WDT overflow forces the MCU
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by
system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset.
The state of the RST pin is unaffected by this reset.
The Watchdog Timer has the following features:
Programmable timeout interval
Runs from the low-frequency oscillator
Lock-out feature to prevent any modification until a system reset
3.6 Communications and Other Digital Peripherals
Universal Serial Bus (USB0)
The USB0 peripheral provides a full-speed USB 2.0 compliant device controller and PHY with additional Low Energy USB features. The
device supports both full-speed (12MBit/s) and low speed (1.5MBit/s) operation, and includes a dedicated USB oscillator with clock re-
covery mechanism for crystal-free operation. No external components are required. The USB function controller (USB0) consists of a
Serial Interface Engine (SIE), USB transceiver (including matching resistors and configurable pull-up resistors), and 1 KB FIFO block.
The Low Energy Mode ensures the current consumption is optimized and enables USB communication on a strict power budget.
The USB0 module includes the following features:
Full and Low Speed functionality.
Implements 4 bidirectional endpoints.
Low Energy Mode to reduce active supply current based on bus bandwidth.
USB 2.0 compliant USB peripheral support (no host capability).
Direct module access to 1 KB of RAM for FIFO memory.
Clock recovery to meet USB clocking requirements with no external components.
Charger detection circuitry with automatic detection of SDP, CDP, and DCP interfaces.
D+ and D- can be routed to ADC input to support ACM and proprietary charger architectures.
EFM8UB1 Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.3 | 9
Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support
allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a
second incoming data byte before software has finished reading the previous data byte.
The UART module provides the following features:
Asynchronous transmissions and receptions.
Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive).
8- or 9-bit data.
Automatic start and stop generation.
Single-byte FIFO on transmit and receive.
Universal Asynchronous Receiver/Transmitter (UART1)
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a
16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates. A received data FIFO allows UART1
to receive multiple bytes before data is lost and an overflow occurs.
UART1 provides the following features:
Asynchronous transmissions and receptions.
Dedicated baud rate generator supports baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive).
5, 6, 7, 8, or 9 bit data.
Automatic start and stop generation.
Automatic parity generation and checking.
Four byte FIFO on transmit and receive.
Auto-baud detection.
LIN break and sync field detection.
CTS / RTS hardware flow control.
Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional
general purpose port I/O pins can be used to select multiple slave devices in master mode.
Supports 3- or 4-wire master or slave modes.
Supports external clock frequencies up to 12 Mbps in master or slave mode.
Support for all clock phase and polarity modes.
8-bit programmable clock rate (master).
Programmable receive timeout (slave).
Four byte FIFO on transmit and receive.
Can operate in suspend or snooze modes and wake the CPU on reception of a byte.
Support for multiple masters on the same data lines.
EFM8UB1 Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.3 | 10
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica-
tion, version 1.1, and compatible with the I2C serial bus.
The SMBus module includes the following features:
Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds
Support for master, slave, and multi-master modes
Hardware synchronization and arbitration for multi-master mode
Clock low extending (clock stretching) to interface with faster masters
Hardware support for 7-bit slave and general call address recognition
Firmware support for 10-bit slave address decoding
Ability to inhibit all slave states
Programmable data setup/hold times
Transmit and receive FIFOs (one byte) to help increase throughput in faster applications
I2C Slave (I2CSLAVE0)
The I2C Slave interface is a 2-wire, bidirectional serial bus that is compatible with the I2C Bus Specification 3.0. It is capable of transfer-
ring in high-speed mode (HS-mode) at speeds of up to 3.4 Mbps. Firmware can write to the I2C interface, and the I2C interface can
autonomously control the serial transfer of data. The interface also supports clock stretching for cases where the core may be tempora-
rily prohibited from transmitting a byte or processing a received byte during an I2C transaction. This module operates only as an I2C
slave device.
The I2C module includes the following features:
Standard (up to 100 kbps), Fast (400 kbps), Fast Plus (1 Mbps), and High-speed (3.4 Mbps) transfer speeds
Support for slave mode only
Clock low extending (clock stretching) to interface with faster masters
Hardware support for 7-bit slave address recognition
Transmit and receive FIFOs (two bytes) to help increase throughput in faster applications
16-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts
the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the
flash contents of the device.
The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC
module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features:
Support for CCITT-16 polynomial
Byte-level bit reversal
Automatic CRC of flash contents on one or more 256-byte blocks
Initial seed selection of 0x0000 or 0xFFFF
EFM8UB1 Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.3 | 11
3.7 Analog
12-Bit Analog-to-Digital Converter (ADC0)
The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes, integrated track-and hold and a program-
mable window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to
measure different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external
reference sources.
Up to 20 external inputs.
Single-ended 12-bit and 10-bit modes.
Supports an output update rate of 200 ksps samples per second in 12-bit mode or 800 ksps samples per second in 10-bit mode.
Operation in low power modes at lower conversion speeds.
Asynchronous hardware conversion trigger, selectable between software, external I/O and internal timer sources.
Output data window comparator allows automatic range checking.
Support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on set-
tling and tracking time.
Conversion complete and window compare interrupts supported.
Flexible output data formatting.
Includes an internal fast-settling reference with two levels (1.65 V and 2.4 V) and support for external reference and signal ground.
Integrated temperature sensor.
Low Current Comparators (CMP0, CMP1)
Analog comparators are used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.
External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and
negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.
The comparator includes the following features:
Up to 10 (CMP0) or 12 (CMP1) external positive inputs
Up to 10 (CMP0) or 12 (CMP1) external negative inputs
Additional input options:
Internal connection to LDO output
Direct connection to GND
Direct connection to VDD
Dedicated 6-bit reference DAC
Synchronous and asynchronous outputs can be routed to pins via crossbar
Programmable hysteresis between 0 and ±20 mV
Programmable response time
Interrupts generated on rising, falling, or both edges
PWM output kill feature
EFM8UB1 Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.3 | 12
3.8 Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
The core halts program execution.
Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
External port pins are forced to a known state.
Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latch-
es are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.
Reset sources on the device include:
Power-on reset
External reset pin
Comparator reset
Software-triggered reset
Supply monitor reset (monitors VDD supply)
Watchdog timer reset
Missing clock detector reset
Flash error reset
USB reset
3.9 Debugging
The EFM8UB1 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debug-
ging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2
protocol.
EFM8UB1 Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.3 | 13
3.10 Bootloader
All devices come pre-programmed with a USB bootloader. This bootloader resides in the code security page and last pages of code
flash; it can be erased if it is not needed.
The byte before the Lock Byte is the Bootloader Signature Byte. Setting this byte to a value of 0xA5 indicates the presence of the boot-
loader in the system. Any other value in this location indicates that the bootloader is not present in flash.
When a bootloader is present, the device will jump to the bootloader vector after any reset, allowing the bootloader to run. The boot-
loader then determines if the device should stay in bootload mode or jump to the reset vector located at 0x0000. When the bootloader
is not present, the device will jump to the reset vector of 0x0000 after any reset.
More information about the bootloader protocol and usage can be found in AN945: EFM8 Factory Bootloader User Guide. Application
notes can be found on the Silicon Labs website (www.silabs.com/8bit-appnotes) or within Simplicity Studio by using the [Application
Notes] tile.
0x0000
0x3FFF
0x4000
0xF7FF
0xF800
0xFBBF
0xFBC0
0xFFC0
0xFFFF
0xFC00
0xFFBF
16 KB Code
(32 x 512 Byte pages)
Reserved
Nonvolatile Data
Code Security Page
64 Bytes
Read-Only
Reserved
Bootloader Vector
Reset Vector
Bootloader Bootloader
0xFBFE
0xFBFF Lock Byte
Bootloader Signature Byte
Figure 3.2. Flash Memory Map with Bootloader—16 KB Devices
EFM8UB1 Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.3 | 14
Table 3.2. Summary of Pins for Bootloader Communication
Bootloader Pins for Bootload Communication
UART TX – P0.4
RX – P0.5
USB VBUS
D+
D-
Table 3.3. Summary of Pins for Bootload Mode Entry
Device Package Pin for Bootload Mode Entry
QFN28 P3.0 / C2D
QSOP24 P2.0 / C2D
QFN20 P2.0 / C2D
EFM8UB1 Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.3 | 15
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the conditions listed in Table 4.1 Recommended Operating Conditions on page
16, unless stated otherwise.
4.1.1 Recommended Operating Conditions
Table 4.1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Operating Supply Voltage on VDD
1
VDD 2.2 — 3.6 V
Operating Supply Voltage on VIO 3VIO 1.71 — VDD V
Operating Supply Voltage on VRE-
GIN
VREGIN 3.0 — 5.25 V
System Clock Frequency fSYSCLK 0 50 MHz
Operating Ambient Temperature TA-40 — 85 °C
Note:
1. Standard USB compliance tests require a minimum of 3.0 V on VDD for compliant operation.
2. All voltages with respect to GND.
3. On devices without a VIO pin, VIO = VDD.
4. GPIO levels are undefined whenever VIO is less than 1 V.
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 16
4.1.2 Power Consumption
Table 4.2. Power Consumption
Parameter Symbol Test Condition Min Typ Max Unit
Digital Core Supply Current
Normal Mode-Full speed with code
executing from flash
IDD FSYSCLK = 48 MHz (HFOSC1) 2 9.4 10.1 mA
FSYSCLK = 24.5 MHz (HFOSC0) 2 4.5 5.2 mA
FSYSCLK = 1.53 MHz (HFOSC0) 2 — 600 — μA
FSYSCLK = 80 kHz 3— 145 — μA
Idle Mode-Core halted with periph-
erals running
IDD FSYSCLK = 48 MHz (HFOSC1) 2 6.3 6.8 mA
FSYSCLK = 24.5 MHz (HFOSC0) 2 2.9 3.3 mA
FSYSCLK = 1.53 MHz (HFOSC0) 2 — 440 — μA
FSYSCLK = 80 kHz 3— 130 — μA
Suspend Mode-Core halted and
high frequency clocks stopped,
Supply monitor off.
IDD LFO Running 125 μA
LFO Stopped 120 μA
Snooze Mode-Core halted and
high frequency clocks stopped.
Regulator in low-power state, Sup-
ply monitor off.
IDD LFO Running 25 μA
LFO Stopped 20 μA
Stop Mode—Core halted and all
clocks stopped,Internal LDO On,
Supply monitor off.
IDD — 120 — μA
Shutdown Mode—Core halted and
all clocks stopped,Internal LDO
Off, Supply monitor off.
IDD — 0.2 — μA
Analog Peripheral Supply Currents
High-Frequency Oscillator 0 IHFOSC0 Operating at 24.5 MHz,
TA = 25 °C
— 105 — μA
High-Frequency Oscillator 1 IHFOSC1 Operating at 48 MHz,
TA = 25 °C
— 850 — μA
Low-Frequency Oscillator ILFOSC Operating at 80 kHz,
TA = 25 °C
4 — μA
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 17
Parameter Symbol Test Condition Min Typ Max Unit
ADC0 Always-on 4IADC 800 ksps, 10-bit conversions or
200 ksps, 12-bit conversions
Normal bias settings
VDD = 3.0 V
820 1200 μA
250 ksps, 10-bit conversions or
62.5 ksps 12-bit conversions
Low power bias settings
VDD = 3.0 V
405 580 μA
ADC0 Burst Mode, 10-bit single
conversions, external reference
IADC 200 ksps, VDD = 3.0 V 370 μA
100 ksps, VDD = 3.0 V 185 μA
10 ksps, VDD = 3.0 V 20 μA
ADC0 Burst Mode, 10-bit single
conversions, internal reference,
Low power bias settings
IADC 200 ksps, VDD = 3.0 V 485 μA
100 ksps, VDD = 3.0 V 245 μA
10 ksps, VDD = 3.0 V 25 μA
ADC0 Burst Mode, 12-bit single
conversions, external reference
IADC 100 ksps, VDD = 3.0 V 505 μA
50 ksps, VDD = 3.0 V 255 μA
10 ksps, VDD = 3.0 V 50 μA
ADC0 Burst Mode, 12-bit single
conversions, internal reference
IADC 100 ksps, VDD = 3.0 V,
Normal bias
— 950 — μA
50 ksps, VDD = 3.0 V,
Low power bias
— 415 — μA
10 ksps, VDD = 3.0 V,
Low power bias
80 — μA
Internal ADC0 Reference, Always-
on 5
IVREFFS Normal Power Mode 680 790 μA
Low Power Mode 170 210 μA
Temperature Sensor ITSENSE 70 120 μA
Comparator 0 (CMP0, CMP1) ICMP CPMD = 11 0.5 μA
CPMD = 10 3 μA
CPMD = 01 8.5 μA
CPMD = 00 22.5 μA
Comparator Reference6ICPREF — 1.2 — μA
Voltage Supply Monitor (VMON0) IVMON 15 20 μA
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 18
Parameter Symbol Test Condition Min Typ Max Unit
5V Regulator IVREG Normal Mode
(SUSEN = 0, BIASENB = 0)
245 340 μA
Suspend Mode
(SUSEN = 1, BIASENB = 0)
60 100 μA
Bias Disabled
(BIASENB = 1)
2.5 10 μA
Disabled
(BIASENB = 1, REG1ENB = 1)
— 2.5 — nA
USB (USB0) Full-Speed IUSB Low Energy Mode, 64 byte 1ms IN
Interrupt transfers
— 850 — μA
Low Energy Mode, 64 byte 1ms
OUT Interrupt transfers
— 250 — μA
Low Energy Mode, Idle (SOF only) 50 μA
Note:
1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increa-
ses supply current by the specified amount.
2. Includes supply current from internal LDO regulator, supply monitor, and High Frequency Oscillator.
3. Includes supply current from internal LDO regulator, supply monitor, and Low Frequency Oscillator.
4. ADC0 always-on power excludes internal reference supply current.
5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
6. This value is the current sourced from the pin or supply selected as the full-scale reference to the comparator DAC.
4.1.3 Reset and Supply Monitor
Table 4.3. Reset and Supply Monitor
Parameter Symbol Test Condition Min Typ Max Unit
VDD Supply Monitor Threshold VVDDM 1.95 2.05 2.15 V
Power-On Reset (POR) Threshold VPOR Rising Voltage on VDD 1.2 V
Falling Voltage on VDD 0.75 1.36 V
VDD Ramp Time tRMP Time to VDD > 2.2 V 10 μs
Reset Delay from POR tPOR Relative to VDD > VPOR 3 10 31 ms
Reset Delay from non-POR source tRST Time between release of reset
source and code execution
— 50 — μs
RST Low Time to Generate Reset tRSTL 15 — μs
Missing Clock Detector Response
Time (final rising edge to reset)
tMCD FSYSCLK >1 MHz 0.625 1.2 ms
Missing Clock Detector Trigger
Frequency
FMCD 7.5 13.5 kHz
VDD Supply Monitor Turn-On Time tMON 2 — μs
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 19
4.1.4 Flash Memory
Table 4.4. Flash Memory
Parameter Symbol Test Condition Min Typ Max Units
Write Time1 , 2tWRITE One Byte,
FSYSCLK = 24.5 MHz
19 20 21 μs
Erase Time1 , 2tERASE One Page,
FSYSCLK = 24.5 MHz
5.2 5.35 5.5 ms
VDD Voltage During Programming 3VPROG 2.2 — 3.6 V
Endurance (Write/Erase Cycles) NWE 20k 100k — Cycles
CRC Calculation Time tCRC One 256-Byte Block
SYSCLK = 48 MHz
— 5.5 — µs
Note:
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.
2. The internal High-Frequency Oscillator 0 has a programmable output frequency, which is factory programmed to 24.5 MHz. If
user firmware adjusts the oscillator speed, it must be between 22 and 25 MHz during any flash write or erase operation. It is
recommended to write the HFO0CAL register back to its reset value when writing or erasing flash.
3. Flash can be safely programmed at any voltage above the supply monitor threshold (VVDDM).
4. Data Retention Information is published in the Quarterly Quality and Reliability Report.
4.1.5 Power Management Timing
Table 4.5. Power Management Timing
Parameter Symbol Test Condition Min Typ Max Units
Idle Mode Wake-up Time tIDLEWK 2 3 SYSCLKs
Suspend Mode Wake-up Time tSUS-
PENDWK
SYSCLK = HFOSC0
CLKDIV = 0x00
— 170 — ns
Snooze Mode Wake-up Time tSLEEPWK SYSCLK = HFOSC0
CLKDIV = 0x00
— 12 — µs
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 20
4.1.6 Internal Oscillators
Table 4.6. Internal Oscillators
Parameter Symbol Test Condition Min Typ Max Unit
High Frequency Oscillator 0 (24.5 MHz)
Oscillator Frequency fHFOSC0 Full Temperature and Supply
Range
24 24.5 25 MHz
Power Supply Sensitivity PSSHFOS
C0
TA = 25 °C 0.5 %/V
Temperature Sensitivity TSHFOSC0 VDD = 3.0 V 40 ppm/°C
High Frequency Oscillator 1 (48 MHz)
Oscillator Frequency fHFOSC1 Full Temperature and Supply
Range
47.3 48 48.7 MHz
Power Supply Sensitivity PSSHFOS
C1
TA = 25 °C 0.02 %/V
Temperature Sensitivity TSHFOSC1 VDD = 3.0 V 45 ppm/°C
Low Frequency Oscillator (80 kHz)
Oscillator Frequency fLFOSC Full Temperature and Supply
Range
75 80 85 kHz
Power Supply Sensitivity PSSLFOSC TA = 25 °C 0.05 %/V
Temperature Sensitivity TSLFOSC VDD = 3.0 V 65 ppm/°C
4.1.7 External Clock Input
Table 4.7. External Clock Input
Parameter Symbol Test Condition Min Typ Max Unit
External Input CMOS Clock
Frequency (at EXTCLK pin)
fCMOS 0 50 MHz
External Input CMOS Clock High
Time
tCMOSH 9 — ns
External Input CMOS Clock Low
Time
tCMOSL 9 — ns
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 21
4.1.8 ADC
Table 4.8. ADC
Parameter Symbol Test Condition Min Typ Max Unit
Resolution Nbits 12 Bit Mode 12 Bits
10 Bit Mode 10 Bits
Throughput Rate
(High Speed Mode)
fS12 Bit Mode 200 ksps
10 Bit Mode 800 ksps
Throughput Rate
(Low Power Mode)
fS12 Bit Mode 62.5 ksps
10 Bit Mode 250 ksps
Tracking Time tTRK High Speed Mode 230 ns
Low Power Mode 450 ns
Power-On Time tPWR 1.2 — μs
SAR Clock Frequency fSAR High Speed Mode,
Reference is 2.4 V internal
6.25 MHz
High Speed Mode,
Reference is not 2.4 V internal
12.5 MHz
Low Power Mode 4 MHz
Conversion Time tCNV 10-Bit Conversion,
SAR Clock = 12.25 MHz,
System Clock = 24.5 MHz.
1.1 μs
Sample/Hold Capacitor CSAR Gain = 1 5 pF
Gain = 0.5 2.5 pF
Input Pin Capacitance CIN — 20 — pF
Input Mux Impedance RMUX — 550 — Ω
Voltage Reference Range VREF 1 — VDD V
Input Voltage Range 1VIN Gain = 1 0 VREF V
Gain = 0.5 0 2xVREF V
Power Supply Rejection Ratio PSRRADC 70 — dB
DC Performance
Integral Nonlinearity INL 12 Bit Mode ±1 ±2.3 LSB
10 Bit Mode ±0.2 ±0.6 LSB
Differential Nonlinearity (Guaran-
teed Monotonic)
DNL 12 Bit Mode -1 ±0.7 1.9 LSB
10 Bit Mode ±0.2 ±0.6 LSB
Offset Error EOFF 12 Bit Mode, VREF = 1.65 V -3 0 3 LSB
10 Bit Mode, VREF = 1.65 V -2 0 2 LSB
Offset Temperature Coefficient TCOFF 0.004 — LSB/°C
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 22
Parameter Symbol Test Condition Min Typ Max Unit
Slope Error EM12 Bit Mode ±0.02 ±0.1 %
10 Bit Mode ±0.06 ±0.24 %
Dynamic Performance 10 kHz Sine Wave Input 1dB below full scale, Max throughput, using AGND pin
Signal-to-Noise SNR 12 Bit Mode 61 66 dB
10 Bit Mode 53 60 dB
Signal-to-Noise Plus Distortion SNDR 12 Bit Mode 61 66 dB
10 Bit Mode 53 60 dB
Total Harmonic Distortion (Up to
5th Harmonic)
THD 12 Bit Mode 71 dB
10 Bit Mode 70 dB
Spurious-Free Dynamic Range SFDR 12 Bit Mode -79 dB
10 Bit Mode -70 dB
Note:
1. Absolute input pin voltage is limited by the VDD supply.
4.1.9 Voltage Reference
Table 4.9. Voltage Reference
Parameter Symbol Test Condition Min Typ Max Unit
Internal Fast Settling Reference
Output Voltage
(Full Temperature and Supply
Range)
VREFFS 1.65 V Setting 1.62 1.65 1.68 V
2.4 V Setting, VDD > 2.6 V 2.35 2.4 2.45 V
Temperature Coefficient TCREFFS 50 — ppm/°C
Turn-on Time tREFFS 1.5 μs
Power Supply Rejection PSRRREF
FS
400 — ppm/V
External Reference
Input Current IEXTREF Sample Rate = 800 ksps; VREF =
3.0 V
8 — μA
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 23
4.1.10 Temperature Sensor
Table 4.10. Temperature Sensor
Parameter Symbol Test Condition Min Typ Max Unit
Offset VOFF TA = 0 °C 757 mV
Offset Error 1EOFF TA = 0 °C 17 mV
Slope M 2.85 — mV/°C
Slope Error 1EM 70 — μV/°
Linearity — 0.5 — °C
Turn-on Time 1.8 μs
Note:
1. Represents one standard deviation from the mean.
4.1.11 1.8 V Internal LDO Voltage Regulator
Table 4.11. 1.8V Internal LDO Voltage Regulator
Parameter Symbol Test Condition Min Typ Max Unit
Output Voltage VOUT_1.8V 1.78 1.85 1.92 V
4.1.12 5 V Voltage Regulator
Table 4.12. 5V Voltage Regulator
Parameter Symbol Test Condition Min Typ Max Unit
Input Voltage Range 1 VREGIN 3.0 — 5.25 V
Output Voltage on VDD 2VREGOUT Output Current = 1 to 100 mA
Regulation range (VREGIN ≥ 4.1V)
3.1 3.3 3.6 V
Output Current = 1 to 100 mA
Dropout range (VREGIN < 4.1V)
— VREGIN
VDROPOUT
— V
Output Current 2IREGOUT 100 mA
Dropout Voltage VDROPOUT Output Current = 100 mA 0.8 V
Note:
1. Input range to meet the Output Voltage on VDD specification. If the 5 V voltage regulator is not used, VREGIN should be tied to
VDD.
2. Output current is total regulator output, including any current required by the device.
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 24
4.1.13 Comparators
Table 4.13. Comparators
Parameter Symbol Test Condition Min Typ Max Unit
Response Time, CPMD = 00
(Highest Speed)
tRESP0 +100 mV Differential, VCM = 1.65 V 110 ns
-100 mV Differential, VCM = 1.65 V 160 ns
Response Time, CPMD = 11 (Low-
est Power)
tRESP3 +100 mV Differential, VCM = 1.65 V 1.2 μs
-100 mV Differential, VCM = 1.65 V 4.5 μs
Positive Hysteresis
Mode 0 (CPMD = 00)
HYSCP+ CPHYP = 00 0.4 mV
CPHYP = 01 8 mV
CPHYP = 10 16 mV
CPHYP = 11 32 mV
Negative Hysteresis
Mode 0 (CPMD = 00)
HYSCP- CPHYN = 00 -0.4 mV
CPHYN = 01 -8 mV
CPHYN = 10 -16 mV
CPHYN = 11 -32 mV
Positive Hysteresis
Mode 3 (CPMD = 11)
HYSCP+ CPHYP = 00 1.5 mV
CPHYP = 01 4 mV
CPHYP = 10 8 mV
CPHYP = 11 16 mV
Negative Hysteresis
Mode 3 (CPMD = 11)
HYSCP- CPHYN = 00 -1.5 mV
CPHYN = 01 -4 mV
CPHYN = 10 -8 mV
CPHYN = 11 -16 mV
Input Range (CP+ or CP-) VIN Direct comparator input -0.25 VDD+0.25 V
Reference DAC input 1.2 VDD V
Reference DAC Resolution Nbits 6 bits
Reference DAC Input Impedance RCPREF — 2.75 —
Input Pin Capacitance CCP — 7.5 — pF
Common-Mode Rejection Ratio CMRRCP 70 — dB
Power Supply Rejection Ratio PSRRCP 72 — dB
Input Offset Voltage VOFF TA = 25 °C -10 0 10 mV
Input Offset Tempco TCOFF 3.5 — μV/°
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 25
4.1.14 Port I/O
Table 4.14. Port I/O
Parameter Symbol Test Condition Min Typ Max Unit
Output High Voltage (High Drive)1VOH IOH = -7 mA, VIO ≥ 3.0 V VIO - 0.7 V
IOH = -3.3 mA, 2.2 V ≤ VIO < 3.0 V
IOH = -1.8 mA, 1.71 V ≤ VIO < 2.2 V
VIO x 0.8 V
Output Low Voltage (High Drive)1VOL IOL = 13.5 mA, VIO ≥ 3.0 V 0.6 V
IOL = 7 mA, 2.2 V ≤ VIO < 3.0 V
IOL = 3.6 mA, 1.71 V ≤ VIO < 2.2 V
— VIO x 0.2 V
Output High Voltage (Low Drive)1VOH IOH = -4.75 mA, VIO ≥ 3.0 V VIO - 0.7 V
IOH = -2.25 mA, 2.2 V ≤ VIO < 3.0 V
IOH = -1.2 mA, 1.71 V ≤ VIO < 2.2 V
VIO x 0.8 V
Output Low Voltage (Low Drive)1VOL IOL = 6.5 mA, VIO ≥ 3.0 V 0.6 V
IOL = 3.5 mA, 2.2 V ≤ VIO < 3.0 V
IOL = 1.8 mA, 1.71 V ≤ VIO < 2.2 V
— VIO x 0.2 V
Input High Voltage
(all port pins including VBUS)
VIH VIO - 0.6 V
Input Low Voltage
(all port pins including VBUS)
VIL — 0.6 V
Pin Capacitance CIO 7 — pF
Weak Pull-Up Current
(VIN = 0 V)
IPU VIO = 3.6 -30 -20 -10 μA
Input Leakage (Pullups off or Ana-
log)
ILK GND < VIN < VIO -1.1 — 1.1 μA
Input Leakage Current with VIN
above VIO
ILK VIO < VIN < VIO+2.0 V 0 5 150 μA
Note:
1. See Figure 4.7 Typical VOH Curves on page 34 and Figure 4.8 Typical VOL Curves on page 34 for more information.
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 26
4.1.15 USB Transceiver
Table 4.15. USB Transceiver
Parameter Symbol Test Condition Min Typ Max Unit
Transmitter
Output High Voltage VOH VDD ≥3.0V 2.8 V
Output Low Voltage VOL VDD ≥3.0V 0.8 V
Output Crossover Point VCRS 1.3 — 2.0 V
Output Impedance ZDRV Driving High
Driving Low
28
28
36
36
44
44
Ω
Pull-up Resistance RPU Full Speed (D+ Pull-up)
Low Speed (D- Pull-up)
1.425 1.5 1.575
Output Rise Time TRLow Speed 75 300 ns
Full Speed 4 20 ns
Output Fall Time TFLow Speed 75 300 ns
Full Speed 4 20 ns
Receiver
Differential Input
Sensitivity
VDI | (D+) - (D-) | 0.2 V
Differential Input Common Mode
Range
VCM 0.8 — 2.5 V
Input Leakage Current ILPullups Disabled <1.0 μA
Refer to the USB Specification for timing diagrams and symbol definitions.
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 27
4.1.16 SMBus
Table 4.16. SMBus Peripheral Timing Performance (Master Mode)
Parameter Symbol Test Condition Min Typ Max Unit
Standard Mode (100 kHz Class)
I2C Operating Frequency fI2C 0 702kHz
SMBus Operating Frequency fSMB 401702kHz
Bus Free Time Between STOP and
START Conditions
tBUF 9.4 — µs
Hold Time After (Repeated)
START Condition
tHD:STA 4.7 — µs
Repeated START Condition Setup
Time
tSU:STA 9.4 — µs
STOP Condition Setup Time tSU:STO 9.4 — µs
Data Hold Time tHD:DAT 2753 — ns
Data Setup Time tSU:DAT 3003 — ns
Detect Clock Low Timeout tTIMEOUT 25 — ms
Clock Low Period tLOW 4.7 — µs
Clock High Period tHIGH 9.4 504µs
Fast Mode (400 kHz Class)
I2C Operating Frequency fI2C 0 2552kHz
SMBus Operating Frequency fSMB 4012552kHz
Bus Free Time Between STOP and
START Conditions
tBUF 2.6 — µs
Hold Time After (Repeated)
START Condition
tHD:STA 1.3 — µs
Repeated START Condition Setup
Time
tSU:STA 2.6 — µs
STOP Condition Setup Time tSU:STO 2.6 — µs
Data Hold Time tHD:DAT 2753 — ns
Data Setup Time tSU:DAT 3003 — ns
Detect Clock Low Timeout tTIMEOUT 25 — ms
Clock Low Period tLOW 1.3 — µs
Clock High Period tHIGH 2.6 504µs
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 28
Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. The minimum SMBus frequency is limited by the maximum Clock High Period requirement of the SMBus specification.
2. The maximum I2C and SMBus frequencies are limited by the minimum Clock Low Period requirements of their respective specifi-
cations. The maximum frequency cannot be achieved with all combinations of oscillators and dividers available, but the effective
frequency must not exceed 256 kHz.
3. Data setup and hold timing at 40 MHz or lower with EXTHOLD set to 1.
4. SMBus has a maximum requirement of 50 µs for Clock High Period. Operating frequencies lower than 40 kHz will be longer than
50 µs. I2C can support periods longer than 50 µs.
Table 4.17. SMBus Peripheral Timing Formulas (Master Mode)
Parameter Symbol Clocks
SMBus Operating Frequency fSMB fCSO / 3
Bus Free Time Between STOP and START Conditions tBUF 2 / fCSO
Hold Time After (Repeated) START Condition tHD:STA 1 / fCSO
Repeated START Condition Setup Time tSU:STA 2 / fCSO
STOP Condition Setup Time tSU:STO 2 / fCSO
Clock Low Period tLOW 1 / fCSO
Clock High Period tHIGH 2 / fCSO
Note:
1. fCSO is the SMBus peripheral clock source overflow frequency.
tLOW
S PSP
VIH
VIL
VIH
VIL
SCL
SDA
tBUF
tHD:STA tHD:DAT
tHIGH
tSU:DAT
tSU:STA tSU:STO
Figure 4.1. SMBus Peripheral Timing Diagram (Master Mode)
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 29
4.2 Thermal Conditions
Table 4.18. Thermal Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Thermal Resistance (Junction to
Ambient)
θJA QFN-20 Packages 60 °C/W
QFN-28 Packages 26 °C/W
QSOP-24 Packages 65 °C/W
Thermal Resistance (Junction to
Case)
θJC QFN-20 Packages 32.9 °C/W
QFN-28 Packages 18.8 °C/W
Thermal Characterization Parame-
ter (Junction to Top)
ΨJT QFN-20 Packages 0.88 °C/W
QFN-28 Packages 0.3 °C/W
Note:
1. Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
4.3 Absolute Maximum Ratings
Stresses above those listed in 4.3 Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specifica-
tion is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on
the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/
default.aspx.
Table 4.19. Absolute Maximum Ratings
Parameter Symbol Test Condition Min Max Unit
Ambient Temperature Under Bias TBIAS -55 125 °C
Storage Temperature TSTG -65 150 °C
Voltage on VDD VDD GND-0.3 4.2 V
Voltage on VIO2VIO GND-0.3 4.2 V
Voltage on VREGIN VREGIN GND-0.3 5.8 V
Voltage on D+ or D- VUSBD GND-0.3 VDD+0.3 V
Voltage on I/O pins (including VBUS /
P3.1) or RSTb
VIN VIO > 3.3 V GND-0.3 5.8 V
VIO < 3.3 V GND-0.3 VIO+2.5 V
Total Current Sunk into Supply Pin IVDD 400 mA
Total Current Sourced out of Ground
Pin
IGND 400 ─ mA
Current Sourced or Sunk by any I/O
Pin or RSTb
IIO -100 100 mA
Operating Junction Temperature TJ-40 105 °C
Note:
1. Exposure to maximum rating conditions for extended periods may affect device reliability.
2. On devices without a VIO pin, VIO = VDD
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 30
Supply Current (mA) Supp‘y Current (mA) 10 — Nema‘ Mode — menace o 5 10 15 20 25 Operating Frequency (MHZ) r r r — Nurma‘ Mode — We Made r 10 20 30 40 50 Operating Frequency (MHZ)
4.4 Typical Performance Curves
Figure 4.2. Typical Operating Supply Current using HFOSC0
Figure 4.3. Typical Operating Supply Current using HFOSC1
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 31
Supp‘y Current (uA) 1200 1000 300 600 400 200 0.20 0157 — Narmamode — Id‘eMode 0.10 , Supp‘y Current (mA) 0057 0.00 10 10-bit Burst Mode, Single Conversions ‘ 3D 40 50 60 Operating Frequency (km) 70 30 12-bit Burst Mode, Single Conversions — Noma‘ mas, \nlemal Reference ‘ ‘ — Norma‘ Bias, \nterna\ Reference ‘ ‘ ‘ — LP Bias. \nlema‘ Relerenze — LP Ems, \ntema‘ Reference — mam orVDD Reference — mm oerr: Reference 1000 , 7 ‘é 800 7 7 ‘5 2 7 ‘5 600 7 7 U 2' o. 7 g 400 7 7 w , 200 , , ‘ ‘ ‘ ‘ ‘ ‘ 0 ‘ ‘ ‘ ‘ ‘ ‘ o 50 100 150 200 250 300 o 20 40 so so 100 120 Sample Rate (ksps) Samp‘e Rate (ksps)
Figure 4.4. Typical Operating Supply Current using LFOSC
Figure 4.5. Typical ADC0 and Internal Reference Supply Current in Burst Mode
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 32
Supp‘y Current (uA) Supp‘y Current (MA) 107bit Conversions, Norma‘ Bias lorbit Conversions, Low Power Bias 900 ‘ ‘ ‘ ‘ ‘ ‘ — qu:35v — VDD=3V 430 350 — vDD=22v 3 420 3 300 E 410 E 400 U 75° E 390 a 3 m 380 700 370 550 ‘ ‘ ‘ ‘ ‘ ‘ 360 ‘ ‘ ‘ 100 200 300 400 500 600 700 900 so 100 150 200 250 Sample Rate (ksps) Samp‘e Rate (ksps) 900 12-bit Conversions, Norma‘ Bias 450 12-bit Conversions, Low Power Bias — VDD=36V ‘ ‘ ‘ ‘ ‘ — VDD=36V ‘ ‘ ‘ ‘ — van: 3v 44o — VDD=2 2V 35“ A 430 <( a="" 420="" 300="" ‘5="" 2="" 410="" 3="" u="" 400="" 750="" 3="" 2="" 390="" s="" 700="" 380="" 370="" 650="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" ‘="" 360="" ‘="" ‘="" ‘="" ‘="" 40="" 60="" so="" 100="" 120="" 140="" 160="" 180="" 200="" sample="" rate="" (ksps)="" 10="" 20="" ‘="" 30="" 40="" samp‘e="" rate="" (ksps)="">
Figure 4.6. Typical ADC0 Supply Current in Normal (always-on) Mode
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 33
Typical VOH (Low Drive Mode) 3.5 30 Typical VOH (High Drive Mode) l l l 11v 35 3.0 VlO = 3 6V we 7 3 av VlO = 2 7v we = 2 2v VlO = 1 7w w 2.5 7 m 7 m m E E 6 T: > 2 0 7 > 7 1 5 7 7 1-0 ; i ; , ; ; i i l l l , 0 5 10 15 20 25 o 2 4 a a 10 12 14 16 18 Load Current (mA) Load Current(mA) 1 3 Typical VOL (High Drive Mode) 1 8 Typical VOL (Low Drive Mode) - l l l l l l l l - l l l l 1.5 7 7 1 6 7 7 1.4 7 7 1 4 7 7 1 2 7 7 1.2 7 7 g 1.0 7 7 g 1.0 7 7 3 E g o a 7 7 g 0.3 7 7 o a 7 7 0.6 7 7 Q4 — , 0_4 — Vlo=3ev , _ — vlo=33v _ — V|O=27V 0.2 _ 7 02 —vlo=22v ’ _ vio=171v — vlo=171v D 0 0.0 ‘ ‘ —45 —40 —35 —30 —25 -20 -15 -10 -5 0 -25 -20 -15 -10 -5 0 Load Current (mA) Load Current (mA)
Figure 4.7. Typical VOH Curves
Figure 4.8. Typical VOL Curves
EFM8UB1 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 34
5. Typical Connection Diagrams
5.1 Power
The figure below shows a typical connection diagram for the power pins of the EFM8UB1 devices when the internal regulator used and
USB is connected (bus-powered).
EFM8UB1 Device
Voltage
Regulator
VREGIN
GND
4.7 µF and 0.1 µF bypass
capacitors required for
each power pin placed as
close to the pins as
possible.
3.3 V (out)
VDD
USB 5 V (in)
Figure 5.1. Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered)
EFM8UB1 Data Sheet
Typical Connection Diagrams
silabs.com | Building a more connected world. Rev. 1.3 | 35
The figure below shows a typical connection diagram for the power pins of the EFM8UB1 devices when the internal regulator used and
USB is connected (self-powered).
EFM8UB1 Device
Voltage
Regulator
VREGIN
GND
4.7 µF and 0.1 µF bypass
capacitors required for
each power pin placed as
close to the pins as
possible.
3.3 V (out)
VDD
3.6-5.25 V (in)
Figure 5.2. Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered)
The figure below shows a typical connection diagram for the power pins of the EFM8UB1 devices when the internal 5 V-to-3.3 V regula-
tor is not used.
EFM8UB1 Device
Voltage
Regulator
2.2-3.6 V (in)
GND
4.7 µF and 0.1 µF bypass
capacitors required for
each power pin placed as
close to the pins as
possible.
VREGIN
VDD
Figure 5.3. Connection Diagram with Voltage Regulator Not Used (Self-Powered)
EFM8UB1 Data Sheet
Typical Connection Diagrams
silabs.com | Building a more connected world. Rev. 1.3 | 36
5.2 USB
Figure 5.4 Bus-Powered Connection Diagram for USB Pins on page 37 shows a typical connection bus-powered diagram for the USB
pins of the EFM8UB1 devices including ESD protection diodes on the USB pins. Bypass capacitors on VREGIN and VDD are required
as discussed in 5.1 Power, but are not shown in the figure.
Note: The VBUS pin is not required as a sensing pin for proper operation in bus-powered configurations. Rather than using VBUS as a
sensing pin, it is recommended to use the VBUS pin only as a GPIO by clearing VBUSEN and VBUSIE to 0 in the USB0CF register. To
do this using the USB stack, set the device to use bus-powered mode.
EFM8UB1 Device
USB
D+
GND
VREGIN
D-
USB
Connector
VBUS
D+
Signal GND
D-
SP0503BAHT or
equivalent USB ESD
protection diodes
(Recommended)
Figure 5.4. Bus-Powered Connection Diagram for USB Pins
EFM8UB1 Data Sheet
Typical Connection Diagrams
silabs.com | Building a more connected world. Rev. 1.3 | 37
Figure 5.5 Self-Powered Connection Diagram for USB Pins on page 38 shows a typical connection self-powered diagram for the USB
pins of the EFM8UB1 devices including ESD protection diodes on the USB pins.
Note: There are two relevant restrictions on the VBUS pin voltage in this self-powered configuration. The first is the absolute maximum
voltage on the VBUS pin, which is defined as VIO + 2.5 V in Table 4.19 Absolute Maximum Ratings on page 30. The second is the
Input High Voltage (VIH) for VBUS to detect when the device is connected to a bus, which is defined as VIO – 0.6 V in 4.1.14 Port I/O.
For self-powered systems where VDD and VIO may be unpowered when VBUS is connected to 4.4 V to 5.5 V, a resistor divider (or
functionally-equivalent circuit) on VBUS is required to meet these specifications and ensure reliable device operation. In this case, the
current limitation of the resistor divider prevents overstress on the pin, even though the VIO + 2.5 V specification is not strictly met.
EFM8UB1 Device
USB
D+
GND
P3.1 / VBUS
D-
USB
Connector
VBUS
D+
Signal GND
D-
SP0503BAHT or
equivalent USB ESD
protection diodes
(Recommended)
22.1 kΩ
47.5 kΩ
Figure 5.5. Self-Powered Connection Diagram for USB Pins
EFM8UB1 Data Sheet
Typical Connection Diagrams
silabs.com | Building a more connected world. Rev. 1.3 | 38
5.3 Debug
The diagram below shows a typical connection diagram for the debug connections pins. The pin sharing resistors are only required if
the functionality on the C2D (a GPIO pin) and the C2CK (RSTb) is routed to external circuitry. For example, if the RSTb pin is connec-
ted to an external switch with debouncing filter or if the GPIO sharing with the C2D pin is connected to an external circuit, the pin shar-
ing resistors and connections to the debug adapter must be placed on the hardware. Otherwise, these components and connections
can be omitted.
For more information on debug connections, see the example schematics and information available in AN124: Pin Sharing Techniques
for the C2 Interface. Application notes can be found on the Silicon Labs website (http://www.silabs.com/8bit-appnotes) or in Simplicity
Studio.
EFM8UB1 Device External
System
(if pin sharing)
1 k 1 k
(if pin sharing)
C2CK
1 k 1 k
Debug Adapter
1 k
VDD
C2D
GND
Figure 5.6. Debug Connection Diagram
5.4 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN203: 8-bit MCU Printed
Circuit Board Design Notes contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs
website (www.silabs.com/8bit-appnotes).
EFM8UB1 Data Sheet
Typical Connection Diagrams
silabs.com | Building a more connected world. Rev. 1.3 | 39
Lcccccr JUUUUUL Wflflflflflf 4333::a
6. Pin Definitions
6.1 EFM8UB1x-QFN28 Pin Definitions
28 pin QFN
(Top View)
28
27
26
25
1
2
3
4
8
9
10
11
21
20
19
18
P0.1
P0.0
GND
D+
P3.1 / VBUS
RSTb / C2CK
P3.0 / C2D
P2.3
P1.1
P1.2
P1.3
P1.4
P0.2
P0.3
P0.4
P0.5
GND
24
23
22
P0.7
P1.0
12
13
14
P2.2
P2.1
P2.0
5
6
7
17
16
15
D-
VDD
VREGIN
P1.5
P1.6
P1.7
P0.6
28 pin QFN
(Top View)
Figure 6.1. EFM8UB1x-QFN28 Pinout
EFM8UB1 Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.3 | 40
Table 6.1. Pin Definitions for EFM8UB1x-QFN28
Pin
Number
Pin Name Description Crossbar Capability Additional Digital
Functions
Analog Functions
1 P0.1 Multifunction I/O Yes P0MAT.1
INT0.1
INT1.1
ADC0.1
CMP0P.1
CMP0N.1
AGND
2 P0.0 Multifunction I/O Yes P0MAT.0
INT0.0
INT1.0
ADC0.0
CMP0P.0
CMP0N.0
VREF
3 GND Ground
4 D+ USB Data Positive ADC0.28
5 D- USB Data Negative ADC0.29
6 VDD Supply Power Input /
5V Regulator Output
7 VREGIN 5V Regulator Input
8 P3.1 Multifunction I/O VBUS
9 RST /
C2CK
Active-low Reset /
C2 Debug Clock
10 P3.0 /
C2D
Multifunction I/O /
C2 Debug Data
11 P2.3 Multifunction I/O Yes P2MAT.3 ADC0.23
CMP1P.12
CMP1N.12
12 P2.2 Multifunction I/O Yes P2MAT.2 ADC0.22
CMP1P.11
CMP1N.11
13 P2.1 Multifunction I/O Yes P2MAT.1 ADC0.21
CMP1P.10
CMP1N.10
14 P2.0 Multifunction I/O Yes P2MAT.0 ADC0.20
CMP1P.9
CMP1N.9
15 P1.7 Multifunction I/O Yes P1MAT.7 ADC0.15
CMP1P.7
CMP1N.7
EFM8UB1 Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.3 | 41
Pin
Number
Pin Name Description Crossbar Capability Additional Digital
Functions
Analog Functions
16 P1.6 Multifunction I/O Yes P1MAT.6
I2C0_SCL
ADC0.14
CMP1P.6
CMP1N.6
17 P1.5 Multifunction I/O Yes P1MAT.5
I2C0_SDA
ADC0.13
CMP1P.5
CMP1N.5
18 P1.4 Multifunction I/O Yes P1MAT.4 ADC0.12
CMP1P.4
CMP1N.4
19 P1.3 Multifunction I/O Yes P1MAT.3 ADC0.11
CMP1P.3
CMP1N.3
20 P1.2 Multifunction I/O Yes P1MAT.2 ADC0.10
CMP1P.2
CMP1N.2
21 P1.1 Multifunction I/O Yes P1MAT.1 ADC0.9
CMP1P.1
CMP1N.1
CMP0P.10
CMP0N.10
22 P1.0 Multifunction I/O Yes P1MAT.0 ADC0.8
CMP1P.0
CMP1N.0
CMP0P.9
CMP0N.9
23 P0.7 Multifunction I/O Yes P0MAT.7
INT0.7
INT1.7
ADC0.7
CMP0P.7
CMP0N.7
24 P0.6 Multifunction I/O Yes P0MAT.6
CNVSTR
INT0.6
INT1.6
ADC0.6
CMP0P.6
CMP0N.6
25 P0.5 Multifunction I/O Yes P0MAT.5
INT0.5
INT1.5
UART0_RX
ADC0.5
CMP0P.5
CMP0N.5
EFM8UB1 Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.3 | 42
Pin
Number
Pin Name Description Crossbar Capability Additional Digital
Functions
Analog Functions
26 P0.4 Multifunction I/O Yes P0MAT.4
INT0.4
INT1.4
UART0_TX
ADC0.4
CMP0P.4
CMP0N.4
27 P0.3 Multifunction I/O Yes P0MAT.3
EXTCLK
INT0.3
INT1.3
ADC0.3
CMP0P.3
CMP0N.3
28 P0.2 Multifunction I/O Yes P0MAT.2
INT0.2
INT1.2
ADC0.2
CMP0P.2
CMP0N.2
Center GND Ground
EFM8UB1 Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.3 | 43
6.2 EFM8UB1x-QSOP24 Pin Definitions
P0.2
P0.1
P0.0
GND
D+
D-
VIO
VDD
VREGIN
P3.1 / VBUS
RSTb / C2CK
P2.0 / C2D
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
2
1
4
3
5
6
7
24 pin QSOP
(Top View)
8
9
10
11
12
23
24
21
22
20
19
18
17
16
15
14
13
Figure 6.2. EFM8UB1x-QSOP24 Pinout
Table 6.2. Pin Definitions for EFM8UB1x-QSOP24
Pin
Number
Pin Name Description Crossbar Capability Additional Digital
Functions
Analog Functions
1 P0.2 Multifunction I/O Yes P0MAT.2
INT0.2
INT1.2
ADC0.2
CMP0P.2
CMP0N.2
2 P0.1 Multifunction I/O Yes P0MAT.1
INT0.1
INT1.1
ADC0.1
CMP0P.1
CMP0N.1
AGND
EFM8UB1 Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.3 | 44
Pin
Number
Pin Name Description Crossbar Capability Additional Digital
Functions
Analog Functions
3 P0.0 Multifunction I/O Yes P0MAT.0
INT0.0
INT1.0
ADC0.0
CMP0P.0
CMP0N.0
VREF
4 GND Ground
5 D+ USB Data Positive ADC0.28
6 D- USB Data Negative ADC0.29
7 VIO I/O Power Input
8 VDD Supply Power Input /
5V Regulator Output
9 VREGIN 5V Regulator Input
10 P3.1 Multifunction I/O VBUS
11 RSTb /
C2CK
Active-low Reset /
C2 Debug Clock
12 P2.0 /
C2D
Multifunction I/O /
C2 Debug Data
13 P1.6 Multifunction I/O Yes P1MAT.6 ADC0.14
CMP1P.9
CMP1N.9
14 P1.5 Multifunction I/O Yes P1MAT.5 ADC0.13
CMP1P.7
CMP1N.7
15 P1.4 Multifunction I/O Yes P1MAT.4 ADC0.12
CMP1P.6
CMP1N.6
16 P1.3 Multifunction I/O Yes P1MAT.3 ADC0.11
CMP1P.5
CMP1N.5
17 P1.2 Multifunction I/O Yes P1MAT.2
I2C0_SCL
ADC0.10
CMP1P.4
CMP1N.4
18 P1.1 Multifunction I/O Yes P1MAT.1
I2C0_SDA
ADC0.9
CMP1P.3
CMP1N.3
EFM8UB1 Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.3 | 45
Pin
Number
Pin Name Description Crossbar Capability Additional Digital
Functions
Analog Functions
19 P1.0 Multifunction I/O Yes P1MAT.0 ADC0.8
CMP1P.2
CMP1N.2
20 P0.7 Multifunction I/O Yes P0MAT.7
INT0.7
INT1.7
ADC0.7
CMP1P.1
CMP1N.1
CMP0P.7
CMP0N.7
21 P0.6 Multifunction I/O Yes P0MAT.6
CNVSTR
INT0.6
INT1.6
ADC0.6
CMP1P.0
CMP1N.0
CMP0P.6
CMP0N.6
22 P0.5 Multifunction I/O Yes P0MAT.5
INT0.5
INT1.5
UART0_RX
ADC0.5
CMP0P.5
CMP0N.5
23 P0.4 Multifunction I/O Yes P0MAT.4
INT0.4
INT1.4
UART0_TX
ADC0.4
CMP0P.4
CMP0N.4
24 P0.3 Multifunction I/O Yes P0MAT.3
EXTCLK
INT0.3
INT1.3
ADC0.3
CMP0P.3
CMP0N.3
EFM8UB1 Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.3 | 46
Lccr JUUL Wflflf 433a
6.3 EFM8UB1x-QFN20 Pin Definitions
20 pin QFN
(Top View)
20
19
18
17
2
3
4
5
7
8
9
10
15
14
13
12
P0.1
P0.0
GND
D+
D-
VDD
VREGIN
P3.1 / VBUS
RSTb / C2CK
P2.0 / C2D
P0.6
P0.7
P1.0
P1.1
GND
P1.2
P0.2
P0.3
P0.4
P0.5
GND
1
6 11
16
Figure 6.3. EFM8UB1x-QFN20 Pinout
Table 6.3. Pin Definitions for EFM8UB1x-QFN20
Pin
Number
Pin Name Description Crossbar Capability Additional Digital
Functions
Analog Functions
1 P0.1 Multifunction I/O Yes P0MAT.1
INT0.1
INT1.1
ADC0.1
CMP0P.1
CMP0N.1
AGND
2 P0.0 Multifunction I/O Yes P0MAT.0
INT0.0
INT1.0
ADC0.0
CMP0P.0
CMP0N.0
VREF
3 GND Ground
EFM8UB1 Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.3 | 47
Pin
Number
Pin Name Description Crossbar Capability Additional Digital
Functions
Analog Functions
4 D+ USB Data Positive ADC0.28
5 D- USB Data Negative ADC0.29
6 VDD Supply Power Input /
5V Regulator Output
7 VREGIN 5V Regulator Input
8 P3.1 Multifunction I/O VBUS
9 RST /
C2CK
Active-low Reset /
C2 Debug Clock
10 P2.0 /
C2D
Multifunction I/O /
C2 Debug Data
11 P1.2 Multifunction I/O Yes P1MAT.2
I2C0_SCL
ADC0.10
CMP1P.4
CMP1N.4
12 GND Ground
13 P1.1 Multifunction I/O Yes P1MAT.1
I2C0_SDA
ADC0.9
CMP1P.3
CMP1N.3
14 P1.0 Multifunction I/O Yes P1MAT.0 ADC0.8
CMP1P.2
CMP1N.2
15 P0.7 Multifunction I/O Yes P0MAT.7
INT0.7
INT1.7
ADC0.7
CMP1P.1
CMP1N.1
CMP0P.7
CMP0N.7
16 P0.6 Multifunction I/O Yes P0MAT.6
CNVSTR
INT0.6
INT1.6
ADC0.6
CMP1P.0
CMP1N.0
CMP0P.6
CMP0N.6
17 P0.5 Multifunction I/O Yes P0MAT.5
INT0.5
INT1.5
UART0_RX
ADC0.5
CMP0P.5
CMP0N.5
EFM8UB1 Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.3 | 48
Pin
Number
Pin Name Description Crossbar Capability Additional Digital
Functions
Analog Functions
18 P0.4 Multifunction I/O Yes P0MAT.4
INT0.4
INT1.4
UART0_TX
ADC0.4
CMP0P.4
CMP0N.4
19 P0.3 Multifunction I/O Yes P0MAT.3
EXTCLK
INT0.3
INT1.3
ADC0.3
CMP0P.3
CMP0N.3
20 P0.2 Multifunction I/O Yes P0MAT.2
INT0.2
INT1.2
ADC0.2
CMP0P.2
CMP0N.2
Center GND Ground
EFM8UB1 Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.3 | 49
m E :1 ti] - I It ... . "70 mm 1mg“ . Plnrl ldenufler Opflan 1 Opus" 2 Ooh'on 2 Opllon 3 Edge Expand Edge Pun—Back Option I \rnqular comr 0mm Scum Irregular Edge
7. QFN28 Package Specifications
7.1 QFN28 Package Dimensions
Figure 7.1. QFN28 Package Drawing
Table 7.1. QFN28 Package Dimensions
Dimension Min Typ Max
A 0.70 0.75 0.80
A1 0.00 — 0.05
A3 0.20 REF
b 0.20 0.25 0.30
D 5.00 BSC
D2 3.15 3.25 3.35
e 0.50 BSC
E 5.00 BSC
E2 3.15 3.25 3.35
L 0.45 0.55 0.65
aaa 0.10
bbb 0.10
ddd 0.05
EFM8UB1 Data Sheet
QFN28 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 50
Dimension Min Typ Max
eee 0.08
Z 0.44
Y 0.18
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220 except for custom features D2, E2, L, Z, and Y which are toleranced per suppli-
er designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
EFM8UB1 Data Sheet
QFN28 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 51
wgggggm +f JUUUUUE \ QDDDDDm DDDUDE E
7.2 QFN28 PCB Land Pattern
X1
X2
Y2
Y1
C2
C1
E
C0.35
Figure 7.2. QFN28 PCB Land Pattern Drawing
Table 7.2. QFN28 PCB Land Pattern Dimensions
Dimension Min Max
C1 4.80
C2 4.80
E 0.50
X1 0.30
X2 3.35
Y1 0.95
Y2 3.35
EFM8UB1 Data Sheet
QFN28 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 52
Dimension Min Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2 x 2 array of 1.2 mm square openings on a 1.5 mm pitch should be used for the center pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
7.3 QFN28 Package Marking
PPPPPPPP
TTTTTT
YYWW #
EFM8
Figure 7.3. QFN28 Package Marking
The package marking consists of:
PPPPPPPP – The part number designation.
TTTTTT – A trace or manufacturing code.
YY – The last 2 digits of the assembly year.
WW – The 2-digit workweek when the device was assembled.
# – The device revision (A, B, etc.).
EFM8UB1 Data Sheet
QFN28 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 53
(2x) E1 (ex 12 Ups) I 0- a 7 7 ‘ 7 7 [E] O ‘ ‘ w wwmm H L “mama T E gmafiw Seufln Plane 6 Dem“ 1 _F \ f—i'L ‘ \ fi Deta‘l l
8. QSOP24 Package Specifications
8.1 Package Dimensions
Figure 8.1. Package Drawing
Table 8.1. Package Dimensions
Dimension Min Typ Max
A — 1.75
A1 0.10 — 0.25
b 0.20 — 0.30
c 0.10 — 0.25
D 8.65 BSC
E 6.00 BSC
E1 3.90 BSC
e 0.635 BSC
L 0.40 — 1.27
EFM8UB1 Data Sheet
QSOP24 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 54
Dimension Min Typ Max
theta 0º — 8º
aaa 0.20
bbb 0.18
ccc 0.10
ddd 0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-137, variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
EFM8UB1 Data Sheet
QSOP24 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 55
4% Egg E EEEEEEEE
8.2 PCB Land Pattern
Figure 8.2. PCB Land Pattern Drawing
Table 8.2. PCB Land Pattern Dimensions
Dimension Min Max
C 5.20 5.30
E 0.635 BSC
X 0.30 0.40
Y 1.50 1.60
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
EFM8UB1 Data Sheet
QSOP24 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 56
8.3 Package Marking
PPPPPPPP #
TTTTTTYYWW
EFM8
Figure 8.3. Package Marking
The package marking consists of:
PPPPPPPP – The part number designation.
TTTTTT – A trace or manufacturing code.
YY – The last 2 digits of the assembly year.
WW – The 2-digit workweek when the device was assembled.
# – The device revision (A, B, etc.).
EFM8UB1 Data Sheet
QSOP24 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 57
2>< é».="" pin“="" \den'hfy:="" loser="" mark="" e="" \o="" coo="" c="" i="" r="" 4="" m="" —="" —="" ':'="" v_|_l="" |="" .="" i="" l="" m="" 2x="" "b”="" "="" "="" deta‘l:="" b="">‘\ = ( L K Baal
9. QFN20 Package Specifications
9.1 QFN20 Package Dimensions
Figure 9.1. QFN20 Package Drawing
Table 9.1. QFN20 Package Dimensions
Dimension Min Typ Max
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.18 0.25 0.30
c 0.25 0.30 0.35
D 3.00 BSC
D2 1.6 1.70 1.80
e 0.50 BSC
E 3.00 BSC
EFM8UB1 Data Sheet
QFN20 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 58
Dimension Min Typ Max
E2 1.60 1.70 1.80
f 2.50 BSC
L 0.30 0.40 0.50
K 0.25 REF
R 0.09 0.125 0.15
aaa 0.15
bbb 0.10
ccc 0.10
ddd 0.05
eee 0.08
fff 0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. The drawing complies with JEDEC MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
EFM8UB1 Data Sheet
QFN20 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 59
Cl C3 4Y X3 + + + __ E + + Y2 f X1 Y1
9.2 QFN20 PCB Land Pattern
Figure 9.2. QFN20 PCB Land Pattern Drawing
Table 9.2. QFN20 PCB Land Pattern Dimensions
Dimension Min Max
C1 3.10
C2 3.10
C3 2.50
C4 2.50
E 0.50
X1 0.30
X2 0.25 0.35
X3 1.80
Y1 0.90
Y2 0.25 0.35
Y3 1.80
EFM8UB1 Data Sheet
QFN20 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 60
Dimension Min Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
8. A 2 x 2 array of 0.75 mm openings on a 0.95 mm pitch should be used for the center pad to assure proper paste volume.
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
9.3 QFN20 Package Marking
PPPP
PPPP
TTTTTT
YYWW #
Figure 9.3. QFN20 Package Marking
The package marking consists of:
PPPPPPPP – The part number designation.
TTTTTT – A trace or manufacturing code.
YY – The last 2 digits of the assembly year.
WW – The 2-digit workweek when the device was assembled.
# – The device revision (A, B, etc.).
EFM8UB1 Data Sheet
QFN20 Package Specifications
silabs.com | Building a more connected world. Rev. 1.3 | 61
10. Revision History
Revision 1.3
October 20th, 2017
Updated Figure 3.1 Detailed EFM8UB1 Block Diagram on page 6 to show 1024 bytes of XRAM in the core, since the 1024 bytes of
USB FIFO RAM are documented in the USB block.
Updated 3.1 Introduction to mention all device documentation.
Updated text and figures in 5.1 Power to remove mention of the VBUS pin.
Updated Figure 5.2 Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered) on page 36 to remove
VBUS pin.
Updated the title of Figure 5.3 Connection Diagram with Voltage Regulator Not Used (Self-Powered) on page 36 to include "Self-
Powered".
Updated 5.2 USB to add a note regarding VBUS.
Updated the maximum Voltage Reference Range specification to reference VDD instead of VIO in 4.1.8 ADC.
Updated the maximum Input Range (CP+ or CP-) specification to reference VDD instead of VIO in 4.1.13 Comparators.
Updated Weak Pull-Up Current specification condition to refer to VIO instead of VDD in 4.1.14 Port I/O.
Added Z and Y dimensions and updated Note 3 in Table 7.1 QFN28 Package Dimensions on page 50.
Updated the QFN20 and QSOP24 C2D pins to not available on the crossbar in 6.3 EFM8UB1x-QFN20 Pin Definitions and
6.2 EFM8UB1x-QSOP24 Pin Definitions.
Revision 1.2
March 15th, 2017
Updated Figure 5.6 Debug Connection Diagram on page 39 to move the pull-up resistor on C2D / RSTb to after the series resistor
instead of before.
Added a reference to AN945: EFM8 Factory Bootloader User Guide in 3.10 Bootloader.
Added bootloader pinout information to 3.10 Bootloader.
Added a note to 3.1 Introduction referencing the Reference Manual.
Specified the sizes of the SMBus and I2CSLAVE transmit and receive FIFOs.
Added a note to Table 4.2 Power Consumption on page 17 providing more information about the Comparator Reference specifica-
tion.
Adjusted the Normal Mode and Idle Mode typical and maximum numbers in Table 4.2 Power Consumption on page 17 for FSYSCLK
= 48 MHz and FSYSCLK = 24.5 MHz.
Added a note linking to the Typical VOH and VOL Performance graphs in 4.1.14 Port I/O.
Added 4.1.11 1.8 V Internal LDO Voltage Regulator.
Added CRC Calculation Time to 4.1.4 Flash Memory.
Added specifications for 4.1.16 SMBus.
Added Thermal Resistance (Junction to Case) and Thermal Characterization Parameter (Junction to Top) for QFN20 and QFN28
packages to 4.2 Thermal Conditions.
Updated 5.2 USB typical connections chapter to add a note and resistor divider for self-powered configurations.
Corrected the application note number for AN124: Pin Sharing Techniques for the C2 Interface in 5.3 Debug.
Adjusted D, E, and aaa in QFN28 Package Dimensions.
Revision 1.1
December 16, 2015
Updated 3.2 Power to properly reflect that a comparator falling edge wakes the device from Suspend and Snooze.
Added Note 4 to Table 4.1 Recommended Operating Conditions on page 16.
Added 5.3 Debug.
EFM8UB1 Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 1.3 | 62
Revision 1.0
Updated any TBD numbers in 4.1 Electrical Characteristics and adjusted various specifications.
Updated VOH and VOL graphs in Figure 4.7 Typical VOH Curves on page 34 and Figure 4.8 Typical VOL Curves on page 34 and
updated the VOH and VOL specifications in Table 4.14 Port I/O on page 26.
Added more information to 3.10 Bootloader.
Updated part numbers to Revision C.
Revision 0.3
Updated QFN20 packaging and landing diagram dimensions.
Updated QFN28 D and E minimum value.
Updated some characterization TBD values.
Added maximum allowable voltages on D+ and D- and added VBUS / P3.1 to the standard I/O row in Table 4.19 Absolute Maximum
Ratings on page 30.
Added a diagram to 5.1 Power for cases when the internal 5 V-to-3.3 V regulator is not used.
Updated the 5 V-to-3.3 V regulator Electrical Characteristics table.
Added Stop mode to the Power Modes table in 3.2 Power.
Revision 0.2
Initial release.
EFM8UB1 Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 1.3 | 63
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