HV2605, HV2705 Datasheet by Microchip Technology

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6‘ MICRDCHIP
2017 Microchip Technology Inc. DS20005498A-page 1
Features
16-channel High-voltage Analog Switch
Low Harmonic Distortion
Integrated Bleed Resistors on the Outputs for
HV2705
3.3V Input Logic Level Compatible
–60 dB typical OFF-isolation at 5 MHz
20 MHz Data Shift Clock Frequency
10 µA Low-quiescent Power Dissipation
Low Parasitic Capacitance
DC to 50 MHz Small-signal Frequency Response
CMOS logic Circuitry for Low Power
Cascadable Serial Data Register with Latches
Flexible Operating Supply Voltages
Applications
Medical Ultrasound Imaging
Non-destructive Metal Flaw Detection
Piezoelectric Transducer Drivers
Optical MEMS Modules
Description
The HV2605 and HV2705 are 16-channel low
harmonic distortion high-voltage analog switch inte-
grated circuits (ICs). These devices are designed for
applications requiring high-voltage switching controlled
by low-voltage control signals, such as medical ultra-
sound imaging and other piezoelectric transducer driv-
ers. The HV2705 has integrated bleed resistors which
eliminate voltage build-up on capacitive loads such as
piezoelectric transducers.
These ICs shift input data into a 16-bit Shift register that
can then be retained in a 16-bit latch. To reduce any
possible clock feed-through noise, the latch enable bar
should be left high until all bits are clocked in. Data are
clocked in during the rising edge of the clock. This
device combines high-voltage, bilateral DMOS
switches and low-power CMOS logic to provide
efficient control of high-voltage analog signals.
The device is suitable for various combinations of high-
voltage supplies, e.g., VPP/VNN: +40V/–160V,
+100V/–100V and +160V/–40V.
Package Types
See Table 2-1 and Table 2-2 for pin information.
42-Ball Bumped Die
(Top view)
1
2
3
8
9
1012
13
4
5
6
7
11
18 17 16 15 14
25
26
21
22
23
24
19
20
41
42
33
34
39
40
31
32
37
38
29
30
35
36
27
28
48-lead LQFP
(Top view)
1
48
HV2605/HV2705
16-Channel Low Harmonic Distortion High-Voltage Analog Switches
I | Ill | o I | Ill | o _E|$|_m|-.lfilfil _ _ _ _ _o 0 O 0
HV2605/HV2705
DS20005498A-page 2 2017 Microchip Technology Inc.
Functional Block Diagram
D
LE
CLR
Latches
Level
Shifters
Output
Switches
SW0
SW1
SW2
SW14
SW15
16-Bit
Shift
Register
RGND
VPP
VNN
CLR
LE
VDD GND
D
LE
CLR
D
LE
CLR
D
LE
CLR
D
LE
CLR
DOUT
CLK
DIN
Bleed
Resistors
HV2705 only
DD PP NN \H DD VDD \L VDD 5K3 VNN VPP Note 1: Powerrup/powerrdown sequence ‘5 arbxlrary excep‘ GND must be powered up firs: and powered down \asl.
2017 Microchip Technology Inc. DS20005498A-page 3
HV2605/HV2705
1.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Logic Supply, VDD ..................................................................................................................................... –0.5V to +7V
Differential Supply, VPP–VNN ................................................................................................................................. 220V
Positive Supply, VPP ...................................................................................................................... –0.5V to VNN +200V
Negative Supply, VNN .............................................................................................................................+0.5V to –200V
Logic Input Voltage .......................................................................................................................... –0.5V to VDD +0.3V
Analog Signal Range ..................................................................................................................................... VNN to VPP
Peak Analog Signal Current/Channel ........................................................................................................................ 3A
Storage Temperature, TS ....................................................................................................................... –65°C to 150°C
Power Dissipation:
42-Ball Bumped Die .................................................................................................................................... 1.5W
48-lead LQFP .................................................................................................................................................. 1W
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Sym. Min. Typ. Max. Unit Conditions
Logic Power Supply Voltage VDD 3 5.5 VNote 1, Note 3
Positive High-voltage Supply VPP 40 — VNN+200V VNote 1, Note 3
Negative High-voltage Supply VNN –40 –160 VNote 1, Note 3
High-level Input Voltage VIH 0.9 VDD VDD V
Low-level Input Voltage VIL 0 0.1 VDD V
Analog Signal Voltage Peak-to-peak VSIG VNN +10V VPP–10V VNote 2
Note 1: Power-up/power-down sequence is arbitrary except GND must be powered up first and powered down last.
2: VSIG must be VNN and VPP or floating during power-up/power-down transition.
3: Rise and fall times of power supplies VDD, VPP and VNN should not be less than 1 millisecond.
HV2605/HV2705
DS20005498A-page 4 2017 Microchip Technology Inc.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over recommended operating conditions unless otherwise noted.
Parameter
Sym.
0°C 25°C 70°C
Unit
Conditions
Min. Max. Min. Typ. Max. Min. Max.
Small Signal Switch
ON-resistance RONS
30 26 38 48 ISIG = 5 mA VPP = +40V
VNN = –160V
25 22 27 32 ISIG = 200 mA
25 22 27 30 ISIG = 5 mA VPP = +100V
VNN= –100V
18 18 24 27 ISIG = 200 mA
23 20 25 30 ISIG = 5 mA VPP = +160V
VNN = –40V
22 16 25 27 ISIG = 200 mA
Small Signal Switch
ON-resistance Matching RONS 20 — 5 20 20 %ISIG = 5 mA, VPP = +100V,
VNN = –100V
Large Signal Switch
ON-resistance RONL 15 — — VSIG = VPP–10V, ISIG = 1A
Output Bleed Resistor
(HV2705 only) RINT 20 35 50 — kOutput Switch to RGND
IRINT = 0.5 mA
Switch OFF Leakage
per Switch ISOL — 5 — 1 10 15 µA
VSIG = VPP–10V and
VNN+10V (See Section 3.1
“Test Circuits”.)
DC Offset Switch OFF
VOS
300 100 300 300 mV HV2605:100 k load
HV2705: No load
(See Section 3.1 “Test Cir-
cuits”.)
DC Offset Switch ON 500 100 500 500 mV
Quiescent VPP Supply
Current IPPQ 10 50 µA All switches off
Quiescent VNN Supply
Current INNQ –10 –50 µA All switches off
Quiescent VPP Supply
Current IPPQ 10 50 µA All switches on, ISW = 5 mA
Quiescent VNN Supply
Current INNQ –10 –50 µA All switches on, ISW = 5 mA
Switch Output Peak
Current ISW — 3 — 3 2 — 2 A VSIG duty cycle < 0.1%
Output Switching
Frequency fSW — — 50 kHz Duty cycle = 50%
Average VPP Supply Current IPP
6.5 — — 7 8 mA VPP = +40V
VNN = –160V 50 kHz
output
switching
frequency
with no load
4 5.5 5.5 mA VPP = +100V
VNN = –100V
— 4 — 5 — 5.5 mA VPP = +160V
VNN = –40V
Average VNN Supply Current INN
6.5 — — 7 8 mA VPP = +40V
VNN = –160V 50 kHz
output
switching
frequency
with no load
— 4 — 5 — 5.5 mA VPP = +100V
VNN = –100V
— 4 — 5 — 5.5 mA VPP = +160V
VNN = –40V
Average VDD Supply Current IDD — 4 — 4 — 4 mA fCLK = 5 MHz, VDD = 5V
Quiescent VDD Supply
Current IDDQ 10 — — 10 10 µA All logic inputs are static.
VDD r ‘I CLOAD lWCLR
2017 Microchip Technology Inc. DS20005498A-page 5
HV2605/HV2705
Data Out Source Current ISOR 0.45 0.45 0.7 0.4 mA VOUT = VDD–0.7V
Data Out Sink Current ISINK 0.45 0.45 0.7 0.4 mA VOUT = 0.7V
Logic Input
Capacitance CIN 10 — — 10 10 pF
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: VDD = 5V, tr = tf 5 ns, 50% duty cycle and CLOAD = 20 pF unless otherwise noted.
Parameter
Sym.
0°C 25°C 70°C
Unit
Conditions
Min. Max. Min. Typ. Max. Min. Max.
Set-up Time before Latch
Enable Rises tSD 25 25 25 ns
Time Width of LE tWLE
56 56 56 ns VDD = 3V
12 12 12 ns VDD = 5V
Clock Delay Time
to Data Out tDO
50 100 50 78 100 50 100 ns VDD = 3V
15 40 15 30 40 15 40 ns VDD = 5V
Time Width of CLR tWCLR 55 55 55 ns
Set-up Time Data to Clock tSU
21 21 21 ns VDD = 3V
7 7 7 ns VDD = 5V
Hold Time Data from
Clock tH2 2 2 ns VDD = 3V or 5V
Clock Frequency fCLK
8 — 8 — 8 MHz VDD = 3V
20 — — 20 20 MHz VDD = 5V
Clock Rise and Fall Times tr, tf50 — — 50 50 ns
Turn ON Time TON 5 — 5 — 5 µs
VSIG = VPP–10V,
RLOAD = 10 k
(See Section 3.1 “Test
Circuits”.)
Turn OFF Time TOFF 5 — 5 — 5 µs
VSIG = VPP–10V,
RLOAD = 10 k
(See Section 3.1 “Test
Circuits”.)
Maximum VSIG Slew Rate dv/dt
20 — — 20 20 V/ns VPP = +40V,
VNN = –160V
20 — — 20 20 V/ns VPP = +100V,
VNN = –100V
20 — — 20 20 V/ns VPP = +160V,
VNN = –40V
OFF Isolation KO
–30 –30 –33 –30 dB
f = 5 MHz, 1 k//15 pF load
(See Section 3.1 “Test
Circuits”.)
–58 –58 –58 dB
f = 5 MHz, 50 load
(See Section 3.1 “Test
Circuits”.)
Switch Crosstalk KCR –60 –60 –70 –60 dB
f = 5 MHz, 50 load
(See Section 3.1 “Test
Circuits”.)
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Over recommended operating conditions unless otherwise noted.
Parameter
Sym.
0°C 25°C 70°C
Unit
Conditions
Min. Max. Min. Typ. Max. Min. Max.
CLOAD
HV2605/HV2705
DS20005498A-page 6 2017 Microchip Technology Inc.
Output Switch Isolation
Diode Current IID 300 300 300 mA
300 ns pulse width,
2% duty cycle
(See Section 3.1 “Test
Circuits”.)
OFF Capacitance
SW to GND CSG(OFF) 15 10 15 15 pF 0V, f = 1 MHz
ON Capacitance
SW to GND CSG(ON) 18 13 18 18 pF 0V, f = 1 MHz
Output Voltage Spike
+VSPK — — —
150
mV VPP = +40V,
VNN = –160V,
RLOAD = 50
(See Section 3.1 “Test
Circuits”.)
–VSPK mV
+VSPK — — —
150
mV VPP = +100V,
VNN = –100V,
RLOAD = 50
(See Section 3.1 “Test
Circuits”.)
–VSPK — — mV
+VSPK — — —
150
mV VPP = +160V,
VNN = –40V,
RLOAD = 50
(See Section 3.1 “Test
Circuits”.)
–VSPK mV
Charge Injection QC
820 pC
VPP = +40V,
VNN = –160V,
VSIG = 0V
(See Section 3.1 “Test
Circuits”.)
600 pC
VPP = +100V,
VNN = –100V,
VSIG = 0V
(See Section 3.1 “Test
Circuits”.)
350 pC
VPP = +160V,
VNN = –40V,
VSIG = 0V
(See Section 3.1 “Test
Circuits”.)
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: VDD = 5V, tr = tf 5 ns, 50% duty cycle and CLOAD = 20 pF unless otherwise noted.
Parameter
Sym.
0°C 25°C 70°C
Unit
Conditions
Min. Max. Min. Typ. Max. Min. Max.
2017 Microchip Technology Inc. DS20005498A-page 7
HV2605/HV2705
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, for all specifications TA = TJ = +25°C.
Parameter Sym. Min. Typ. Max. Unit Conditions
TEMPERATURE RANGE
Operating Ambient Temperature TA0 70 °C
Storage Temperature TS–65 150 °C
PACKAGE THERMAL RESITANCE
48-lead LQFP θJA 52 °C/W Note 1
Note 1: Mounted on an FR-4 board, 25 mm x 25 mm x 1.57 mm
Timing Waveforms
DATA IN
DIN
LE
CLOCK
CLK
DATA OUT
DOUT
OFF
VOUT
(typ)
ON
CLR
50% 50%
50% 50%
t
WLE
t
SD
t
SU
t
h
50%
50%
t
OFF
50%
t
DO
DO
t
ON
t
WCL
D
N+1
D
N
D
N-1
50%50%
90%
10%
HV2605/HV2705
DS20005498A-page 8 2017 Microchip Technology Inc.
2.0 PIN DESCRIPTION
The description of pins in the 42-ball bumped die and
48-lead LQFP packages are listed on Ta b l e 2-1 and
Table 2-2, respectively. The locations of the pads/balls
are listed in Package Types.
TABLE 2-1: 42-BALL BUMPED DIE PIN FUNCTION TABLE
Pin Number HV2605
Pin Name
HV2705
Pin Name Description
1NC No connection
RGND Ground for bleed resistor
2VPP VPP Positive supply voltage
3VNN VNN Negative supply voltage
4DOUT DOUT Data out logic output
5CLR CLR Latch clear logic input
6CLK CLK Clock logic input for Shift register
7 GND GND Ground
8SW15A SW15A Analog Switch 15 Terminal A
9SW15B SW15B Analog Switch 15 Terminal B
10 LE LE Latch enable logic input, low active
11 VDD VDD Logic supply voltage
12 SW0A SW0A Analog Switch 0 Terminal A
13 SW0B SW0B Analog Switch 0 Terminal B
14 SW14A SW14A Analog Switch 14 Terminal A
15 SW14B SW14B Analog Switch 14 Terminal B
16 DIN DIN Data in logic input
17 SW1A SW1A Analog Switch 1 Terminal A
18 SW1B SW1B Analog Switch 1 Terminal B
19 SW13A SW13A Analog Switch 13 Terminal A
20 SW13B SW13B Analog Switch 13 Terminal B
21 SW2A SW2A Analog Switch 2 Terminal A
22 SW2B SW2B Analog Switch 2 Terminal B
23 SW12A SW12A Analog Switch 12 Terminal A
24 SW12B SW12B Analog Switch 12 Terminal B
25 SW3A SW3A Analog Switch 3 Terminal A
26 SW3B SW3B Analog Switch 3 Terminal B
27 SW11A SW11A Analog Switch 11 Terminal A
28 SW11B SW11B Analog Switch 11 Terminal B
29 SW9B SW9B Analog Switch 9 Terminal B
30 SW8B SW8B Analog Switch 8 Terminal B
31 SW7A SW7A Analog Switch 7 Terminal A
32 SW6A SW6A Analog Switch 6 Terminal A
33 SW4A SW4A Analog Switch 4 Terminal A
34 SW4B SW4B Analog Switch 4 Terminal B
35 SW10B SW10B Analog Switch 10 Terminal B
36 SW10A SW10A Analog Switch 10 Terminal A
37 SW9A SW9A Analog Switch 9 Terminal A
38 SW8A SW8A Analog Switch 8 terminal A
2017 Microchip Technology Inc. DS20005498A-page 9
HV2605/HV2705
39 SW7B SW7B Analog Switch 7 Terminal B
40 SW6B SW6B Analog Switch 6 Terminal B
41 SW5B SW5B Analog Switch 5 Terminal B
42 SW5A SW5A Analog Switch 5 Terminal A
TABLE 2-1: 42-BALL BUMPED DIE PIN FUNCTION TABLE
Pin Number HV2605
Pin Name
HV2705
Pin Name Description
TABLE 2-2: 48-LEAD LQFP PIN FUNCTION TABLE
Pin Number HV2605
Pin Name
HV2705
Pin Name Description
1NC NC No connection
2NC NC No connection
3SW4B SW4B Analog Switch 4 Terminal B
4SW4A SW4A Analog Switch 4 Terminal A
5SW3B SW3B Analog Switch 3 Terminal B
6SW3A SW3A Analog Switch 3 Terminal A
7SW2B SW2B Analog Switch 2 Terminal B
8SW2A SW2A Analog Switch 2 Terminal A
9SW1B SW1B Analog Switch 1 Terminal B
10 SW1A SW1A Analog Switch 1 Terminal A
11 SW0B SW0B Analog Switch 0 Terminal B
12 SW0A SW0A Analog Switch 0 Terminal A
13 VNN VNN Negative supply voltage
14 NC NC No connection
15 VPP VPP Positive supply voltage
16 NC NC No connection
17 GND GND Ground
18 VDD VDD Logic supply voltage
19 DIN DIN Data in logic input
20 CLK CLK Clock logic input for Shift register
21 LE LE Latch-enable logic input, low active
22 CLR CLR Latch clear logic input
23 DOUT DOUT Data out logic output
24 NC No connection
RGND Ground for bleed resistor
25 SW15B SW15B Analog Switch 15 Terminal B
26 SW15A SW15A Analog Switch 15 Terminal A
27 SW14B SW14B Analog Switch 14 Terminal B
28 SW14A SW14A Analog Switch 14 Terminal A
29 SW13B SW13B Analog Switch 13 Terminal B
30 SW13A SW13A Analog Switch 13 Terminal A
31 SW12B SW12B Analog Switch 12 Terminal B
32 SW12A SW12A Analog Switch 12 Terminal A
33 SW11B SW11B Analog Switch 11 Terminal B
34 SW11A SW11A Analog Switch 11 Terminal A
HV2605/HV2705
DS20005498A-page 10 2017 Microchip Technology Inc.
35 NC NC No connection
36 NC NC No connection
37 SW10B SW10B Analog Switch 10 Terminal B
38 SW10A SW10A Analog Switch 10 Terminal A
39 SW9B SW9B Analog Switch 9 Terminal B
40 SW9A SW9A Analog Switch 9 Terminal A
41 SW8B SW8B Analog Switch 8 Terminal B
42 SW8A SW8A Analog Switch 8 Terminal A
43 SW7B SW7B Analog Switch 7 Terminal B
44 SW7A SW7A Analog Switch 7 Terminal A
45 SW6B SW6B Analog Switch 6 Terminal B
46 SW6A SW6A Analog Switch 6 Terminal A
47 SW5B SW5B Analog Switch 5 Terminal B
48 SW5A SW5A Analog Switch 5 Terminal A
TABLE 2-2: 48-LEAD LQFP PIN FUNCTION TABLE
Pin Number HV2605
Pin Name
HV2705
Pin Name Description
H 1 )— U g.— S M \ f if : in ”J |
2017 Microchip Technology Inc. DS20005498A-page 11
HV2605/HV2705
3.0 FUNCTIONAL DESCRIPTION
3.1 Test Circuits
Figure 3-1 to Figure 3-8 show the test circuits for
HV2605/HV2705.
V
PP
-10V
RGND
Open
V
PP
5V
V
NN
VPP
VNN
VDD
Open
I
SOL
GND
FIGURE 3-1: Switch Off Leakage per
Switch.
FIGURE 3-2: Switch DC Offset.
RGND
5V
GND
V
PP
-10V
10kΩ
V
OUT
R
LOAD
V
PP
V
NN
VPP
VNN
VDD
FIGURE 3-3: TON/TOFF Test Circuit.
RGND
K
O
= 20Log V
OUT
V
IN
V
IN
= 10V
P-P
@5MHz
5V
GND
V
OUT
R
LOAD
V
PP
V
NN
VPP
VNN
VDD
FIGURE 3-4: Off Isolation.
RGND
I
ID
5V
GND
V
NN
V
SIG
V
PP
V
NN
VPP
VNN
VDD
FIGURE 3-5: Output Switch Isolation
Diode Current.
RGND
V
IN
= 10V
P-P
@5MHz
NC
5V
GND
50Ω
50Ω
V
PP
V
NN
VPP
VNN
VDD
K
CR
= 20Log V
OUT
V
IN
FIGURE 3-6: Switch Crosstalk.
RGND
Q = 1000pF x ΔV
OUT
5V
GND
V
PP
V
NN
VPP
VNN
VDD
V
OUT
ΔV
OUT
1000pF
V
SIG
HV2605/HV2705
DS20005498A-page 12 2017 Microchip Technology Inc.
FIGURE 3-7: Charge Injection.
RGND
5V
GND
V
OUT
1kΩ
R
LOAD
50Ω
+V
SPK
–V
SPK
V
PP
V
NN
VPP
VNN
VDD
FIGURE 3-8: Output Voltage Spike.
2017 Microchip Technology Inc. DS20005498A-page 13
HV2605/HV2705
TABLE 3-1: TRUTH FUNCTION TABLE
D0 D1 ... D7 D8 ... D15 LE CLR SW0 SW1 ... SW7 SW8 ... SW15
L —
...
— —
...
L L OFF
...
— —
...
H — — — — L L ON — — — —
— L — L L — OFF — —
H L L ON — —
— — — — L L — — — —
— — — — L L — — — —
— — L L L — — OFF — —
— — H L L — — ON — —
— — L L L — — OFF
— — H L L — — ON
— — — — L L — — — —
— — — — L L — — — —
— — — — L L — — — —
— — — — L L — — — —
— — — — L L L — — OFF
— — — — H L L — — ON
X X X X X X X H L HOLD PREVIOUS STATE
X X X X X X X X H ALL SWITCHES OFF
Note 1: The 16 switches operate independently.
2: Serial data is clocked in on the low-to-high transition of the clock.
3: All 16 switches go to a state retaining their latched condition at the rising edge of LE.
When LE is low, the Shift registers data flow through the latch.
4: DOUT is high when data in the Shift register 15 is high.
5: Shift registers clocking has no effect on the switch states if LE is high.
6: The CLR clear input overrides all other inputs.
4Zrball Bumped D‘e EXamp‘e Examp‘e NN
HV2605/HV2705
DS20005498A-page 14 2017 Microchip Technology Inc.
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
Legend: XX...X Product Code or Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
3
e
3
e
42-ball Bumped Die Example
XXXXX
XXXXXXX
YYWWNNN
BD
HV2605
1750343
BD
HV2705
1732674
Example
e3 e3e3
48-lead LQFP Example
NNN
YYWW
XXXXXX
XXXXXX
e3
343
1750
2605FG
HV
e3
Example
426
1712
2705FG
HV
e3
42-Ball Bumped Die Package Outline (BD)
5.29x5.30mm body, 1.0mm height (max), 0.52 / 0.60mm pitch
Symbol A A1 A2 b D D1 E E1 E2 e e1
Dimension
(mm)
MIN 0.90.21 0. 0.29 5.19 4.20
BSC
5.20 4.04
BSC
0.68
BSC
0.60
BSC
0.52
BSC
NOM 0.95 0.24 0.7 0.32 5.29 5.30
MAX 1.00.27 0.70.35 5.39 5.40
Top View
View B
Side View
A2
A1
Seating
Plane
View A View B
Bottom View
D
View A
b
E
A
Note 1
(Ball 1
Index Area
D/4 x E/4)
0,0
E1
e1
E2
e D1
e
e1
e1
e
C/L
C/L
1
42
1
42
Notes:
1. %DOOLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG%DOOLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURUD
printed indicator.
1RWHV)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJV6HHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQDWZZZPLFURFKLSFRPSDFNDJLQJ
2017 Microchip Technology Inc. DS20005498A-page 15
HV2605/HV2705
Note: For more information about ball coordinates, contact Microchip sales.
1" View B H
48-Lead LQFP Package Outline (FG)
7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch
Symbol A A1 A2 b D D1 E E1 e L L1 L2 ș
Dimension
(mm)
MIN 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80*
0.50
BSC
0.45
1.00
REF
0.25
BSC
0O
NOM - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5O
MAX 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* 0.75 7O
JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001.
7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ
Drawings are not to scale.
1
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
Seating
Plane
Top View
Side View
Note 1
(Index Area
D1/4 x E1/4)
48
A2A
A1
b
D
D1
E
E1
e
Note:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU
a printed indicator.
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
HV2605/HV2705
DS20005498A-page 16 2017 Microchip Technology Inc.
2017 Microchip Technology Inc. DS20005498A-page 17
HV2605/HV2705
APPENDIX A: REVISION HISTORY
Revision A (November 2017)
Converted Supertex Doc # DSFP-HV2605 and
Doc # DSFP-HV2705-HV2706 to Microchip
DS20005498A
Removed HV2706 from the document. HV2706 is EOL.
Combined HV2605 and HV2705 into one
document
Changed the package marking format
Added information for 42-Ball Bumped Die package
Removed the “HVCMOS technology for high per-
formance” in the Features section
Made minor text changes throughout the docu-
ment
To order or obtam mlormanon, 99” an pncmg or dehver ‘refer tu me factory or me \Islad sa‘es office. PART NO. XX x x T T T v
HV2605/HV2705
DS20005498A-page 18 2017 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Devices: HV2605 = 16-Channel Low Harmonic Distortion
High-Voltage Analog Switch
HV2705 = 16-Channel Low Harmonic Distortion
High-Voltage Analog Switch with Bleed Resistors
Packages: BD = 42-Ball Bumped Die
FG = 48-lead LQFP
Environmental: G = Lead (Pb)-free/RoHS-compliant package
(not used for BD packages)
Media Types: (blank) = 250/Tray for an FG package
M931 = 1000/Reel for an FG package
M936 = 2500/Reel for a BD package
Examples:
a) HV2605FG-G: 16-Channel Low Har-
monic Distortion High-
Voltage Analog Switch,
48-lead LQFP Pack-
age, 250/Tray
b) HV2605FG-G-M931: 16-Channel Low Har-
monic Distortion High-
Voltage Analog Switch,
48-lead LQFP Pack-
age, 1000/Reel
c) HV2705BD-M936: 16-Channel Low Har-
monic Distortion High-
Voltage Analog Switch
with Bleed Resistors,
42-ball Bumped Die,
2500/Reel
PART NO. X
Device
X
Environmental
XX
Package Media
--
Type
Note: HV2605BD and HV2705BD are RoHS-compliant products
YSTEM
2017 Microchip Technology Inc. DS20005498A-page 19
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2345-4
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
6‘ ‘MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS20005498A-page 20 2017 Microchip Technology Inc.
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Worldwide Sales and Service
10/25/17

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