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This document contains complete and detailed description of all modules included in the
Atmel®AVR® XMEGA® E microcontroller family. The XMEGA E is a family of low-power, high-
performance, and peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced
RISC architecture. The available XMEGA E modules described in this manual are:
Atmel AVR CPU
Memories
EDMA - Enhanced direct memory access
Event system
System clock and clock options
Power management and sleep modes
Reset system
WDT - Watchdog timer
Interrupts and programmable multilevel interrupt controller
PORT - I/O ports
TC4/5 - 16-bit timer/counters
WeX - Waveform extension
Hi-Res - High resolution extension
Fault - Fault extension
RTC - Real-time counter
TWI - Two-wire serial interface
SPI - Serial peripheral interface
USART - Universal synchronous and asynchronous serial receiver and transmitter
IRCOM - Infrared communication module
XCL - XMEGA custom logic
CRC - Cyclic redundancy check
ADC - Analog-to-digital converter
DAC - Digital-to-analog converter
AC - Analog comparator
PDI - Program and debug interface
Memory Programming
Peripheral module address map
Instruction set summary
Manual revision history
Table of contents
8/16-bit Atmel AVR XMEGA Microcontrollers
XMEGA E MANUAL
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1. About the Manual
This document contains in-depth documentation of all peripherals and modules available for the Atmel AVR XMEGA E
microcontroller family. All features are documented on a functional level and described in a general sense. All peripherals
and modules described in this manual may not be present in all XMEGA E devices.
For all device-specific information such as characterization data, memory sizes, modules, peripherals available and their
absolute memory addresses, refer to the device datasheets. When several instances of a peripheral exists in one device,
each instance will have a unique name. For example each port module (PORT) have unique name, such as PORTA,
PORTB, etc. Register and bit names are unique within one module instance.
For more details on applied use and code examples for peripherals and modules, refer to the Atmel AVR XMEGA
specific application notes available from http://www.atmel.com/avr.
1.1 Reading the Manual
The main sections describe the various modules and peripherals. Each section contains a short feature list and overview
describing the module. The remaining section describes the features and functions in more detail.
The register description sections list all registers and describe each register, bit and flag with their function. This includes
details on how to set up and enable various features in the module. When multiple bits are needed for a configuration
setting, these are grouped together in a bit group. The possible bit group configurations are listed for all bit groups
together with their associated Group Configuration and a short description. The Group Configuration refers to the defined
configuration name used in the Atmel AVR XMEGA assembler header files and application note source code.
The register summary sections list the internal register map for each module type.
The interrupt vector summary sections list the interrupt vectors and offset address for each module type.
1.2 Resources
A comprehensive set of development tools, application notes, and datasheets are available for download from
http://www.atmel.com/avr.
1.3 Recommended Reading
XMEGA E device datasheets
XMEGA application notes
This manual contains general modules and peripheral descriptions. The AVR XMEGA E device datasheets contains the
device-specific information. The XMEGA application notes and Atmel Software Framework contain example code and
show applied use of the modules and peripherals.
For new users, it is recommended to read the AVR1000 - Getting Started Writing C Code for Atmel XMEGA.
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2. Overview
The AVR XMEGA E microcontrollers is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit
microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the XMEGA E devices achieve throughputs approaching one million instructions per second (MIPS) per
megahertz, allowing the system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The XMEGA E devices provide the following features: in-system programmable flash; internal EEPROM and SRAM;
four-channel enhanced DMA controller (EDMA); eight-channel event system with asynchronous event support;
programmable multilevel interrupt controller; up to 26 general purpose I/O lines; 16-bit real-time counter (RTC) with
digital correction; up to three flexible, 16-bit timer/counters with capture, compare and PWM modes; up to two USARTs;
one I2C and SMBUS compatible two-wire serial interfaces (TWI); one serial peripheral interfaces (SPI); one XMEGA
custom logic (XCL) with timer/counter and logic functions; CRC module; one 16-channel, 12-bit ADC with programmable
gain, offset and gain correction, averaging, oversampling and decimation; one 2-channel, 12-bit DAC; two analog
comparators with window mode; programmable watchdog timer with separate internal oscillator; accurate internal
oscillators with PLL and prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. Selected
devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for on-chip debug and
programming.
The Atmel AVR XMEGA devices have five software selectable power saving modes. The idle mode stops the CPU while
allowing the SRAM, EDMA controller, event system, interrupt controller, and all peripherals to continue functioning. The
power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the
next TWI, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external
crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external
crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the
asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual
peripheral can optionally be stopped in active mode and idle sleep mode. The low power internal 8MHz oscillator allows
very fast start-up time, combined with low power modes.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI interface. A boot loader running in the device can use any interface to
download the application program to the flash memory. By combining an 8/16-bit RISC CPU with In-system, self-
programmable flash, the Atmel AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost
effective solution for many embedded applications.
The XMEGA E devices are supported with a full suite of program and system development tools, including C compilers,
macro assemblers, program debugger/simulators, programmers, and evaluation kits.
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2.1 Block Diagram
Figure 2-1. XMEGA E Block Diagram
Note: 1. AVCC is only powering the following I/Os and analog functions:
PA0 to PA7, AREF, ADC, DAC, AC0:1, Power Supervision, tempref, VREF
, and Watchdog Oscillator.
VCC is powering all other functions and I/Os.
Power
Supervision
POR/BOD &
RESET
EVENT ROUTING NETWORK
EDMA
Controller
BUS Matrix
SRAM
OCD
PDI
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
Prog/Debug
Controller
VCC
GND
PORT R (2)
PR[0..1]
Oscillator
Control
Real Time
Counter
Event System
Controller
PDI_DATA
RESET /
PDI_CLK
Sleep
Controller
CRC
IRCOM
PORT C (8)
PC[0..7]
TCC4:5
USARTC0
SPIC
EVENT ROUTING NETWORK
CPU
NVM Controller
Flash EEPROM
DATA BUS
XTAL2 /
TOSC2
XTAL1 /
TOSC1
Oscillator
Circuits/
Clock
Generation
Digital function
Analog function / Oscillators
Programming, debug, test
External clock / Crystal pins
General Purpose I/O
Ground
Power
TWIC
TCD5
USARTD0
XCL
PORT A (8)
PORT D (8)
ADCA
DACA
ACA
Int. Refs.
PA[0..7]
PD[0..7]
AREFA
AREFD
Tempref
VCC/10
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In Table 2-1 on page 5 a feature summary for the XMEGA E family is shown, split into one feature summary column for
each sub-family. Each sub-family has identical feature set, but different memory options, refer to their device datasheet
for ordering codes and memory options.
Table 2-1. XMEGA E Feature Summary Overview
Feature Details / sub-family E5
Pins, I/O
Total 32
Programmable I/O pins 26
Memory
Program memory (KB) 8 - 32
Boot memory (KB) 2 - 4
SRAM (KB) 1 - 4
EEPROM (Bytes) 512
General purpose registers 4
Package
TQFP 32A
QFN /VQFN 32Z
QTouch®Sense channels 56
EDMA Controller Channels 4
Event System
Channels 8
QDEC 1
Rotary 1
Crystal Oscillator
0.4 - 16MHz XOSC Yes
32.768 kHz TOSC Yes
Internal Oscillator
8MHz calibrated Yes
32MHz calibrated Yes
128MHz PLL Yes
32.768kHz calibrated Yes
32kHz ULP Yes
Timer / Counter
TC4 - 16-bit, 4 CC 1
TC5 - 16-bit, 2 CC 2
Hi-Res 1
WeX 1
FAULT 2
RTC Yes
XMEGA Custom Logic
BTC0 - 8-bit, 1 CC 1
BTC1 - 8-bit, 1 CC 1
LUT, 2-input, one output 2
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Serial Communication
USART 2
SPI 1
TWI 1
CRC
CRC-16 Yes
CRC-32 Yes
Analog to Digital Converter (ADC)
1
Resolution (bits) 12
Oversampling extra resolution (bits) 4
Sampling speed (kbps) 300
External inputs per ADC 16
Conversion channels 1
Offset/gain error correction Yes
Averaging (samples) 1 - 1024
Digital to Analog Converter (DAC)
1
Resolution (bits) 12
Sampling speed (kbps) 1000
Output channels per DAC 2
Analog Comparator (AC) 2
Program and Debug Interface (PDI) PDI Yes
Feature Details / sub-family E5
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3. Atmel AVR CPU
3.1 Features
8/16-bit, high-performance Atmel AVR RISC CPU
141 instructions
Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack pointer accessible in I/O memory space
Direct addressing of up to 16MB of program memory and 16MB of data memory
True 16/24-bit access to 16/24-bit I/O registers
Efficient support for 8-, 16-, and 32-bit arithmetic
Configuration change protection of system-critical features
3.2 Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, “PMIC – Interrupts and
Programmable Multilevel Interrupt Controller” on page 132.
3.3 Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For a summary of all AVR instructions, refer to “Instruction Set Summary” on page
432. For details of all AVR instructions, refer to http://www.atmel.com/avr.
Figure 3-1. Block Diagram of the AVR CPU Architecture
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The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM is memory
mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-
programming of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for save storing of nonvolatile data in the program memory.
3.4 ALU - Arithmetic Logic Unit
The arithmetic logic unit supports arithmetic and logic operations between registers or between a constant and a register.
Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose
registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status
register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
3.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
Multiplication of unsigned integers
Multiplication of signed integers
Multiplication of a signed integer with an unsigned integer
Multiplication of unsigned fractional numbers
Multiplication of signed fractional numbers
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
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3.5 Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
3.6 Instruction Execution Timing
The AVR CPU is clocked by the CPU clock, clkCPU. No internal clock division is used. Figure 3-2 shows the parallel
instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file
concept. This is the basic pipelining concept used to obtain up to 1MIPS/MHz performance with high power efficiency.
Figure 3-2. The Parallel Instruction Fetches and Instruction Executions
Figure 3-3 shows the internal timing concept for the register file. In a single clock cycle, an ALU operation using two
register operands is executed and the result is stored back to the destination register.
Figure 3-3. Single Cycle ALU Operation
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2
nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU
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3.7 Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the “Instruction Set Summary” on page 432. This
will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact
code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
3.8 Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
3.9 Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.
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Figure 3-4. AVR CPU General Purpose Working Registers
The register file is located in a separate address space, and so the registers are not accessible as data memory.
3.9.1 The X-, Y-, and Z-registers
Registers R26..R31 have added functions besides their general-purpose usage.
These registers can form 16-bit address pointers for addressing data memory. These three address registers are called
the X-register, Y-register, and Z-register. The Z-register can also be used as an address pointer to read from and/or write
to the flash program memory, signature rows, fuses, and lock bits.
Figure 3-5. The X-, Y-, and Z-registers
The lowest register address holds the least-significant byte (LSB), and the highest register address holds the most-
significant byte (MSB). In the different addressing modes, these address registers function as fixed displacement,
automatic increment, and automatic decrement (see the “Instruction Set Summary” on page 432 for details).
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
Bit (individually) 7 R27 0 7 R26 0
X-register XH XL
Bit (X-register) 15 8 7 0
Bit (individually) 7 R29 0 7 R28 0
Y-register YH YL
Bit (Y-register) 15 8 7 0
Bit (individually) 7 R31 0 7 R30 0
Z-register ZH ZL
Bit (Z-register) 15 8 7 0
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3.10 RAMP and Extended Indirect Registers
In order to access program memory or data memory above 64KB, the address pointer must be larger than 16 bits. This is
done by concatenating one register to one of the X-, Y-, or Z-registers. This register then holds the most-significant byte
(MSB) in a 24-bit address or address pointer.
These registers are available only on devices with external bus interface and/or more than 64KB of program or data
memory space. For these devices, only the number of bits required to address the whole program and data memory
space in the device is implemented in the registers.
3.10.1 RAMPX, RAMPY, and RAMPZ Registers
The RAMPX, RAMPY, and RAMPZ registers are concatenated with the X-, Y-, and Z-registers, respectively, to enable
indirect addressing of the whole data memory space above 64KB and up to 16MB.
Figure 3-6. The Combined RAMPX + X, RAMPY + Y, and RAMPZ + Z Registers
When reading (ELPM) and writing (SPM) program memory locations above the first 128KB of the program memory,
RAMPZ is concatenated with the Z-register to form the 24-bit address. LPM is not affected by the RAMPZ setting.
3.10.2 RAMPD Register
This register is concatenated with the operand to enable direct addressing of the whole data memory space above 64KB.
Together, RAMPD and the operand will form a 24-bit address.
Figure 3-7. The Combined RAMPD + K Register
3.10.3 EIND - Extended Indirect Register
EIND is concatenated with the Z-register to enable indirect jump and call to locations above the first 128KB (64K words)
of the program memory.
Figure 3-8. The Combined EIND + Z Register
Bit (Individually) 7 0 7 0 7 0
RAMPX XH XL
Bit (X-pointer) 23 16 15 8 7 0
Bit (Individually) 7 0 7 0 7 0
RAMPY YH YL
Bit (Y-pointer) 23 16 15 8 7 0
Bit (Individually) 7 0 7 0 7 0
RAMPZ ZH ZL
Bit (Z-pointer) 23 16 15 8 7 0
Bit (Individually) 7 0 15 0
RAMPD K
Bit (D-pointer) 23 16 15 0
Bit (Individually) 7 0 7 0 7 0
EIND ZH ZL
Bit (D-pointer) 23 16 15 8 7 0
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3.11 Accessing 16-bit Registers
The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These registers must be
byte-accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary register
using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte is then written
into the temporary register. When the high byte of the 16-bit register is written, the temporary register is copied into the
low byte of the 16-bit register in the same clock cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low byte register is
read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the
low byte is read. When the high byte is read, it is then read from the temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when reading or writing
the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit register during an
atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when writing or reading 16-bit registers.
The temporary registers can also be read and written directly from user software.
3.11.1 Accessing 24- and 32-bit Registers
For 24- and 32-bit registers, the read and write access is done in the same way as described for 16-bit registers, except
there are two temporary registers for 24-bit registers and three for 32-bit registers. The least-significant byte must be
written first when doing a write, and read first when doing a read.
3.12 Configuration Change Protection
System critical I/O register settings are protected from accidental modification. The SPM instruction is protected from
accidental execution, and the LPM instruction is protected when reading the fuses and signature row. This is handled
globally by the configuration change protection (CCP) register. Changes to the protected I/O registers or bits, or
execution of protected instructions, are only possible after the CPU writes a signature to the CCP register. The different
signatures are described in the register description.
There are two modes of operation: one for protected I/O registers, and one for the protected instructions, SPM/LPM.
3.12.1 Sequence for Write Operation to Protected I/O Registers
1. The application code writes the signature that enable change of protected I/O registers to the CCP register.
2. Within four instruction cycles, the application code must write the appropriate data to the protected register. Most
protected registers also contain a write enable/change enable bit. This bit must be written to one in the same oper-
ation as the data are written. The protected change is immediately disabled if the CPU performs write operations to
the I/O register or data memory or if the SPM, LPM, or SLEEP instruction is executed.
3.12.2 Sequence for Execution of Protected SPM/LPM
1. The application code writes the signature for the execution of protected SPM/LPM to the CCP register.
2. Within four instruction cycles, the application code must execute the appropriate instruction. The protected change
is immediately disabled if the CPU performs write operations to the data memory or if the SLEEP instruction is
executed.
Once the correct signature is written by the CPU, interrupts will be ignored for the duration of the configuration change
enable period. Any interrupt request (including non-maskable interrupts) during the CCP period will set the
corresponding interrupt flag as normal, and the request is kept pending. After the CCP period is completed, any pending
interrupts are executed according to their level and priority. EDMA requests are still handled, but do not influence the
protected configuration change enable period. A signature written by EDMA is ignored.
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3.13 Fuse Lock
For some system-critical features, it is possible to program a fuse to disable all changes to the associated I/O control
registers. If this is done, it will not be possible to change the registers from the user software, and the fuse can only be
reprogrammed using an external programmer. Details on this are described in the datasheet module where this feature is
available.
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3.14 Register Descriptions
3.14.1 CCP – Configuration Change Protection Register
Bit 7:0 – CCP[7:0]: Configuration Change Protection Bits
The CCP register must be written with the correct signature to enable change of the protected I/O register or exe-
cution of the protected instruction for a maximum period of four CPU instruction cycles. All interrupts are ignored
during these cycles. After these cycles, interrupts will automatically be handled again by the CPU, and any pend-
ing interrupts will be executed according to their level and priority. When the protected I/O register signature is
written, CCP[0] will read as one as long as the protected feature is enabled. Similarly when the protected
SPM/LPM signature is written, CCP[1] will read as one as long as the protected feature is enabled. CCP[7:2] will
always read as zero. Table 3-1 on page 15 shows the signature for the various modes.
Table 3-1. Modes of CPU Change Protection
3.14.2 RAMPD – Extended Direct Addressing Register
This register is concatenated with the operand for direct addressing (LDS/STS) of the whole data memory space on
devices with more than 64KB of data memory. This register is not available if the data memory, including external
memory, is less than 64KB.
Bit 7:0 – RAMPD[7:0]: Extended Direct Addressing Bits
These bits hold the MSB of the 24-bit address created by RAMPD and the 16-bit operand. Only the number of bits
required to address the available data memory is implemented for each device. Unused bits will always read as
zero.
3.14.3 RAMPX – Extended X-Pointer Register
This register is concatenated with the X-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory
space on devices with more than 64KB of data memory. This register is not available if the data memory, including
external memory, is less than 64KB.
Bit 76543210
+0x04 CCP[7:0]
Read/Write W W W W W W R/W R/W
Initial value 00000000
Signature Group configuration Description
0x9D SPM Protected SPM/LPM
0xD8 IOREG Protected IO register
Bit 76543210
+0x08 RAMPD[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000
Bit 76543210
+0x09 RAMPX[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000
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Bit 7:0 – RAMPX[7:0]: Extended X-pointer Address Bits
These bits hold the MSB of the 24-bit address created by RAMPX and the 16-bit X-register. Only the number of
bits required to address the available data memory is implemented for each device. Unused bits will always read
as zero.
3.14.4 RAMPY – Extended Y-Pointer Register
This register is concatenated with the Y-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory
space on devices with more than 64KB of data memory. This register is not available if the data memory, including
external memory, is less than 64KB.
Bit 7:0 – RAMPY[7:0]: Extended Y-pointer Address Bits
These bits hold the MSB of the 24-bit address created by RAMPY and the 16-bit Y-register. Only the number of
bits required to address the available data memory is implemented for each device. Unused bits will always read
as zero.
3.14.5 RAMPZ – Extended Z-Pointer Register
This register is concatenated with the Z-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory
space on devices with more than 64KB of data memory. RAMPZ is concatenated with the Z-register when reading
(ELPM) program memory locations above the first 64KB and writing (SPM) program memory locations above the first
128KB of the program memory.
This register is not available if the data memory, including external memory and program memory in the device, is less
than 64KB.
Bit 7:0 – RAMPZ[7:0]: Extended Z-pointer Address Bits
These bits hold the MSB of the 24-bit address created by RAMPZ and the 16-bit Z-register. Only the number of
bits required to address the available data and program memory is implemented for each device. Unused bits will
always read as zero.
3.14.6 EIND – Extended Indirect Register
This register is concatenated with the Z-register for enabling extended indirect jump (EIJMP) and call (EICALL) to the
whole program memory space on devices with more than 128KB of program memory. The register should be used for
jumps to addresses below 128KB if ECALL/EIJMP are used, and it will not be used if CALL and IJMP commands are
used. For jump or call to addresses below 128KB, this register is not used. This register is not available if the program
memory in the device is less than 128KB.
Bit 76543210
+0x0A RAMPY[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000
Bit 76543210
+0x0B RAMPZ[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000
Bit76543210
+0x0C EIND[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000
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Bit 7:0 – EIND[7:0]: Extended Indirect Address Bits
These bits hold the MSB of the 24-bit address created by EIND and the 16-bit Z-register. Only the number of bits
required to access the available program memory is implemented for each device. Unused bits will always read as
zero.
3.14.7 SPL – Stack Pointer Register Low
The SPH and SPL stack pointer pair represent the 16-bit SP value. The SP holds the stack pointer that points to the top
of the stack. After reset, the stack pointer points to the highest internal SRAM address. To prevent corruption when
updating the stack pointer from software, a write to SPL will automatically disable interrupts for the next four instructions
or until the next I/O memory write.
Only the number of bits required to address the available data memory, including external memory, up to 64KB is
implemented for each device. Unused bits will always read as zero.
Note: 1. Refer to specific device datasheets for exact size.
Bit 7:0 – SP[7:0]: Stack Pointer Low Byte
These bits hold the LSB of the 16-bit stack pointer (SP).
3.14.8 SPH – Stack Pointer Register High
Note: 1. Refer to specific device datasheets for the exact size.
Bit 7:0 – SP[15:8]: Stack Pointer High Byte
These bits hold the MSB of the 16-bit stack pointer (SP).
3.14.9 SREG – Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. For details information about the bits in this register and how they are affected by the different instructions
see “Instruction Set Summary” on page 432.
Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set for interrupts to be enabled. If the global interrupt enable register is
cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. This bit is not
cleared by hardware after an interrupt has occurred. This bit can be set and cleared by the application with the SEI
and CLI instructions, as described in “Instruction Set Summary” on page 432. Changing the I flag through the I/O-
register result in a one-cycle wait state on the access.
Bit 76543210
+0x0D SP[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value(1) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Bit 76543210
+0x0E SP[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value(1) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Bit 76543210
+0x0F ITHSVNZC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000
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Bit 6 – T: Bit Copy Storage
The bit copy instructions bit load (BLD) and bit store (BST) use the T bit as source or destination for the operated
bit. A bit from a register in the register file can be copied into this bit by the BST instruction, and this bit can be cop-
ied into a bit in a register in the register file by the BLD instruction.
Bit 5 – H: Half Carry Flag
The half carry flag (H) indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic.
Bit 4 – S: Sign Bit, S = N V
The sign bit is always an exclusive or between the negative flag, N, and the two’s complement overflow flag, V.
Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag (V) supports two’s complement arithmetic.
Bit 2 – N: Negative Flag
The negative flag (N) indicates a negative result in an arithmetic or logic operation.
Bit 1 – Z: Zero Flag
The zero flag (Z) indicates a zero result in an arithmetic or logic operation.
Bit 0 – C: Carry Flag
The carry flag (C) indicates a carry in an arithmetic or logic operation.
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3.15 Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 Reserved ––––––––
+0x01 Reserved ––––––––
+0x02 Reserved ––––––––
+0x03 Reserved ––––––––
+0x04 CCP CCP[7:0] 15
+0x05 Reserved ––––––––
+0x06 Reserved ––––––––
+0x07 Reserved ––––––––
+0x08 RAMPD RAMPD[7:0] 15
+0x09 RAMPX RAMPX[7:0] 15
+0x0A RAMPY RAMPY[7:0] 16
+0x0B RAMPZ RAMPZ[7:0] 16
+0x0C EIND EIND[7:0] 16
+0x0D SPL SPL[7:0] 17
+0x0E SPH SPH[7:0] 17
+0x0F SREG I T H S V N Z C 17
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4. Memories
4.1 Features
Flash program memory
One linear address space
In-system programmable
Self-programming and boot loader support
Application section for application code
Application table section for application code or data storage
Boot section for application code or bootloader code
Separate read/write protection lock bits for all sections
Built in fast CRC check of a selectable flash program memory section
Data memory
One linear address space
Single-cycle access from CPU
SRAM
EEPROM
Byte and page accessible
Memory mapped for direct load and store
I/O memory
Configuration and status registers for all peripherals and modules
Four bit-accessible general purpose registers for global variables or flags
Bus arbitration
Deterministic handling of priority between CPU, EDMA controller, and other bus masters
Separate buses for SRAM, EEPROM, I/O memory, and external memory access
Simultaneous bus access for CPU and EDMA controller
Production signature row memory for factory programmed data
ID for each microcontroller device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
User signature row
One flash page in size
Can be read and written from software
Content is kept after chip erase
4.2 Overview
This section describes the different memory sections. The AVR architecture has two main memory spaces, the program
memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the
program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile
data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces
can be locked for further write and read/write operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
4.3 Flash Program Memory
All XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory
can be accessed for read and write from an external programmer through the PDI or from application software running in
the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section, as shown in Figure 4-1 on page 21. The sizes
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of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have
different levels of protection. The store program memory (SPM) instruction, used to write to the flash from the application
software, will only operate when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Figure 4-1. Flash Memory Sections
4.3.1 Application Section
The Application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
4.3.2 Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
4.3.3 Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can initiate programming when executing from this section. When
programming, the CPU is halted, waiting for the flash operation to complete. The SPM instruction can access the entire
flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot
loader lock bits. If this section is not used for boot loader software, application code can be stored here.
Application Flash
Section
0x000000
End Application
Start Boot Loader
Flashend
Application Table
Flash Section
Boot Loader Flash
Section
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4.3.4 Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions such as temperature, voltage
references, etc., refer to the device datasheet.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
4.3.5 User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
4.4 Fuses and Lockbits
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure the startup configuration and reset sources such
as brownout detector and watchdog.
The lock bits are used to set protection levels for the different flash sections (i.e., if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
4.5 Data Memory
The data memory contains the I/O memory, internal SRAM, EEPROM, and external memory, if available. The data
memory is organized as one continuous memory section, as shown in Figure 4-2 on page 23.
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Figure 4-2. Data Memory Map
I/O memory, EEPROM, and SRAM will always have the same start addresses for all XMEGA devices.
4.6 Internal SRAM
The internal SRAM always starts at hexadecimal address 0x2000. SRAM is accessed by the CPU using the load
(LD/LDS/LDD) and store (ST/STS/STD) instructions.
4.7 EEPROM
All XMEGA devices have EEPROM for nonvolatile data storage. It is addressable in a separate memory mapped space
and accessed in normal data space. The EEPROM supports both byte and page access. EEPROM is accessible using
load and store instructions, allowing highly efficient EEPROM reading and EEPROM buffer loading. EEPROM always
starts at the hexadecimal address 0x1000.
4.8 I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
4.8.1 General Purpose I/O Registers
The lowest four I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
4.9 Data Memory and Bus Arbitration
Since the data memory is organized as three separate sets of memories, the different bus masters (CPU, EDMA
controller read and EDMA controller write, etc.) can access different memory sections at the same time. See Figure 4-3
on page 24.
I/O Memory
(Up to 4KB)
EEPROM
(Up to 1KB)
Internal SRAM
0x0000
0x1000
0x2000
Start/End
Address Data Memory
(Up to 4KB)
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Figure 4-3. Bus Access
4.9.1 Bus Priority
When several masters request access to the same bus, the bus priority is in the following order (from higher to lower
priority):
1. Bus Master with ongoing access.
2. Bus Master with ongoing burst.
1. Alternating EDMA controller read and EDMA controller write when they access the same data memory
section.
3. Bus Master requesting burst access.
1. CPU has priority.
4. Bus Master requesting bus access.
1. CPU has priority.
4.10 Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (EDMA), new data are available every cycle. EEPROM page load (write) takes
one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the
instruction summary for more details on instructions and instruction timing.
4.11 Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
Peripherals and system modules
Bus matrix
CPUEDMA
OCD
USART
SPI Timer /
Counter
TWI
Interrupt
controller
Power
management
External
programming
PDIAVR core
ADC
AC
Event
system
Oscillator
control
CH2 CH3
Non-volatile
memory
EEPROM
Flash CRC
Real Time
Counter
RAM
SRAM
I/ODAC
CH0 CH1
XMEGA
Custom Logic
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4.12 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism. For details, refer to “Configuration Change
Protection” on page 13.
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4.13 Register Description – NVM Controller
4.13.1 ADDR0 Address Register 0
The ADDR0, ADDR1, and ADDR2 registers represent the 24-bit value, ADDR. This is used for addressing all NVM
sections for read, write, and CRC operations.
Bit 7:0 – ADDR[7:0]: Address Byte 0
This register gives the address low byte when accessing NVM locations.
4.13.2 ADDR1 – Address Register 1
Bit 7:0 – ADDR[15:8]: Address Byte 1
This register gives the address high byte when accessing NVM locations.
4.13.3 ADDR2 – Address Register 2
Bit 7:0 – ADDR[23:16]: Address Byte 2
This register gives the address extended byte when accessing NVM locations.
4.13.4 DATA0 – Data Register 0
The DATA0, DATA1, and DATA registers represent the 24-bit value, DATA. This holds data during NVM read, write, and
CRC access.
Bit 7:0 – DATA[7:0]: Data Byte 0
This register gives the data value byte 0 when accessing NVM locations.
Bit 76543210
+0x00 ADDR[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value11111111
Bit 76543210
+0x01 ADDR[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 76543210
+0x02 ADDR[23:16]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 76543210
+0x04 DATA[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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4.13.5 DATA1 – Data Register 1
Bit 7:0 – DATA[15:8]: Data Byte 1
This register gives the data value byte 1 when accessing NVM locations.
4.13.6 DATA2 – Data Register 2
Bit 7:0 – DATA[23:16]: Data Byte 2
This register gives the data value byte 2 when accessing NVM locations.
4.13.7 CMD – Command Register
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 6:0 – CMD[6:0]: Command
These bits define the programming commands for the flash. Bit 6 is only set for external programming commands.
See “Memory Programming” on page 411 for programming commands.
4.13.8 CTRLA – Control Register A
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – CMDEX: Command Execute
Setting this bit will execute the command in the CMD register. This bit is protected by the configuration change
protection (CCP) mechanism. Refer to “Configuration Change Protection” on page 13 for details on the CCP.
Bit 76543210
+0x05 DATA[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 76543210
+0x06 DATA[23:16]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 76543210
+0x0A –CMD[6:0]
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 7654321 0
+0x0B –––––––CMDEX
Read/Write R R RRRRR S
Initial value0000000 0
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4.13.9 CTRLB – Control Register B
Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 1 – EPRM: EEPROM Power Reduction Mode
Setting this bit enables power saving for the EEPROM. The EEPROM will then be turned off in a manner equiva-
lent to entering sleep mode. If access is required, the bus master will be halted for a time equal to the start-up time
from idle sleep mode.
Bit 0 – SPMLOCK: SPM Locked
This bit can be written to prevent all further self-programming. The bit is cleared at reset, and cannot be cleared
from software. This bit is protected by the configuration change protection (CCP) mechanism. Refer to “Configura-
tion Change Protection” on page 13 for details on the CCP.
4.13.10 INTCTRL – Interrupt Control Register
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:2 – SPMLVL[1:0]: SPM Ready Interrupt Level
These bits enable the interrupt and select the interrupt level, as described in “PMIC – Interrupts and Programma-
ble Multilevel Interrupt Controller” on page 132. This is a level interrupt that will be triggered only when the
NVMBUSY flag in the STATUS register is set to zero. Thus, the interrupt should not be enabled before triggering
an NVM command, as the NVMBUSY flag will not be set before the NVM command is triggered. The interrupt
should be disabled in the interrupt handler.
Bit 1:0 – EELVL[1:0]: EEPROM Ready Interrupt Level
These bits enable the EEPROM ready interrupt and select the interrupt level, as described in “PMIC – Interrupts
and Programmable Multilevel Interrupt Controller” on page 132. This is a level interrupt that will be triggered only
when the NVMBUSY flag in the STATUS register is set to zero. Thus, the interrupt should not be enabled before
triggering an NVM command, as the NVMNVMBUSY flag will not be set before the NVM command is triggered.
The interrupt should be disabled in the interrupt handler.
Bit 7 6 5 4 3 2 1 0
+0x0C ––––– EPRM SPMLOCK
Read/Write R R R R R R R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
+0x0D –––– SPMLVL[1:0] EELVL[1:0]
Read/Write RRRRR/WR/WR/WR/W
Initial value00000000
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4.13.11 STATUS – Status Register
Bit 7 – NVMBUSY: Nonvolatile Memory Busy
The NVMBUSY flag indicates if the NVM (Flash, EEPROM, lock bit) is being programmed. Once an operation is
started, this flag is set and remains set until the operation is completed. The NVMBUSY flag is automatically
cleared when the operation is finished.
Bit 6 – FBUSY: Flash Busy
The FBUSY flag indicates if a flash programming operation is initiated. Once an operation is started, the FBUSY
flag is set and the application section cannot be accessed. The FBUSY flag is automatically cleared when the
operation is finished.
Bit 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 1 – EELOAD: EEPROM Page Buffer Active Loading
The EELOAD flag indicates that the temporary EEPROM page buffer has been loaded with one or more data
bytes. It remains set until an EEPROM page write or a page buffer flush operation is executed. For more details,
see “Flash and EEPROM Programming Sequences” on page 413.
Bit 0 – FLOAD: Flash Page Buffer Active Loading
The FLOAD flag indicates that the temporary flash page buffer has been loaded with one or more data bytes. It
remains set until an application page write, boot page write, or page buffer flush operation is executed. For more
details, see “Flash and EEPROM Programming Sequences” on page 413.
4.13.12 LOCKBITS – Lock Bit Register
This register is a mapping of the NVM lock bits into the I/O memory space which enables direct read access from
the application software. Refer to “LOCKBITS – Lock Bit Register” on page 33 for a description.
Bit 7 6 5432 1 0
+0x0F NVMBUSY FBUSY ––– EELOAD FLOAD
Read/Write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
+0x10 BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0]
Read/Write R R R R R R R R
Initial Value 1 1 1 1 1 1 1 1
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4.14 Register Descriptions – Fuses and Lock Bits
4.14.1 FUSEBYTE1 – Fuse Byte 1
Bit 7:4 – WDWPER[3:0]: Watchdog Window Timeout Period
These fuse bits are used to set initial value of the closed window for the Watchdog Timer in Window Mode. During
reset these fuse bits are automatically written to the WPER bits Watchdog Window Mode Control Register. Refer
to “WINCTRL – Window Mode Control Register” on page 130 for details.
Bit 3:0 – WDPER[3:0]: Watchdog Timeout Period
These fuse bits are used to set the initial value of the watchdog timeout period. During reset, these fuse bits are
automatically written to the PER bits in the watchdog control register. Refer to “CTRL – Control Register” on page
129 for details.
4.14.2 FUSEBYTE2 – Fuse Byte 2
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to one
when this register is written.
Bit 6 – BOOTRST: Boot Loader Section Reset Vector
This fuse can be programmed so the reset vector is pointing to the first address in the boot loader flash section.
The device will then start executing from the boot loader flash section after reset.
Table 4-1. Boot Reset Fuse
Bit 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
one when this register is written.
Bit 1:0 – BODPD[1:0]: BOD Operation in Power-down Mode
These fuse bits set the BOD operation mode in all sleep modes except idle mode.
For details on the BOD and BOD operation modes, refer to “Brownout Detection” on page 122.
Bit 7 6543210
+0x01 WDWPER[3:0] WDPER[3:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0000000
Bit 7 6 5 43210
+0x02 BOOTRST – – –BODPD[1:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 11111
BOOTRST Reset address
0Reset vector = Boot loader reset
1Reset vector = Application reset (address 0x0000)
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Table 4-2. BOD Operation Modes in Sleep Modes
4.14.3 FUSEBYTE4 – Fuse Byte 4
Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
one when this register is written.
Bit: 4 – RSTDISBL: External Reset Disable
This fuse can be programmed to disable the external reset pin functionality. When this is done, pulling the reset pin
low will not cause an external reset. A reset is required before this bit will be read correctly after it is changed.
Bit 3:2 – STARTUPTIME[1:0]: Start-up Time
These fuse bits can be used to set at a programmable timeout period from when all reset sources are released
until the internal reset is released from the delay counter. A reset is required before these bits will be read correctly
after they are changed.
The delay is timed from the 1kHz output of the ULP oscillator. Refer to “Reset Sequence” on page 121 for details.
Table 4-3. Start-up Time
Bit 1 – WDLOCK: Watchdog Timer Lock
The WDLOCK fuse can be programmed to lock the watchdog timer configuration. When this fuse is programmed,
the watchdog timer configuration cannot be changed, and the ENABLE bit in the watchdog CTRL register is auto-
matically set at reset and cannot be cleared from the application software. The WEN bit in the watchdog WINCTRL
register is not set automatically, and needs to be set from software. A reset is required before this bit will be read
correctly after it is changed.
Table 4-4. Watchdog Timer Lock
BODPD[1:0] Description
00 Reserved
01 BOD enabled in sampled mode
10 BOD enabled continuously
11 BOD disabled
Bit 7 6 5 4 3 2 1 0
+0x04 – – RSTDISBL STARTUPTIME[1:0] WDLOCK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1
STARTUPTIME[1:0] 1kHz ULP oscillator cycles
00 64
01 4
10 Reserved
11 0
WDLOCK Description
0Watchdog timer locked for modifications
1Watchdog timer not locked
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Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to one
when this register is written.
4.14.4 FUSEBYTE5 – Fuse Byte 5
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
one when this register is written.
Bit 5:4 – BODACT[1:0]: BOD Operation in Active Mode
These fuse bits set the BOD operation mode when the device is in active and idle modes. For details on the BOD
and BOD operation modes, refer to “Brownout Detection” on page 122.
Table 4-5. BOD Operation Modes in Active and Idle Modes
Bit 3 – EESAVE: EEPROM Preserved through the Chip Erase
A chip erase command will normally erase the flash, EEPROM, and internal SRAM. If this fuse is programmed, the
EEPROM is not erased during chip erase. This is useful if EEPROM is used to store data independently of the
software revision.
Table 4-6. EEPROM Preserved Through Chip Erase
Changes to the EESAVE fuse bit take effect immediately after the write timeout elapses. Hence, it is possible to
update EESAVE and perform a chip erase according to the new setting of EESAVE without leaving and reentering
programming mode.
Bit 2:0 – BODLEVEL[2:0]: Brownout Detection Voltage Level
These fuse bits sets the BOD voltage level. Refer to “Reset Sequence” on page 121 for details. For BOD level
nominal values, see Table 9-2 on page 123.
Bit 7 6 5 4 3 2 1 0
+0x05 BODACT[1:0] EESAVE BODLEVEL[2:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 –– –
BODACT[1:0] Description
00 Reserved
01 BOD enabled in sampled mode
10 BOD enabled continuously
11 BOD disabled
EESAVE Description
0EEPROM is preserved during chip erase
1EEPROM is erased during chip erase
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4.14.5 FUSEBYTE6 – Fuse Byte 6
Bit 7 – FDACT5: Fault Detection Action Timer/Counter 5
This fuse sets the fault detection action on Px4 and Px5 port pins during the Reset phase, which are the default
output pins for timer/counter 5 output compare channels. Table 4-7 on page 33 shows the possible settings.
Bit 6 – FDACT4: Fault Detection Action Timer/Counter 4
This fuse sets the fault detection action on Px0 to Px3 port pins during the Reset phase, which are the default out-
put pins for timer/counter 4 output compare channels. Table 4-7 on page 33 shows the possible settings.
Table 4-7. Fault Detection Action
Bit 5:0 – VALUE[5:0]: Port Pin n Value
These fuses select the value that will be output on the corresponding port pin when an emergency fault occurs and
if the corresponding FDACT fuse is set.
Table 4-8. Port Pin Value
4.14.6 LOCKBITS – Lock Bit Register
Bit 7:6 – BLBB[1:0]: Boot Lock Bit Boot Loader Section
These lock bits control the software security level for accessing the boot loader section. The BLBB bits can only be
written to a more strict locking. Resetting the BLBB bits is possible only by executing a chip erase command.
Bit 7 6 5 4 3 2 1 0
+0x06 FDACT5 FDACT4 VALUE[5:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1
FDACT Description
0In reset state and until a timer/counter compare channel is enabled, the port pins are forced to the value set in
the corresponding VALUEn fuse.
1Default I/O pin configuration.
VALUEn Description
0The corresponding port pin output value is set to 1 (high level).
1The corresponding port pin output value is set to 0 (low level).
Bit 76543210
+0x07 BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value11111111
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Table 4-9. Boot Lock Bit for the Boot Loader Section
Bit 5:4 – BLBA[1:0]: Boot Lock Bit Application Section
These lock bits control the software security level for accessing the application section. The BLBA bits can only be
written to a more strict locking. Resetting the BLBA bits is possible only by executing a chip erase command.
Table 4-10. Boot Lock Bit for the Application Section
Bit 3:2 – BLBAT[1:0]: Boot Lock Bit Application Table Section
These lock bits control the software security level for accessing the application table section for software access.
The BLBAT bits can only be written to a more strict locking. Resetting the BLBAT bits is possible only by executing
a chip erase command.
BLBB[1:0] Group configuration Description
11 NOLOCK No lock – no restrictions for SPM and (E)LPM accessing the boot loader section.
10 WLOCK Write lock – SPM is not allowed to write the boot loader section.
01 RLOCK
Read lock – (E)LPM executing from the application section is not allowed to
read from the boot loader section.
If the interrupt vectors are placed in the application section, interrupts are
disabled while executing from the boot loader section.
00 RWLOCK
Read and write lock – SPM is not allowed to write to the boot loader section, and
(E)LPM executing from the application section is not allowed to read from the
boot loader section.
If the interrupt vectors are placed in the application section, interrupts are
disabled while executing from the boot loader section.
BLBA[1:0] Group configuration Description
11 NOLOCK No Lock - no restrictions for SPM and (E)LPM accessing the application section.
10 WLOCK Write lock – SPM is not allowed to write the application section.
01 RLOCK
Read lock – (E)LPM executing from the boot loader section is not allowed to
read from the application section.
If the interrupt vectors are placed in the boot loader section, interrupts are
disabled while executing from the application section.
00 RWLOCK
Read and write lock – SPM is not allowed to write to the application section, and
(E)LPM executing from the boot loader section is not allowed to read from the
application section.
If the interrupt vectors are placed in the boot loader section, interrupts are
disabled while executing from the application section.
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Table 4-11. Boot Lock Bit for the Application Table Section
Bit 1:0 – LB[1:0]: Lock Bits(1)
These lock bits control the security level for the flash and EEPROM during external programming. These bits are
writable only through an external programming interface. Resetting the lock bits is possible only by executing a
chip erase command. All other access; using the TIF and OCD, is blocked if any of the Lock Bits are written to 0.
These bits do not block any software access to the memory.
Table 4-12. Lock Bit Protection Mode
Note: 1. Program the Fuse bits and Boot Lock bits before programming the Lock Bits.
BLBAT[1:0] Group configuration Description
11 NOLOCK No lock – no restrictions for SPM and (E)LPM accessing the application table
section.
10 WLOCK Write lock – SPM is not allowed to write the application table
01 RLOCK
Read lock – (E)LPM executing from the boot loader section is not allowed to
read from the application table section.
If the interrupt vectors are placed in the boot loader section, interrupts are
disabled while executing from the application section.
00 RWLOCK
Read and write lock – SPM is not allowed to write to the application table
section, and (E)LPM executing from the boot loader section is not allowed to
read from the application table section.
If the interrupt vectors are placed in the boot loader section, interrupts are
disabled while executing from the application section.
LB[1:0] Group configuration Description
11 NOLOCK3 No lock – no memory locks enabled.
10 WLOCK
Write lock – programming of the flash and EEPROM is disabled for the
programming interface. Fuse bits are locked for write from the programming
interface.
00 RWLOCK
Read and write lock – programming and read/verification of the flash and
EEPROM are disabled for the programming interface. The lock bits and fuses
are locked for read and write from the programming interface.
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4.15 Register Description – Production Signature Row
Note: The initial value for these registers will read as 0xFFFF if production calibration is not done.
4.15.1 RCOSC8M – Internal 8MHz Oscillator Calibration Register
Bit 7:0 – RCOSC8M[7:0]: Internal 8MHz Oscillator Calibration Value
This byte contains the oscillator calibration value for the internal 8MHz oscillator. Calibration of the oscillator is per-
formed during production testing of the device. During reset, this value is automatically loaded into calibration
register for the 8MHz oscillator. Refer to “RC8MCAL – 8MHz Internal Oscillator Calibration Register” on page 108
for more details.
4.15.2 RCOSC32K – Internal 32.768kHz Oscillator Calibration Register
Bit 7:0 – RCOSC32K[7:0]: Internal 32.768kHz Oscillator Calibration Value
This byte contains the oscillator calibration value for the internal 32.768kHz oscillator. Calibration of the oscillator
is performed during production testing of the device. During reset, this value is automatically loaded into the cali-
bration register for the 32.768kHz oscillator. Refer to “RC32KCAL – 32kHz Oscillator Calibration Register” on page
107 for more details.
4.15.3 RCOSC32M – Internal 32MHz Oscillator Calibration Register
Bit 7:0 – RCOSC32M[7:0]: Internal 32MHz Oscillator Calibration Value
This byte contains the oscillator calibration value for the internal 32MHz oscillator. Calibration of the oscillator is
performed during production testing of the device. During reset, this value is automatically loaded into calibration
register B for the 32MHz DFLL. Refer to “CALB – DFLL Calibration Register B” on page 109 for more details.
4.15.4 RCOSC32MA – Internal 32MHz RC Oscillator Calibration Register
Bit 7:0 – RCOSC32MA[7:0]: Internal 32MHz Oscillator Calibration Value
This byte contains the oscillator calibration value for the internal 32MHz oscillator. Calibration of the oscillator is
performed during production testing of the device. During reset, this value is automatically loaded into calibration
register A for the 32MHz DFLL. Refer to “CALA – DFLL Calibration Register A” on page 109 for more details.
Bit 7654 3 2 1 0
+0x00 RCOSC8M[7:0]
Read/Write RRRR R R R R
Initial value x x x x x x x x
Bit 7654 3 2 1 0
+0x02 RCOSC32K[7:0]
Read/Write RRRR R R R R
Initial value x x x x x x x x
Bit 7 6 5 4 3 2 1 0
+0x03 RCOSC32M[7:0]
Read/Write R R R R R R R R
Initial valuexxxx x x x x
Bit 7 6 5 4 3 2 1 0
+0x04 RCOSC32MA[7:0]
Read/Write R R R R R R R R
Initial value x x x x x x x x
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4.15.5 LOTNUM0 – Lot Number Register 0
LOTNUM0, LOTNUM1, LOTNUM2, LOTNUM3, LOTNUM4, and LOTNUM5 contain the lot number for each device.
Together with the wafer number and wafer coordinates, this gives a serial number for the device.
Bit 7:0 – LOTNUM0[7:0]: Lot Number Byte 0
This byte contains byte 0 of the lot number for the device.
4.15.6 LOTNUM1 – Lot Number Register 1
Bit 7:0 – LOTNUM1[7:0]: Lot Number Byte 1
This byte contains byte 1 of the lot number for the device.
4.15.7 LOTNUM2 – Lot Number Register 2
Bit 7:0 – LOTNUM2[7:0]: Lot Number Byte 2
This byte contains byte 2 of the lot number for the device.
4.15.8 LOTNUM3- Lot Number Register 3
Bit 7:0 – LOTNUM3[7:0]: Lot Number Byte 3
This byte contains byte 3 of the lot number for the device.
4.15.9 LOTNUM4 – Lot Number Register 4
Bit 7:0 – LOTNUM4[7:0]: Lot Number Byte 4
This byte contains byte 4 of the lot number for the device.
Bit 7654 3 2 1 0
+0x08 LOTNUM0[7:0]
Read/Write RRRR R R R R
Initial value x x x x x x x x
Bit 7 6 5 4 3 2 1 0
+0x09 LOTNUM1[7:0]
Read/Write R R R R R R R R
Initial valuexxxx x x x x
Bit 7 6 5 4 3 2 1 0
+0x0A LOTNUM2[7:0]
Read/Write R R R R R R R R
Initial value x x x x x x x x
Bit 7654 3 2 1 0
+0x0B LOTNUM3[7:0]
Read/Write RRRR R R R R
Initial value x x x x x x x x
Bit 7 6 5 4 3 2 1 0
+0x0C LOTNUM4[7:0]
Read/Write R R R R R R R R
Initial value x x x x x x x x
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4.15.10 LOTNUM5 – Lot Number Register 5
Bit 7:0 – LOTNUM5[7:0]: Lot Number Byte 5
This byte contains byte 5 of the lot number for the device.
4.15.11 WAFNUM – Wafer Number Register
Bit 7:0 – WAFNUM[7:0]: Wafer Number
This byte contains the wafer number for each device. Together with the lot number and wafer coordinates, this
gives a serial number for the device.
4.15.12 COORDX0 – Wafer Coordinate X Register 0
COORDX0, COORDX1, COORDY0, and COORDY1 contain the wafer X and Y coordinates for each device. Together
with the lot number and wafer number, this gives a serial number for each device.
Bit 7:0 – COORDX0[7:0]: Wafer Coordinate X Byte 0
This byte contains byte 0 of wafer coordinate X for the device.
4.15.13 COORDX1 – Wafer Coordinate X Register 1
Bit 7:0 – COORDX0[7:0]: Wafer Coordinate X Byte 1
This byte contains byte 1 of wafer coordinate X for the device.
4.15.14 COORDY0 – Wafer Coordinate Y Register 0
Bit 7:0 – COORDY0[7:0]: Wafer Coordinate Y Byte 0
This byte contains byte 0 of wafer coordinate Y for the device.
Bit 7 6 5 4 3 2 1 0
+0x0D LOTNUM5[7:0]
Read/Write R R R R R R R R
Initial value x x x x x x x x
Bit 7654 3 2 1 0
+0x10 WAFNUM[7:0]
Read/Write RRRR R R R R
Initial value 0 0 0 x x x x x
Bit 7654 3 2 1 0
+0x12 COORDX0[7:0]
Read/Write RRRR R R R R
Initial value x x x x x x x x
Bit 7 6 5 4 3 2 1 0
+0x13 COORDX1[7:0]
Read/Write R R R R R R R R
Initial valuexxxx x x x x
Bit 7654 3 2 1 0
+0x14 COORDY0[7:0]
Read/Write R R R R R R R R
Initial valuexxxx x x x x
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4.15.15 COORDY1 – Wafer Coordinate Y Register 1
Bit 7:0 – COORDY1[7:0]: Wafer Coordinate Y Byte 1
This byte contains byte 1 of wafer coordinate Y for the device.
4.15.16 ROOMTEMP – Room Temperature Register
.
Bit 7:0 – ROOMTEMP[7:0]: Room Temperature Value
This byte contains the room temperature value.
4.15.17 HOTTEMP – Hot Temperature Register
.
Bit 7:0 – HOTTEMP[7:0]: Hot Temperature Value
This byte contains the hot temperature value.
4.15.18 ADCACAL0 – ADCA Calibration Register 0
ADCACAL0 and ADCACAL1 contain the calibration value for the analog- to -digital converter A (ADCA). Calibration is
done during production testing of the device. The calibration bytes are not loaded automatically into the ADC calibration
registers, and so this must be done from software.
Bit 7:0 – ADCACAL0[7:0]: ADCA Calibration Byte 0
This byte contains byte 0 of the ADCA calibration data, and must be loaded into the ADCA CALL register.
4.15.19 ADCACAL1 – ADCA Calibration Register 1
Bit 7:0 – ADCACAL1[7:0]: ADCA Calibration Byte 1
This byte contains byte 1 of the ADCA calibration data.
Bit 7 6 5 4 3 2 1 0
+0x15 COORDY1[7:0]
Read/Write R R R R R R R R
Initial valuexxxx x x x x
Bit 7654 3 2 1 0
+0x1E ROOMTEMP[7:0]
Read/Write R R R R R R R R
Initial value x x x x x x x x
Bit 7654 3 2 1 0
+0x1F HOTTEMP[7:0]
Read/Write R R R R R R R R
Initial value x x x x x x x x
Bit 7 6 5 4 3 2 1 0
+0x20 ADCACAL0[7:0]
Read/Write R R R R R R R R
Initial valuexxxx x x x x
Bit 7 6 5 4 3 2 1 0
+0x21 ADCACAL1[7:0]
Read/Write R R R R R R R R
Initial valuexxxx x x x x
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4.15.20 ACACURRCAL – ACA Current Calibration Register
Bit 7:0 – ACACURRCAL[7:0]: ACA Current Calibration Byte
This byte contains the ACA current source calibration value, and must be loaded into the ACA CURRCALIB
register.
4.15.21 TEMPSENSE2 – Temperature Sensor Calibration Register 2
TEMPSENSE2 and TEMPSENSE3 contain the 12-bit ADCA value from a temperature measurement done with the
internal temperature sensor. The measurement is done in production testing at room temperature, and can be used for
single- or multi-point temperature sensor calibration.
Bit 7:0 – TEMPSENSE2[7:0]: Temperature Sensor Calibration Byte 2
This byte contains the byte 2 of the temperature measurement.
4.15.22 TEMPSENSE3 – Temperature Sensor Calibration Register 3
Bit 7:0 – TEMPSENSE3[7:0]: Temperature Sensor Calibration Byte 3
This byte contains byte 3 of the temperature measurement.
4.15.23 TEMPSENSE0 – Temperature Sensor Calibration Register 0
TEMPSENSE0 and TEMPSENSE1 contain the 12-bit ADCA value from a temperature measurement done with the
internal temperature sensor. The measurement is done in production testing at 85C, and can be used for single- or
multi-point temperature sensor calibration.
Bit 7:0 – TEMPSENSE0[7:0]: Temperature Sensor Calibration Byte 0
This byte contains the byte 0 of the temperature measurement.
Bit 7 6 5 4 3 2 1 0
+0x28 ACACURRCAL[7:0]
Read/Write R R R R R R R R
Initial value 0 0 0 0 x x x x
Bit 7654 3 2 1 0
+0x2C TEMPSENSE2[7:0]
Read/Write R R R R R R R R
Initial value x x x x x x x x
Bit 7654 3 2 1 0
+0x2D TEMPSENSE3[7:0]
Read/Write R R R R R R R R
Initial value 0 0 0 0 x x x x
Bit 7654 3 2 1 0
+0x2E TEMPSENSE0[7:0]
Read/Write R R R R R R R R
Initial value x x x x x x x x
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4.15.24 TEMPSENSE1 – Temperature Sensor Calibration Register 1
Bit 7:0 – TEMPSENSE1[7:0]: Temperature Sensor Calibration Byte 1
This byte contains byte 1 of the temperature measurement.
4.15.25 DACA0OFFCAL – DACA Offset Calibration Register
Bit 7:0 – DACA0OFFCAL[7:0]: DACA0 Offset Calibration Byte
This byte contains the offset calibration value for channel 0 in the digital -to -analog converter A (DACA). Calibra-
tion is done during production testing of the device. The calibration byte is not loaded automatically into the DAC
channel 0 offset calibration register, so this must be done from software.
4.15.26 DACA0GAINCAL – DACA Gain Calibration Register
Bit 7:0 – DACA0GAINCAL[7:0]: DACA0 Gain Calibration Byte
This byte contains the gain calibration value for channel 0 in the digital -to -analog converter A (DACA). Calibration
is done during production testing of the device. The calibration byte is not loaded automatically into the DAC gain
calibration register, so this must be done from software.
4.15.27 DACA1OFFCAL – DACA Offset Calibration Register
Bit 7:0 – DACA1OFFCAL[7:0]: DACA1 Offset Calibration Byte
This byte contains the offset calibration value for channel 1 in the digital- to -analog converter A (DACA). Calibra-
tion is done during production testing of the device. The calibration byte is not loaded automatically into the DAC
channel 1 offset calibration register, so this must be done from software.
Bit 7654 3 2 1 0
+0x2F TEMPSENSE1[7:0]
Read/Write R R R R R R R R
Initial value 0 0 0 0 x x x x
Bit 7654 3 2 1 0
+0x30 DACA0OFFCAL[7:0]
Read/Write R R R R R R R R
Initial value 0 0 0 0 x x x x
Bit 76543 210
+0x31 DACA0GAINCAL[7:0]
Read/Write R R R R R R R R
Initial value 0 0 0 0 x x x x
Bit 7654 3 2 1 0
+0x34 DACA1OFFCAL[7:0]
Read/Write R R R R R R R R
Initial value 0 0 0 0 x x x x
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4.15.28 DACA1GAINCAL – DACA Gain Calibration Register
Bit 7:0 – DACA1GAINCAL[7:0]: DACA1 Gain Calibration Byte
This byte contains the gain calibration value for channel 1 in the digital -to- analog converter A (DACA). Calibration
is done during production testing of the device. The calibration byte is not loaded automatically into the DAC chan-
nel 1 gain calibration register, so this must be done from software.
4.16 Register Description – General Purpose I/O Memory
4.16.1 GPIORn – General Purpose I/O Register n
These are general purpose registers that can be used to store data, such as global variables and flags, in the bit-
accessible I/O memory space.
4.17 Register Descriptions – MCU Control
4.17.1 DEVID0 – Device ID Register 0
DEVID0, DEVID1, and DEVID2 contain the byte identification that identifies each microcontroller device type.
For details on the actual ID, refer to the device datasheet.
Bit 7:0 – DEVID0[7:0]: Device ID Byte 0
Byte 0 of the device ID. This byte will always be read as 0x1E. This indicates that the device is manufactured by
Atmel.
4.17.2 DEVID1 – Device ID Register 1
Bit 7:0 – DEVID[7:0]: Device ID Byte 1
Byte 1 of the device ID indicates the flash size of the device.
Bit 76543 210
+0x35 DACA1GAINCAL[7:0]
Read/Write R R R R R R R R
Initial value 0 0 0 0 x x x x
Bit 76543210
+n GPIORn[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 76543210
+0x00 DEVID0[7:0]
Read/Write R R R RRRRR
Initial value00011110
Bit 76543210
+0x01 DEVID1[7:0]
Read/Write RRRRRRRR
Initial value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
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4.17.3 DEVID2 – Device ID Register 2
Bit 7:0 – DEVID2[7:0]: Device ID Byte 2
Byte 2 of the device ID indicates the device number.
4.17.4 REVID – Revision ID
Bit 7:4 – Reserved
These bits are unused and reserved for future use.
Bit 3:0 – REVID[3:0]: Revision ID
These bits contains the device revision. 0 = A, 1 = B, and so on.
4.17.5 ANAINIT – Analog Initialization Register
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:2 / 1:0 – STARTUPDLYx[1:0]: Analog Start-up Delay
Setting these bits enables sequential start of the internal components used for the ADC, DAC, and analog compar-
ator with the main input/output connected to that port. When this is done, the internal components, such as voltage
reference and bias currents, are started sequentially when the module is enabled. This reduces the peak current
consumption during startup of the module. For maximum effect, the start-up delay should be set so that it is larger
than 0.5µs.
Table 4-13. Analog Start-up Delay
Bit 76543210
+0x02 DEVID2[7:0]
Read/Write R R R RRRRR
Initial value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
Bit 76543210
+0x03 –––– REVID[3:0]
Read/Write R R R R R R R R
Initial value 0 0 0 0 1/0 1/0 1/0 1/0
Bit 76543210
+0x07 ––– STARTUPDLYD[1:0] STARTUPDLYA[1:0]
Read/Write R R R R R/W R/W R/W R/W
Initial value00000000
STARTUPDLYx Group configuration Description
00 NONE Direct startup
11 2CLK 2 * ClkPER
10 8CLK 8 * ClkPER
11 32CLK 32 * ClkPER
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4.17.6 EVSYSLOCK – Event System Lock Register
Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 4 – EVSYS1LOCK: Event System Channel 4-7 Lock
Setting this bit will lock all registers in the event system related to event channels 4 to 7against for further modifica-
tion. The following registers in the event system are locked: CH4MUX, CH4CTRL, CH5MUX, CH5CTRL,
CH6MUX, CH6CTRL, CH7MUX, and CH7CTRL. This bit is protected by the configuration change protection
mechanism. For details, refer to “Configuration Change Protection” on page 13.
Bit 3:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – EVSYS0LOCK: Event System Channel 0-3 Lock
Setting this bit will lock all registers in the event system related to event channels 0 to 3 for against further modifi-
cation. The following registers in the event system are locked: CH0MUX, CH0CTRL, CH1MUX, CH1CTRL,
CH2MUX, CH2CTRL, CH3MUX, and CH3CTRL. This bit is protected by the configuration change protection
mechanism. For details, refer to “Configuration Change Protection” on page 13.
4.17.7 WEXLOCK – Waveform Extension Lock Register
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – WEXCLOCK: Waveform Extension Port C Lock
Setting this bit will lock all protected registers in the WEX module extension on port C, against further modification.
This bit is protected by the configuration change protection mechanism.
For details, refer to “Configuration Change Protection” on page 13.
Bit 765 4 321 0
+0x08 –– EVSYS1LOCK – – – EVSYS0LOCK
Read/Write R R R R/W R R R R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7654321 0
+0x09 ––––––– WEXCLOCK
Read/Write RRRRRRR R/W
Initial value0000000 0
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4.17.8 FAULTLOCK – Fault Extension Lock Register
Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 1 – FAULTC5LOCK: Fault Lock for Timer/Counter 5 on Port C
Setting this bit will lock all protected registers in the FAULT module extension on port C of the timer/counter 5,
against further modification. This bit is protected by the configuration change protection mechanism.
For details refer to “Configuration Change Protection” on page 13.
Bit 0 – FAULTC4LOCK: Fault Lock for Timer/Counter 4 on Port C
Setting this bit will lock all protected registers in the FAULT module extension on port C of the timer/counter 4,
against further modification. This bit is protected by the configuration change protection mechanism.
For details refer to “Configuration Change Protection” on page 13.
Bit 765432 1 0
+0x03 ––––– FAULTC5LOCK FAULTC4LOCK
Read/Write R R R R R R R R
Initial value000000 0 0
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4.18 Register Summary – NVM Controller
4.19 Register Summary – Fuses and Lockbits
4.20 Register Summary – Production Signature Row
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 ADDR0 Address Byte 0 26
+0x01 ADDR1 Address Byte 1 26
+0x02 ADDR2 Address byte 2 26
+0x03 Reserved - - - - - - - -
+0x04 DATA0 Data byte 0 26
+0x05 DATA1 Data byte 1 27
+0x06 DATA2 Data byte 2 27
+0x07 Reserved - - - - - - - -
+0x08 Reserved - - - - - - - -
+0x09 Reserved - - - - - - - -
+0x0A CMD - CMD[6:0] 27
+0x0B CTRLA - - - - - - -CMDEX27
+0x0C CTRLB - - - - - - EPRM SPMLOCK 28
+0x0D INTCTRL - --- SPMLVL[1:0] EELVL[1:0] 28
+0x0E Reserved - - - - - - - -
+0x0F STATUS NVMBUSY FBUSY ---- EELOAD FLOAD 29
+0x10 LOCKBITS BLBB1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] 29
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 Reserved - - - - - - - -
+0x01 FUSEBYTE1 WDWPER[3:0] WDPER[3:0] 30
+0x02 FUSEBYTE2 -BOOTRST---- BODPD[1:0] 30
+0x03 Reserved - - - - - - - -
+0x04 FUSEBYTE4 - - - RSTDISBL STARTUPTIME[1:0] WDLOCK -31
+0x05 FUSEBYTE5 -- BODACT[1:0] EESAVE BODLEVEL[2:0] 32
+0x06 FUSEBYTE6 FDACT5 FDACT4 VALUE[5:0] 33
+0x07 LOCKBITS BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] 33
Address Auto Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 3 Bit 1 Bit 0 Page
+0x00 YES RCOSC8M RCOSC8M[7:0] 36
+0x01 Reserved - - - - - - - -
+0x02 YES RCOSC32K RCOSC32K[7:0] 36
+0x03 YES RCOSC32M RCOSC32M[7:0] 36
+0x04 YES RCOSC32MA RCOSC32MA[7:0] 36
+0x05 Reserved - - - - - - - -
+0x06 Reserved - - - - - - - -
+0x07 Reserved - - - - - - - -
+0x08 NO LOTNUM0 LOTNUM0 [7:0] 37
+0x09 NO LOTNUM1 LOTNUM1 [7:0] 37
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+0x0A NO LOTNUM2 LOTNUM2 [7:0] 37
+0x0B NO LOTNUM3 LOTNUM3 [7:0] 37
+0x0C NO LOTNUM4 LOTNUM4 [7:0] 37
+0x0D NO LOTNUM5 LOTNUM5 [7:0] 38
+0x0E Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
+0x10 NO WAFNUM WAFNUM [7:0] 38
+0x11 Reserved - - - - - - - -
+0x12 NO COORDX0 COORDX0 [7:0] 38
+0x13 NO COORDX1 COORDX1 [7:0] 38
+0x14 NO COORDY0 COORDY0 [7:0] 38
+0x15 NO COORDY1 COORDY1 [7:0] 39
+0x16 Reserved - - - - - - - -
+0x17 Reserved - - - - - - - -
+0x18 Reserved - - - - - - - -
+0x19 Reserved - - - - - - - -
+0x1A Reserved - - - - - - - -
+0x1B Reserved - - - - - - - -
+0x1C Reserved - - - - - - - -
+0x1D Reserved - - - - - - - -
+0x1E NO ROOMTEMP ROOMTEMP[7:0] 39
+0x1F NO HOTTEMP HOTTEMP[7:0] 39
+0x20 NO ADCACAL0 ADCACAL0[7:0] 39
+0x21 NO ADCACAL1 ADCACAL1[7:0] 39
+0x22 Reserved - - - - - - - -
+0x23 Reserved - - - - - - - -
+0x24 Reserved - - - - - - - -
+0x25 Reserved - - - - - - - -
+0x26 Reserved - - - - - - - -
+0x27 Reserved - - - - - - - -
+0x28 NO ACACURRCAL ACACURRCAL[7:0] 40
+0x29 Reserved - - - - - - - -
+0x2A Reserved - - - - - - - -
+0x2B Reserved - - - - - - - -
+0x2C NO TEMPSENSE2 TEMPSENSE2[7:0] 40
+0x2D NO TEMPSENSE3 - - - - TEMPSENSE3[11:8] 40
+0x2E NO TEMPSENSE0 TEMPSENSE0[7:0] 40
+0x2F NO TEMPSENSE1 - - - - TEMPSENSE1[11:8] 41
+0x30 NO DACA0OFFCAL DACA0OFFCAL[7:0] 41
+0x31 NO DACA0GAINCAL DACA0GAINCAL[1:0] 41
+0x32 Reserved - - - - - - - -
+0x33 Reserved - - - - - - - -
Address Auto Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 3 Bit 1 Bit 0 Page
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+0x34 NO DACA1OFFCAL DACA1OFFCAL[7:0] 41
+0x35 NO DACA1GAINCAL DACA1GAINCAL[7:0] 42
+0x36 Reserved - - - - - - - -
+0x37 Reserved - - - - - - - -
+0x38 Reserved - - - - - - - -
+0x39 Reserved - - - - - - - -
+0x3A Reserved - - - - - - - -
+0x3B Reserved - - - - - - - -
+0x3C Reserved - - - - - - - -
+0x3D Reserved - - - - - - - -
+0x3E Reserved - - - - - - - -
+0x3F Reserved - - - - - - - -
Address Auto Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 3 Bit 1 Bit 0 Page
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4.21 Register Summary – General Purpose I/O Registers
4.22 Register Summary – MCU Control
4.23 Interrupt Vector Summary
Table 4-14. NVM Interrupt vectors and their word offset address from NVM controller interrupt base.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 GPIOR0 GPIOR0[7:0] 42
+0x01 GPIOR1 GPIOR1[7:0] 42
+0x02 GPIOR2 GPIOR2[7:0] 42
+0x03 GPIOR3 GPIOR3[7:0] 42
+0x04 Reserved - - - - - - - -
+0x05 Reserved - - - - - - - -
+0x06 Reserved - - - - - - - -
+0x07 Reserved - - - - - - - -
+0x08 Reserved - - - - - - - -
+0x09 Reserved - - - - - - - -
+0x0A Reserved - - - - - - - -
+0x0B Reserved - - - - - - - -
+0x0C Reserved - - - - - - - -
+0x0D Reserved - - - - - - - -
+0x0E Reserved - - - - - - - -
+0x0F Reserved - - - - - - - -
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 DEVID0 DEVID0[7:0] 42
+0x01 DEVID1 DEVID1[7:0] 42
+0x02 DEVID2 DEVID2[7:0] 43
+0x03 REVID - - - - REVID[7:0] 43
+0x04 Reserved - - - - - - - -
+0x05 Reserved - - - - - - - -
+0x06 Reserved - - - - - - - -
+0x07 ANAINIT - - - - STARTUPDLYD[1:0] STARTUPDLYA[1:0] 43
+0x08 EVSYSLOC - - - EVSYS1LOCK - - - EVSYS0LOCK 44
+0x09 WEXLOCK - - - - - - - WEXCLOCK 44
+0x0A FAULTLOCK - - - - - - FAULTC5LOC FAULTC4LOC 45
+0x0B Reserved - - - - - - - -
Offset Source Interrupt description
0x00 EE_vect Nonvolatile memory EEPROM interrupt vector
0x02 SPM_vect Nonvolatile memory SPM interrupt vector
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5. EDMA – Enhanced Direct Memory Access
5.1 Features
The EDMA Controller allows data transfers with minimal CPU intervention
From data memory to data memory
From data memory to peripheral
From peripheral to data memory
From peripheral to peripheral
Four peripheral EDMA channels with separate:
Transfer triggers
Interrupt vectors
Addressing modes
Data match
Up to two standard EDMA with separate:
Transfer triggers
Interrupt vectors
Addressing modes
Data search
Programmable channel priority
From 1 byte to 128KB of data in a single transaction
Up to 64K block transfer with repeat
1 or 2 bytes burst transfers
Multiple addressing modes
Static
Increment
Optional reload of source and destination address at the end of each
Burst
Block
Transaction
Optional Interrupt on end of transaction
Optional connection to CRC Generator module for CRC on EDMA data
5.2 Overview
The enhanced direct memory access (EDMA) controller can transfer data between memories and peripherals, and thus
off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four EDMA channels enable up to four independent and parallel transfers.
The EDMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the EDMA controller can handle automatic transfer of data to/from
communication modules. The EDMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1 or 2 bytes. They build block transfers of configurable size from 1 byte to
64KB. Repeat option can be used to repeat once each block transfer for single transactions up to 128KB. Source and
destination addressing can be static or incremental. Automatic reload of source and/or destination addresses can be
done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and events
can trigger EDMA transfers.
The EDMA channels have individual configuration and control settings. This includes source or destination pointers,
transfer triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when
a transaction is complete or when the EDMA controller detects an error on an EDMA channel.
To have flexibility in transfers, channels can be interlinked so that the second takes over the transfer when the first is
finished.
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The EDMA controller supports extended features such as double buffering, data match for peripherals or data search for
SRAM or EEPROM.
The EDMA controller supports two types of channel. Each channel type can be selected individually.
5.2.1 Peripheral Channel
In peripheral channel configuration, a channel enables transfer from specific peripheral address to memory locations or
from memory locations to specific peripheral address. The specific peripheral address is provided by the selected trigger
source. In this configuration, up to four independent and parallel transfers are supported. The size of a block transfer is
limited to 256 bytes for each peripheral channel. The repeat feature enables transfers up to 512 bytes. Two channels can
be interlinked so that the second takes over the transfer when the first is finished.
In data match configuration, the EDMA compares the input data from the programmable source with a pattern contained
in an EDMA register. As example, this mode can be used with serial peripherals to enable the transfer only if specific
character/frame is received (ex. serial address field). Optionally, the transfer counter can be enabled to allow recognition
within a window.
Figure 5-1. EDMA – Full Peripheral Channel Mode Overview
5.2.2 Standard Channel
To create a standard channel, the EDMA controller uses resources of two peripheral channels. Register addresses are
re-arranged and the standard channel 0 is configured with resources found in the peripheral channels 0 and 1, the
standard channel 2 is configured with resources found in the peripheral channels 2 and 3.
In standard channel configuration, any transfer type can be enabled. The trigger source, source address and destination
address are independent and separately programmable. The size of a block transfer can be set up to 65536 bytes (64K)
for each standard channel. The repeat option enables transfers up to 131072 bytes (128K). Two channels can be
interlinked so that the second takes over the transfer when the first is finished, and vice versa.
In data search configuration, the EDMA searches for the data (8-bit or 16-bit) contained in an EDMA register within a
memory buffer. On a match, the source address register will provide to the user the intended data pointer.
R/W Master port
Arbitration
BUF
Bus
matrix
Arbiter
Read
Write
Slave port
Read /
Write
CTRL
EDMA Peripheral Channel 1
EDMA Peripheral Channel 2
EDMA Peripheral Channel 3
EDMA trigger / Event
EDMA Peripheral Channel 0
MEMADDR
TRFCNT
(PeriphAddr)
TRIGSRC
Enable
Burst
CTRLA
CTRLB
Control Logic
Repeat
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Figure 5-2. EDMA – Full Standard Channel Mode Overview
5.2.3 Channel Combinations
The EDMA can be configured in four different modes (CHMODE bits in “CTRL – Control Register ” on page 59) mixing
peripheral and standard channels.
Figure 5-3. EDMA – Channel Modes
5.3 EDMA Transaction
Figure 5-4. EDMA Transaction
R/W Master port
Arbitration
BUF
Bus
matrix
Arbiter
Read
Write
Slave port
Read /
Write
CTRL
EDMA Standard Channel 2
EDMA trigger / Event
EDMA Standard Channel 0
DESTADDR
TRFCNT
TRIGSRC
Enable
Burst
CTRLA
CTRLB
Control Logic
Repeat
SRCADDR
PER 0123 Conf. STD0 Conf. STD2 Conf. STD02 Conf.
Per-Ch0
Per-Ch1
Per-Ch2
Per-Ch3
Std-Ch0
Per-Ch2
Per-Ch3
Per- Ch0
Per- Ch1
Std-Ch2 Std-Ch2
Std-Ch0
4 peripheral channels
1 standard channel
2 peripheral channels
2 peripheral channels
1 standard channel 2 standard channels
2-byte burst mode Block size: 6 bytesRepeat Block transfer
EDMA transaction
Block transferBlock transfer
Burst transfer Burst transfer Burst transfer
Trig. (Trig.) (Trig.) (Trig.) (Trig.) (Trig.) TRNIF
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A complete EDMA read and write operation between memories and/or peripherals is called an EDMA transaction. A
transaction is done in data blocks, and the size of the transaction (number of bytes to transfer) is selectable from
software and controlled by the block size and repeat bit settings. Each block transfer is divided into bursts.
5.3.1 Block Transfer and Repeat Block Transfer
The size of the block transfer is set by the block transfer count register, and can be programmed from 1 byte to 64KB. If
the double buffering is not used, a repeat option can be enabled to repeat once a block transfer before a transaction is
complete.
5.3.2 Burst Transfer
Since the AVR CPU and EDMA controller use the same data buses, a block transfer is divided into smaller burst
transfers. The burst transfer is selectable to 1 or 2 bytes. This means that if a transfer request is pending and the EDMA
acquires the data bus, it will occupy the bus until all bytes in the burst are transferred.
A bus arbiter controls when the EDMA controller and the AVR CPU can use the bus. The CPU always has priority, and
so as long as the CPU requests access to the bus, any pending burst transfer must wait. The CPU requests bus access
when it executes an instruction that writes or reads data to SRAM, I/O memory or to the EEPROM. For more details on
memory access bus arbitration refer to.
5.4 Transfer Triggers
EDMA transfers can be started only when an EDMA transfer trigger is detected. A transfer trigger can be set-up by
software, from an external trigger source (peripheral), or from an event. There are dedicated source trigger selections for
each EDMA channel. The available trigger sources may vary from device to device, depending on the modules or
peripherals that exist in the device. Using a transfer trigger for a module or peripherals that does not exist will have no
effect. For a list of all transfer triggers of peripheral channels, refer to Table 5-8 on page 64 and for standard channels,
refer to Table 5-18 on page 71.
By default, a trigger starts a block transfer operation. When the block transfer is complete, the channel is automatically
disabled. When enabled again, the channel will wait for the next block transfer trigger.
It is possible to select the trigger to start a burst transfer instead of a block transfer. This is called a single-shot transfer,
and for each trigger only one burst is transferred. In this configuration, when block repeat transfer mode is enabled (and
if no double buffering mode), the next block transfer does not require a transfer trigger. It will start as soon as the
previous block is done.
If a source generates a transfer trigger during an ongoing transfer, this will be kept pending, and the transfer can start
when the ongoing one is done. Only one pending transfer can be kept, and so if the trigger source generates more
transfer triggers when one is already pending, these will be lost.
In peripheral channel configuration, setting the trigger source automatically determines the peripheral register address
and the data transfer direction.
5.5 Addressing and Transfer Count
5.5.1 Addressing in Peripheral Channel Configuration
In peripheral channel configuration, the memory address for an EDMA transfer can either be static or automatically
incremented and the 16-bit peripheral address is automatically incremented if 2-byte burst is set. When memory address
increment is used, the default behavior is to update the memory address after each access. The original memory
address is stored by the EDMA controller, and can be individually configured to be reloaded at the following points:
End of each burst transfer
End of each block transfer
End of transaction
Never reloaded
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When 2-byte burst option is used to address 16-bit peripheral, the first byte access of the burst will be for the low byte of
the 16-bit register (ex: ACDA.CH0RESL) the second, for the high byte (ex: ACDA.CH0RESH). The 1-byte burst option is
reserved for 8-bit peripherals.
5.5.2 Addressing in Standard Channel Configuration
In standard channel configuration, the source and destination address for an EDMA transfer can either be static or
automatically incremented, with individual selections for source and destination. When address increment is used, the
default behavior is to update the address after each access. The original source and destination addresses are stored by
the EDMA controller, and so the source and destination addresses can be individually configured to be reloaded at the
following points:
End of each burst transfer
End of each block transfer
End of transaction
Never reloaded
5.5.3 Transfer Count Reload
When the channel transaction complete interrupt flag is set, the transfer counter is reloaded. The transfer counter is not
reloaded when the channel error interrupt flag is set.
5.6 Priority Between Channels
If several channels request a data transfer at the same time, a priority scheme is available to determine which channel is
allowed to transfer data. Application software can decide whether one or more channels should have a fixed priority or if
a round robin scheme should be used. A round robin scheme means that the channel that last transferred data will have
the lowest priority.
5.7 Double Buffering
Two channels can be interlinked so that two different EDMA transactions can be serialized, the second takes over the
transfer when the first is finished.
This can leave time for the application to process the data transferred by the first channel, prepare fresh data
buffers, and set up the channel registers again while the second channel is working
This can link two different processes as data match on serial peripheral and once matching (ex: address
recognition) a transfer of valid data is enabled
This is referred to as double buffering or chained transfers. The first channel is referred as the first software enabled
channel within the pair of linked channels.
DBUFMODE bits in CRTL register (CTRL.DBUFMODE) configure the double buffer modes. At channel level, the
REPEAT bit (CTRLA.REPEAT) of the second channel enables the link. The end of transfer (without error) on the first
channel enables the second channel (CTRLA.REPEAT).
Note that double buffering is incompatible with repeat block transfer.
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Figure 5-5. EDMA - Double Buffer Modes Versus Channel Modes
5.8 Data Processing
5.8.1 Data Match
This feature is available only for peripheral channels doing transfer from peripheral to memory locations.
To avoid unnecessary data transfers between peripherals and data memory, the EDMA controller has a built-in data
match feature. In this mode, the memory address register is set to store the data used during match operation. The
operation stops on data match or if the transfer count reaches zero. If the block transfer counter is programmed with
zero, then the data match is in free running mode and stopped when a match occurs. In case of no match an abort could
be necessary.
If a data match occurs, the corresponding peripheral channel is disabled and optionally a transaction complete interrupt
is generated. To know the true matched data in Mask-match or OR-match setting, the matched data is updated in the
corresponding EDMA register. Note that the un-matched data are lost.
If the block transfer counter is used and no data match is detected, then the channel is disabled, the transfer counter is
reloaded and optionally an error interrupt is generated.
Repeat block transfer mode is unavailable in data match operation.
DBUFMODE=01
(BUF01)
Per-Ch0
Per-Ch1
Per-Ch2
Per-Ch3
Std-Ch0
Per-Ch2
Per-Ch3
no double
buffer mode
Per-Ch0
Per-Ch1
Std-Ch2 Std-Ch2
Std-Ch0
no double
buffer mode
DBUFMODE=10
(BUF23)
Per-Ch0
Per-Ch1
Per-Ch2
Per-Ch3
Per-Ch2
Per-Ch3
Std-Ch0
Std-Ch2
Per-Ch0
Per-Ch1
Std-Ch2
Std-Ch0
no double
buffer mode
no double
buffer mode
DBUFMODE=11
(BUF0123)
Per-Ch2
Per-Ch3
Per-Ch0
Per-Ch1
Per-Ch2
Per-Ch3
Std-Ch0
Std-Ch2
Per-Ch0
Per-Ch1
Std-Ch2
Std-Ch0
CHMODE=00
(PER0123)
CHMODE=01
(STD0)
CHMODE=10
(STD2)
CHMODE=11
(STD02)
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Figure 5-6. EDMA – Data Match
5.8.2 Data Search
This feature is only available for standard channels.
To off-load the CPU, the EDMA controller has a built-in data search feature. In this mode, the destination address
register is set to store the bytes used for searching while the source address register is set to store the first address of
the memory buffer to scan. The data search operation stops on match or if the transfer count reaches zero. If the block
transfer counter is programmed with zero, then the data search is in free running mode and stopped when a match
occurs. In case on no match, an abort could be necessary.
If a data match occurs, the corresponding standard channel is disabled and optionally a transaction complete interrupt is
generated. To know the true matched data in Mask-match or OR-match setting, the matched data is updated in the
corresponding EDMA register. The source address register can be used to compute the data pointer.
If the block transfer counter is used and no data match is detected, then the channel is disabled, the transfer counter is
reloaded and optionally an error interrupt is generated.
Repeat block transfer mode is unavailable in data search operation.
In this mode, it is recommended to configure the increment mode and no reload mode for source address.
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Figure 5-7. EDMA – Data Search
5.9 Error Detection
The EDMA controller can detect erroneous operation. Error conditions are detected individually for each EDMA channel,
and the error conditions are:
Write to EEPROM locations
Reading EEPROM when the EEPROM is off (sleep entered)
EDMA controller or a busy channel is disabled in software during a transfer
5.10 Software Reset
Both the EDMA controller and an EDMA channel can be reset from the user software. When the EDMA controller is
reset, all registers associated with the EDMA controller, including channels, are cleared. A software reset can be done
only when the EDMA controller is disabled.
When an EDMA channel is reset, all registers associated with the EDMA channel are cleared. A software reset can be
done only when the EDMA channel is disabled.
Update : data <= mem_buf [4 ]
-
---
ptr
1
st
occurrence of ((mem_buf [n] &mask) == (data &mask)) = Match
mem_buf [ ]
[0][1][2][3][4][5][6][7][8]
Sear ch pr ogr ession (IN C mode )
Pointer position on match
Mask-Search (DP1)
(1-byte burst length)
Pointer position on match
-
---
ptr
1
st
occurrence of either (mem_buf [n] ==data 1) or ( m em _buf [n] ==data 2) = Match
mem_buf [ ]
[0][1][2][3][4][5][6][7][8]
Sear ch pr ogr ession (IN C mode )
OR-Search (DP2)
(1-byte burst length)
---
1
st
occurrence of ((mem_buf [n]
,
mem_buf [n+1 ]) == (data1
,
data 2)) = Match
mem_buf [ ]
[0][1][2][3][4][5][6][7][8]
Sear ch pr ogr ession (IN C mode )
“2-byte-Search (DP3)
(1-byte burst length)
Pointer position on m atch
ptr
----
1
st
occurrence of (mem_buf [2]) == (data1
,
data2)) = Match
mem_buf [ ]
[0] [1] [2] [3] [4]
Sear ch pr ogr ession (IN C mode )
(2-byte burst length)
Pointer positi on on m atch
Ptr
(
*
)
data1 = mem_buf [3 ]
data2 = mem_buf [4 ]
data1 = ( lsb ) mem_buf [2 ]
data2 = (msb) mem_buf [2 ]
Update : data1 <= mem_buf [4 ]
(
*
)
16 - bit data poi nter
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5.11 Protection
In order to enable a safe operation:
The channel mode bits (CTRL.CHMODE) are protected against user modification when the EDMA controller is
enabled (ENABLE=1)
Some channel bits and registers are protected against user modification during a transaction (CTRL.ENABLE=1):
REPEAT and SINGLE bits in CTRLA register
ADDCTRL (SRCADDCRTL) and DESTADDCTRL registers
ADDR (SRCADDR) and DESTADDR 16-bit registers
TRFCNTL (TRFCNT) and TRFCNTH registers.
Note that TRFREQ bit in CTRLA register and TRIGSRC register are not protected.
5.12 Interrupts
The EDMA controller can generate interrupts when an error is detected on an EDMA channel or when a transaction is
complete for an EDMA channel. Each EDMA channel has a separate interrupt vector, and there are different interrupt
flags for error and transaction complete.
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5.13 Register Description – EDMA Controller
5.13.1 CTRL – Control Register
Bit 7 – ENABLE: Enable
Setting this bit enables the EDMA controller. If the EDMA controller is enabled and this bit is written to zero, the
ENABLE bit is not cleared before the internal transfer buffer is empty, and the EDMA data transfer is aborted.
Bit 6 – RESET: Software Reset
Writing a one to RESET will be ignored as long as EDMA is enabled (ENABLE = 1). The software reset re-initial-
izes the controller and the channel registers. This bit can be set only when the EDMA controller is disabled
(ENABLE = 0).
Bit 5:4 – CHMODE[1:0]: Channel Mode
These bits set the channel in standard or peripheral mode, according to Table 5-1 on page 59 .
Table 5-1. Channel Configuration Settings
This field can be set only when the EDMA controller is disabled (ENABLE = 0).
Bit 3:2 – DBUFMODE[1:0]: Double Buffer Mode
These bits enable the double buffer on the different channels according to Table 5-2 on page 59.
Table 5-2. EDMA Double Buffer Settings
Bit 76543210
+0x00 ENABLE RESET CHMODE[1:0] DBUFMODE[1:0] PRIMODE[1:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
CMODE[1:0] Group configuration Description Channel number
00 PER0123 Four peripheral channels 0, 1, 2, 3
01 STD0
One standard channel 0
Two peripheral channels 2, 3
10 STD2
Two peripheral channels 0, 1
One standard channel 2
11 STD02 Two standard channels 0, 2
DBUFMODE[1:0] Group configuration Description
00 DISABLED No double buffer enabled
01 BUF01 Double buffer enabled on peripheral channels 0 and 1 (if exist)
10 BUF23 Double buffer enabled on peripheral channels 2 and 3 (if exist)
11 BUF0123
- If CHMOD = 00:
Double buffer enabled on peripheral channels 0
and 1 and also on peripheral channels 2 and 3
- If CHMOD ! = 00:
Double buffer enabled on channels 0 and 2
(irrespective of the channel configuration)
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In buffer modes, REPEAT bit of each channel controls the link (ex: to set-up a link from CHx to CHy, REPEAT bit of CHy
must be set).
There are no predefined channels order in the double buffer mode. The first channel that is enabled by software starts
first and, at the end of its transaction, it enables the second channel for a new transaction if the corresponding REPEAT
bit is set (hardware setting of CTRLA.ENABLE bit).
Bit 1:0 – PRIMODE[1:0]: Priority Mode
These bits determine the internal channel priority according to Table 5-3 on page 60.
Table 5-3. EDMA Channel Priority Settings
5.13.2 INTFLAGS – Interrupt Status Flags Register
Bit 7:4 – CHnERRIF: Channel n Error Interrupt Flag
If an error condition is detected on EDMA channel n, the CHnERRIF flag will be set. Writing a one to this bit loca-
tion will clear the flag.
These flags are duplicated in each CTRLB channel register.
Bit 3:0 – CHnTRNIF: Channel n Transaction Complete Interrupt
When a transaction on channel n has been completed, the CHnTRFIF flag will be set. Writing a one to this bit loca-
tion will clear the flag.
These flags are duplicated in each CTRLB channel register.
5.13.3 STATUS –Status Register
Bit 7:4 – CHnBUSY: Channel n Busy
When channel n starts an EDMA transaction, the CHnBUSY flag will be read as one. This flag is automatically
cleared when the EDMA channel is disabled, when the channel n transaction complete interrupt flag is set, or if the
EDMA channel n error interrupt flag is set.
Bit 3:0 – CHnPEND: Channel n Pending
If a block transfer is pending on EDMA peripheral channel n high, the CHnPEND flag will be read as one. This flag
is automatically cleared when the block transfer starts or if the transfer is aborted.
PRIMODE[1:0] Group Configuration Description
00 RR0123 Round robin
01 RR123 Channel0 > Round robin (channel 1, 2, and 3)
10 RR23 Channel0 > Channel1 > Round robin (channel 2 and 3)
11 CH0123 Channel0 > Channel1 > Channel2 > Channel3
Bit 76543210
+0x03 CH3ERRIF CH2ERRIF CH1ERRIF CH0ERRIF CH3TRNIF CH2TRNIF CH1TRNIF CH0TRNIF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 76543210
+0x04 CH3BUSY CH2BUSY CH1BUSY CH0BUSY CH3PEND CH2PEND CH1PEND CH0PEND
Read/Write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
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5.13.4 TEMP – Temporary Register
Bit 7:0 – TEMP[7:0]: Temporary Bits
This register is used when reading 16-bit registers in the EDMA controller. The high byte of the 16-bit register is
stored here when the low byte is read by the CPU. This register can also be read and written from the user soft-
ware. Reading and writing 16- bit registers requires special attention.
For details, refer to “Accessing 16-bit Registers” on page 13.
5.14 Register Description – Peripheral Channel
5.14.1 CTRLA – Control Register A
Bit 7 – ENABLE: Channel Enable
Setting this bit enables the peripheral channel. This bit is automatically cleared when the transaction is completed.
If the peripheral channel is enabled and this bit is written to zero, the channel is disabled between bursts and the
transfer is aborted.
Bit 6 – RESET: Software Reset
Setting this bit will reset the peripheral channel. It can only be set when the peripheral channel is disabled
(CTRLA.ENABLE = 0). Writing a one to this bit will be ignored as long as the peripheral channel is enabled
(CHEN=1). This bit is automatically cleared when reset is completed.
Bit 5 – REPEAT: Repeat Mode
Setting this bit enables the repeat mode. The repeat mode enables a “Repeat Block Transfer” if there is no double
buffering mode. Else this bit enables the link for the buffer mode and it is cleared by hardware at the end of the first
block transfer. A write to this bit will be ignored while the channel is enabled.
Bit 4 – TRFREQ: Transfer Request
Setting this bit requests a data transfer on the peripheral channel and acts as a software trigger. This bit is auto-
matically cleared at the beginning of the data transfer. Writing this bit does not have any effect unless the
peripheral channel is enabled.
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 2 – SINGLE: Single-Shot Data Transfer
Setting this bit enables the single-shot mode. The peripheral channel will then do a burst transfer of BURSTLEN
bytes on the transfer trigger. A write to this bit will be ignored while the channel is enabled.
Bit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 0 – BURSTLEN: Burst Length
This bit defines the peripheral channel burst length according to Table 5-4 on page 62.
This bit cannot be changed if the channel is busy.
Bit 76543210
+0x06 TEMP[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x00 ENABLE RESET REPEAT TRFREQ –SINGLE– BURSTLEN
Read/Write R/W R/W R/W R/W R R/W R R/W
Initial value 0 0 0 0 0 0 0 0
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Table 5-4. Peripheral Channel Burst Length
5.14.2 CTRLB – Control Register B
Bit 7 – CHBUSY - Busy
When the peripheral channel starts an EDMA transaction, the BUSY flag will be read as one. This flag is automat-
ically cleared when the EDMA channel is disabled, when the channel transaction complete interrupt flag is set or
when the channel error interrupt flag is set.
Bit 6 – CHPEND - Pending
If a block transfer is pending on the peripheral channel, the PEND flag will be read as one. This flag is automati-
cally cleared when the transfer starts or if the transfer is aborted.
Bit 5 – ERRIF - Error Interrupt Flag
If an error condition is detected on the peripheral channel, the ERRIF flag will be set and the optional interrupt is
generated.
Since the peripheral channel error interrupt shares the interrupt address with the peripheral channel n transaction
complete interrupt, ERRIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing
a one to this location.
Bit 4 – TRNIF - Transaction Complete Interrupt Flag
When a transaction on the peripheral channel has been completed, the TRNIF flag will be set and the optional
interrupt is generated. When repeat block transfer is not enabled, the transaction is completed and TRNIFR is set
after the block transfer. Else, TRNIF is also set after the last block transfer.
Since the peripheral channel transaction n complete interrupt shares the interrupt address with the peripheral
channel error interrupt, TRNIF will not be cleared when the interrupt vector is executed. This flag is cleared by writ-
ing a one to this location.
Bit 3:2 – ERRINTLVL[1:0]: Channel Error Interrupt Level
These bits enable the interrupt for EDMA channel transfer errors and select the interrupt level, as described in
“PMIC – Interrupts and Programmable Multilevel Interrupt Controller” on page 132. The enabled interrupt will trig-
ger for the conditions when ERRIF is set.
Bit 1:0 – TRNINTLVL[1:0]: Channel Transaction Complete Interrupt Level
These bits enable the interrupt for EDMA channel transaction completes and select the interrupt level, as
described in “PMIC – Interrupts and Programmable Multilevel Interrupt Controller” on page 132. The enabled inter-
rupt will trigger for the conditions when TRNIF is set.
BURSTLEN Group configuration Description
00 1BYTE 1 byte burst
01 2BYTE 2 bytes burst
Bit 76543210
+0x01 CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0]
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial value00000000
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5.14.3 ADDCTRL – Address Control Register
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5:4 – RELOAD[1:0]: Memory Address Reload
These bits decide the memory address reload according to Table 5-5 on page 63 .
A write to these bits is ignored while the channel is busy.
Table 5-5. Memory Address Reload Settings
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 2:0 – DIR[2:0]: Memory Address Mode
These bits decide the memory address mode, according to Table 5-6 on page 63 and Table 5-7 on page 63.
These bits cannot be changed if the channel is busy.
Table 5-6. Memory Address Mode Settings – Transfer Memory to Peripheral
Table 5-7. Memory Address Mode Settings – Transfer Peripheral to Memory
Bit 76543210
+0x02 -- RELOAD[1:0] -DIR[2:0]
Read/Write R R R/W R/W R R/W R/W R/W
Initial value00000000
RELOAD[1:0] Group configuration Description
00 NONE No reload performed.
01 BLOCK Memory address register is reloaded with initial value at end of each block transfer.
10 BURST Memory address register is reloaded with initial value at end of each burst transfer.
11 TRANSACTION Memory address register is reloaded with initial value at end of each transaction.
DIR[2:0] Group configuration Description
000 FIXED Fixed memory address
001 INC Increment
010 Reserved
011 Reserved
1xx Reserved
DIR[2:0] Group configuration Description
000 FIXED Fixed memory address
001 INC Increment
010 Reserved
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5.14.4 TRIGSRC – Trigger Source Register
Bit 7:0 – TRIGSRC[7:0]: Peripheral Channel Trigger Source Select
These bits select which trigger source is used for triggering a transfer on the EDMA channel. Some modules or
peripherals are not available as trigger source for EDMA peripheral channels. Other codes than those of Table 5-8
on page 64 will have no effect.
If the interrupt flag related to the trigger source is cleared or the interrupt level enabled so that an interrupt is trig-
gered, the EDMA request will be lost. Since an EDMA request can clear the interrupt flag, interrupts can be lost.
Note: For most trigger sources, the request is cleared by accessing a register belonging to the peripheral with the request. Refer to the different peripheral
chapters for description on how requests are generated and cleared.
Table 5-8. Trigger Codes for EDMA Peripheral Channels
Note: 1. It is recommended to set BURST2 configuration when reading or writing 16-bits registers.
011 Reserved
100 DP1
“Mask-Match” (1 byte)
- data: ADDRL register
- mask: ADDRH register (active bit-mask=1)
Note: Only available in 1-byte burst length mode
101 DP2
“OR-Match” (1 byte)
- data1: ADDRL register
OR
- data2: ADDRH register
Note: Only available in 1-byte burst length mode
110 DP3
“2-byte-Match” (two consecutive bytes)
- data1 (1st data or lsb) in DESTADDRL register
followed by
- data2 (2nd data or msb) in DESTADDRH register.
111 Reserved
DIR[2:0] Group configuration Description
Bit 7 6 5 4 3 2 1 0
+0x04 TRIGSRC[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
TRIGSRC[7:0] Group configuration Description
0x10 ADCA(1) ADCA EDMA triggers base value
0x15 DACA(1) DACA EDMA triggers base value
0x4A SPIC SPI C EDMA triggers base value
0x4C USARTC0 USART C0 EDMA triggers base value
0x6C USARTD0 USART D0 EDMA triggers base value
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Table 5-9. EDMA Trigger Source Offset Values for ADC Triggers
Table 5-10. EDMA Trigger Source Offset Values for DAC Triggers
Table 5-11. EDMA Trigger Source Offset Values for USART Triggers
Table 5-12. EDMA Trigger Source Offset Values for SPI Triggers
TRIGSRC offset value Group configuration Description
+0x00 CH0
ADC channel 0
- transfer direction: peripheral to memory
- EDMA reads CH0RES register
TRIGSRC offset value Group configuration Description
+0x00 CH0
DAC channel 0
- transfer direction: memory to peripheral
- EDMA writes CH0DATA register
+0x01 CH1
DAC channel 1
- transfer direction: memory to peripheral
- EDMA writes CH1DATA register
TRIGSRC offset value Group configuration Description
+0x00 RXC
Receive complete
- transfer direction: peripheral to memory
- EDMA reads DATA register
+0x01 DRE
Data register empty
- transfer direction: memory to peripheral
- EDMA writes DATA register
TRIGSRC offset value Group configuration Description
+0x00 IFRXC
Transfer complete in standard mode or receive complete in
double buffer mode
- transfer direction: peripheral to memory
- EDMA reads DATA register
+0x01 IFDRE
Transfer complete in standard mode or data register empty in
double buffer mode
- transfer direction: memory to peripheral
- EDMA writes DATA register
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5.14.5 TRFCNT – Block Transfer Count Register
TRFCNT defines the number of bytes in a block transfer. The value of TRFCNT is decremented after each byte read by
the EDMA channel.
When TRFCNT reaches zero, the register is reloaded with the last value written to it.
Bit 7:0 – TRFCNT[7 :0]: Block Transfer Count
The default value of this register is 0x01. If in transfer mode the user writes 0x00 to this register and fires an EDMA
trigger, EDMA will perform 256 transfers. If this register is set to 0x00 in data match mode, the operation will have
no count limit and will run up to a match occurs.
5.14.6 ADDRL – Memory Address Register Low
ADDRL and ADDRH represent the 16-bit value ADDR, which is the memory address in a transaction executed by a
peripheral channel. ADDRH is the most significant byte in the register. ADDR may be automatically incremented based
on settings in the DIR bits in “ADDCTRL – Address Control Register” on page 63.
In data match mode, ADDR is used for data to recognize, according to the Table 5-7 on page 63 .
Bit 7:0 – ADDR[7 :0]: Memory Address Low Byte
These bits hold the low-byte of the 16-bit memory address.
5.14.7 ADDRH – Memory Address Register High
Bit 7:0 – ADDR[15:8]: Memory Address High Byte
These bits hold the high-byte of the 16-bit memory address.
Bit 7 6 5 4 3 2 1 0
+0x06 TRFCNT[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 1
Bit 7 6 5 4 3 2 1 0
+0x08 ADDR[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x09 ADDR[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
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5.15 Register Description – Standard Channel
5.15.1 CTRLA – Control Register A
Bit 7 – ENABLE: Channel Enable
Setting this bit enables the standard channel. This bit is automatically cleared when the transaction is completed. If
the standard channel is enabled and this bit is written to zero, the channel is disabled between bursts, and the
transfer is aborted.
Bit 6 – RESET: Software Reset
Setting this bit will reset the standard channel. It can only be set when the standard channel is disabled
(CTRLA.ENABLE=0). Writing a one to this bit will be ignored as long as the standard channel is enabled
(CTRLA.ENABLE=1). This bit is automatically cleared when reset is completed.
Bit 5 – REPEAT: Repeat Mode
Setting this bit enables the repeat mode. The repeat mode enables a “Repeat Block Transfer” if there is no double
buffering mode. Else this bit enables the link for the buffer mode and it is cleared by hardware at the end of the first
block transfer. A write to this bit will be ignored while the channel is enabled.
Bit 4 – TRFREQ: Transfer Request
Setting this bit requests a data transfer on the standard channel and acts as a software trigger. This bit is automat-
ically cleared at the beginning of the data transfer. Writing this bit does not have any effect unless the standard
channel is enabled.
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 2 – SINGLE: Single-Shot Data transfer
Setting this bit enables the single-shot mode. The standard channel will then do a burst transfer of BURSTLEN
bytes on the transfer trigger. A write to this bit will be ignored while the channel is enabled.
Bit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 0 – BURSTLEN: Burst Length
This bit defines the standard channel burst length according to Table 5-13 on page 67 .
This bit cannot be changed if the channel is busy.
Table 5-13. Standard Channel Burst Length
Bit 7 6 5 4 3 2 1 0
+0x00 ENABLE RESET REPEAT TRFREQ -SINGLE- BURSTLEN
Read/Write R/W R/W R/W R/W R R/W R R/W
Initial value 0 0 0 0 0 0 0 0
BURSTLEN Group configuration Description
00 1BYTE 1 byte burst
01 2BYTE 2 bytes burst
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5.15.2 CTRLB – Control Register B
Bit 7 – CHBUSY - Channel Busy
When the standard channel starts an EDMA transaction, the CHBUSY flag will be read as one. This flag is auto-
matically cleared when the EDMA channel is disabled, when the channel transaction complete interrupt flag is set
or when the channel error interrupt flag is set.
Bit 6 – CHPEND - Channel Pending
If a block transfer is pending on the standard channel, the CHPEND flag will be read as one. This flag is automati-
cally cleared when the transfer starts or if the transfer is aborted.
Bit 5 – ERRIF - Error Interrupt Flag
If an error condition is detected on the standard channel, the ERRIF flag will be set and the optional interrupt is
generated.
Since the standard channel error interrupt shares the interrupt address with the peripheral channel n transaction
complete interrupt, ERRIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing
a one to this location.
Bit 4 – TRNIF - Transaction Complete Interrupt Flag
When a transaction on the standard channel has been completed, the TRNIF flag will be set and the optional inter-
rupt is generated. When repeat block transfer is not enabled, the transaction is completed and TRNIFR is set after
the block transfer. Else, TRNIF is also set after the last block transfer.
Since the standard channel transaction n complete interrupt shares the interrupt address with the peripheral chan-
nel error interrupt, TRNIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing a
one to this location.
Bit 3:2 – ERRINTLVL[1:0]: Channel Error Interrupt Level
These bits enable the interrupt for EDMA channel transfer errors and select the interrupt level, as described in
“PMIC – Interrupts and Programmable Multilevel Interrupt Controller” on page 132. The enabled interrupt will trig-
ger for the conditions when ERRIF is set.
Bit 1:0 – TRNINTLVL[1:0]: Channel Transaction Complete Interrupt Level
These bits enable the interrupt for EDMA channel transaction completes and select the interrupt level, as
described in “PMIC – Interrupts and Programmable Multilevel Interrupt Controller” on page 132. The enabled inter-
rupt will trigger for the conditions when TRNIF is set.
5.15.3 SRCADDCTRL – Source Address Control Register
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5:4 – SRCRELOAD[1:0]: Source Address Reload
These bits decide the source address reload according to Table 5-14 on page 69 . A write to these bits is ignored
while the channel is busy.
Bit 7 6 54 3 210
+0x01 CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0]
Read/Write R R R/W R/W R/W R/W R/W R/W R/W
Initial value0 0 0000000
Bit 76543210
+0x02 -- SRCRELOAD[1:0] - SRCDIR[2:0]
Read/Write R R R/W R/W R R/W R/W R/W
Initial value00000000
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Table 5-14. Source Address Reload Settings
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 2:0 – SRCDIR[2:0]: Source Address Mode
These bits decide the source address mode, according to Table 5-15 on page 69.
These bits cannot be changed if the channel is busy.
Table 5-15. Source Address Mode Settings
5.15.4 DESTADDCTRL – Destination Address Control Register
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5:4 – DESTRELOAD[1:0]: Destination Address Reload
These bits decide the destination address reload according to Table 5-16 on page 70.
A write to these bits is ignored while the channel is busy.
SRCRELOAD[1:0] Group configuration Description
00 NONE No reload performed.
01 BLOCK Source address register is reloaded with initial value at end of each block
transfer.
10 BURST Source address register is reloaded with initial value at end of each burst
transfer.
11 TRANSACTION Source address register is reloaded with initial value at end of each
transaction.
SRCDIRD[2:0] Group configuration Description
000 FIXED Fixed address
001 INC Increment
010 -Reserved
011 -Reserved
1xx -Reserved
Bit 76543210
+0x03 -- DESTRELOAD[1:0] - DESTDIR[2:0
Read/Write R R R/W R/W R R/W R/W R/W
Initial value00000000
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Table 5-16. EDMA Channel Source Address Reload Settings
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 2:0 – DESTDIR[2:0]: Destination Address Mode
These bits decide the destination address mode, according to Table 5-17 on page 70.
These bits cannot be changed if the channel is busy.
Table 5-17. Destination Address Mode Settings
DESTRELOAD[1:0] Group configuration Description
00 NONE No reload performed.
01 BLOCK Destination address register is reloaded with initial value at end of each
block transfer.
10 BURST Destination address register is reloaded with initial value at end of each
burst transfer.
11 TRANSACTION Destination address register is reloaded with initial value at end of each
transaction.
DESTDIR[1:0] Group configuration Description
000 FIXED Fixed address
001 INC Increment
010 -Reserved
011 -Reserved
100 DP1
“Mask-Search” (1 byte)
- data: DESTADDRL register
- mask: DESTADDRH register (active bit-mask=1)
Note: Only available in 1-byte burst length mode
101 DP2
“OR-Search” (1 byte)
- data1: DESTADDRL register
OR
- data2: DESTADDRH register
Note: Only available in 1-byte burst length mode
110 DP3
“2-byte-Search” (two consecutive bytes)
- data1 (1st data or lsb) in DESTADDRL register
followed by
- data2 (2nd data or msb) in DESTADDRH register.
111 -Reserved
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5.15.5 TRIGSRC – Trigger Source Register
Bit 7:0 – TRIGSRC[7:0]: Trigger Source Select
These bits select which trigger source is used for triggering a transfer on the EDMA standard channel. A zero
value means that the trigger source is disabled. Table 5-18 on page 71 shows the peripherals and triggers which
are supported by an EDMA standard channel. For modules or peripherals which do not exist for a device, the
transfer trigger does not exist. Refer to the device datasheet for the list of peripherals available.
If the interrupt flag related to the trigger source is cleared or the interrupt level enabled so that an interrupt is trig-
gered, the EDMA request will be lost. Since an EDMA request can clear the interrupt flag, interrupts can be lost.
Table 5-18. EDMA Trigger Source Base Values for all Modules and Peripherals
Table 5-19. EDMA Trigger Source Offset Values for ADC Triggers
Table 5-20. EDMA Trigger Source Offset Values for DAC Triggers
Bit 7 6 5 4 3 2 1 0
+0x04 TRIGSRC[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
TRIGSRC base value Group configuration Description
0x00 OFF Software triggers only (see TRFREQ bit in “CTRLA – Control
Register A” on page 61)
0x01 SYS Event system EDMA triggers base value
0x10 ADCA ADCA EDMA triggers base value
0x15 DACA DACA EDMA triggers base value
0x40 TCC4 Timer/counter C4 EDMA triggers base value
0x46 TCC5 Timer/counter C5 EDMA triggers base value
0x4A SPIC SPI C EDMA triggers base value
0x4C USARTC0 USART C0 EDMA triggers base value
0x66 TCD5 Timer/counter D5 EDMA triggers base value
0x6C USARTD0 USART D0 EDMA triggers base value
TRIGSRC offset value Group configuration Description
+0x00 CH0 ADC channel 0
TRIGSRC offset value Group configuration Description
+0x00 CH0 DAC channel 0
+0x01 CH1 DAC channel 1
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Table 5-21. EDMA Trigger Source Offset Values for Event System Triggers
Table 5-22. EDMA Trigger Source Offset Values for Event System Triggers
Note: 1. CC channel C and D triggers are available only for timer/counters 4.
Table 5-23. EDMA Trigger Source Offset Values for USART Triggers
Table 5-24. EDMA Trigger Source Offset Values for SPI Triggers
The group configuration is the “base_offset;” for example, TCC5_CCA for the timer/counter C5 CC channel A the transfer
trigger.
TRIGSRC offset value Group configuration Description
+0x00 CH0 Event channel 0
+0x01 CH1 Event channel 1
+0x02 CH2 Event channel 2
TRIGSRC offset value Group configuration Description
+0x00 OVF Overflow/underflow
+0x01 ERR Error
+0x02 CCA Compare or capture channel A
+0x03 CCB Compare or capture channel B
+0x04 CCC(1) Compare or capture channel C
+0x05 CCD(1) Compare or capture channel D
TRIGSRC offset value Group configuration Description
+0x00 RXC Receive complete
+0x01 DRE Data register empty
TRIGSRC offset value Group configuration Description
+0x00 IFRXC - Transfer complete in standard mode
- Receive complete in double buffer mode
+0x01 IFDRE - Transfer complete in standard mode
- Data register empty in double buffer mode
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5.15.6 TRFCNTL – Block Transfer Count Register Low
The TRFCNTH and TRFCNTL register pair represents the 16-bit value TRFCNT. TRFCNT defines the number of bytes
in a block transfer. The value of TRFCNT is decremented after each byte read by the EDMA standard channel.
The default value of this 16-bit register is 0x0101 (not 0x0001). If the user writes 0x0000 to this 16-bit register and fires
an EDMA trigger, EDMA will perform 65536 transfers or searches.
When TRFCNT reaches zero, the register is reloaded with the last value written to it.
Bit 7:0 – TRFCNT[7:0]: Block Transfer Count Low Byte
These bits hold the low-byte of the 16-bit block transfer count.
5.15.7 TRFCNTH – Block Transfer Count Register High
Bit 7:0 – TRFCNT[15:8]: Block Transfer Count High Byte
These bits hold the high-byte of the 16-bit block transfer count.
5.15.8 SRCADDRL – Source Address Register Low
SRCADDRL and SRCADDRH represent the16-bit value SRCADDR, which is the source address in a transaction
executed by a standard channel. SRCADDRH is the most significant byte in the register. SRCADDR may be
automatically incremented based on settings in the SRCDIR bits in “SRCADDCTRL – Source Address Control Register” .
Bit 7:0 – SRCADDR[7 :0]: Source Address Low Byte
These bits hold the low-byte of the 16-bit source address.
5.15.9 SRCADDRH – Source Address Register High
Bit 7:0 – SRCADDR[15:8]: Source Address High Byte
These bits hold the high-byte of the 16-bit source address.
Bit 7 6 5 4 3 2 1 0
+0x06 TRFCNT[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 1
Bit 7 6 5 4 3 2 1 0
+0x07 TRFCNT [15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 1
Bit 7 6 5 4 3 2 1 0
+0x08 SRCADDR[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7654321 0
+0x09 SRCADDR[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
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5.15.10 DESTADDRL – Destination Address Register Low
DESTADDRL and DESTADDRH represent the16-bit value DESTADDR, which is the destination address in a transaction
executed by a standard channel. DESTADDRH is the most significant byte in the register. DESTADDR may be
automatically incremented based on settings in the DESTDIR bits in “DESTADDCTRL – Destination Address Control
Register” .
In data search mode, DESTADDR is used for data to recognize according to Table 5-17 on page 70 .
Bit 7:0 – DESTADDR[7 :0]: Destination Address Low Byte
These bits hold the low-byte of the 16-bit destination address.
5.15.11 DESTADDRH – Destination Address Register High
Bit 7:0 – DESTADDR[15:8]: Destination Address High Byte
These bits hold the high-byte of the 16-bit destination address.
Bit 7 6 5 4 3 2 1 0
+0x08 DESTADDR[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x09 DESTADDR[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
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5.16 Register Summary – EDMA Controller in PER0123 Configuration
5.17 Register Summary – EDMA Controller in STD0 Configuration
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL ENABLE RESET CHMODE[1:0] DBUFMODE[1:0] PRIMODE[1:0] 59
+0x01 Reserved – – –
+0x02 Reserved – – –
+0x03 INTFLAGS CH3ERRI
F
CH2ERRI
FCH1ERRIF CH0ERRIF CH3TRNFIF CH2TRNFI
FCH1TRNFIF CH0TRNFIF 60
+0x04 STATUS CH3BUSY CH2BUSY CH1BUSY CH0BUSY CH3PEND CH2PEND CH1PEND CH0PEND 60
+0x05 Reserved – – –
+0x06 TEMP TEMP[7:0] 61
+0x07 Reserved – – –
+0x10/0x1F CH0 Register addresses for EDMA peripheral channel 0
+0x20/0x2F CH1 Register addresses for EDMA peripheral channel 1
+0x30/0x3F CH2 Register addresses for EDMA peripheral channel 2
+0x40/0x4F CH3 Register addresses for EDMA peripheral channel 3
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL ENABLE RESET CHMODE[1:0] DBUFMODE[1:0] PRIMODE[1:0] 59
+0x01 Reserved – – –
+0x02 Reserved – – –
+0x03 INTFLAGS CH3ERRI
F
CH2ERRI
F CH0ERRIF CH3TRNFIF CH2TRNFI
F CH0TRNFIF 60
+0x04 STATUS CH3BUSY CH2BUSY CH0BUSY CH3PEND CH2PEND CH0PEND 60
+0x05 Reserved – – –
+0x06 TEMP TEMP[7:0] 61
+0x07 Reserved – – –
+0x10/0x1F CH0 Register addresses for EDMA standard channel 0
+0x20/0x2F Reserved – – –
+0x30/0x3F CH2 Register addresses for EDMA peripheral channel 2
+0x40/0x4F CH3 Register addresses for EDMA peripheral channel 3
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5.18 Register Summary – EDMA Controller in STD2 Configuration
5.19 Register Summary – EDMA Controller in STD02 Configuration
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 bit 0 Page
+0x00 CTRL ENABLE RESET CHMODE[1:0] DBUFMODE[1:0] PRIMODE[1:0] 59
+0x01 Reserved – –
+0x02 Reserved – –
+0x03 INTFLAGS CH2ERRIF CH1ERRI
FCH0ERRIF CH2TRNFIF CH1TRNFIF CH0TRNFIF 60
+0x04 STATUS CH2BUSY CH1BUSY CH0BUSY CH2PEND CH1PEND CH0PEND 60
+0x05 Reserved – –
+0x06 TEMP TEMP[7:0] 61
+0x07 Reserved – –
+0x10/0x1F CH0 Register addresses for EDMA peripheral channel 0
+0x20/0x2F CH1 Register addresses for EDMA peripheral channel 1
+0x30/0x3F CH2 Register addresses for EDMA standard channel 2
+0x40/0x4F Reserved – –
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL ENABLE RESET CHMODE[1:0] DBUFMODE[1:0] PRIMODE[1:0] 59
+0x01 Reserved – –
+0x02 Reserved – –
+0x03 INTFLAGS CH2ERRIF – CH0ERRIF – CH2TRNFIF CH0TRNFIF 60
+0x04 STATUS CH2BUSY – CH0BUSY – CH2PEND CH0PEND 60
+0x05 Reserved – –
+0x06 TEMP TEMP[7:0] 61
+0x07 Reserved – –
+0x10/0x1F CH0 Register addresses for EDMA peripheral channel 0
+0x20/0x2F Reserved – –
+0x30/0x3F CH2 Register addresses for EDMA standard channel 2
+0x40/0x4F Reserved – –
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5.20 Register Summary – EDMA Peripheral Channel
5.21 Register Summary – EDMA Standard Channel
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRLA ENABLE RESET REPEAT TRFREQ SINGLE BURSTLEN 61
+0x01 CTRLB CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0] 62
+0x02 ADDCTRL – RELOAD[1:0] DIR[2:0] 63
+0x03 Reserved – – –
+0x04 TRIGSRC TRIGSRC[7:0] 64
+0x05 Reserved – – –
+0x06 TRFCNTL TRFCNT[7:0] 66
+0x07 Reserved – – –
+0x08 ADDRL ADDR[7:0] 66
+0x09 ADDRH ADDR[15:8] 66
+0x0A Reserved – – –
+0x0B Reserved – – –
+0x0C Reserved – – –
+0x0D Reserved – – –
+0x0E Reserved – – –
+0x0F Reserved – – –
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRLA ENABLE RESET REPEAT TRFREQ –SINGLE BURSTLEN 67
+0x01 CTRLB CHBUSY CHPEND ERRIF TRNIF ERRINTLVL[1:0] TRNINTLVL[1:0] 68
+0x02 SRCADDCTRL – SRCRELOAD[1:0] SRCDIR[2:0] 68
+0x03 DESTADDCTRL – DESTRELOAD[1:0] DESTDIR[2:0] 69
+0x04 TRIGSRC TRIGSRC[7:0] 71
+0x05 Reserved – –
+0x06 TRFCNTL TRFCNT[7:0] 73
+0x07 TRFCNTH TRFCNT[15:8] 73
+0x08 SRCADDRL SRCADDR[7:0] 73
+0x09 SRCADDRH SRCADDR[15:8] 73
+0x0A Reserved – –
+0x0B Reserved – –
+0x0C DESTADDRL DESTADDR[7:0] 74
+0x0D DESTADDRH DESTADDR[15:8] 74
+0x0E Reserved – –
+0x0F Reserved – –
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5.22 Interrupt Vector Summary
Table 5-25. EDMA Interrupt Vectors and their Word Offset Addresses from the EDMA Controller Interrupt Base
Offset Source Interrupt description
0x00 CH0_vect EDMA controller channel 0 interrupt vector
0x02 CH1_vect EDMA controller channel 1 interrupt vector
0x04 CH2_vect EDMA controller channel 2 interrupt vector
0x06 CH3_vect EDMA controller channel 3 interrupt vector
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6. Event System
6.1 Features
System for direct peripheral-to-peripheral communication and signalling
Peripherals can directly send, receive, and react to peripheral events
CPU and EDMA controller independent operation
100% predictable signal timing
Short and guaranteed response time
Eight event channels for up to eight different and parallel signal routings and configurations
Events can be sent and/or used by most peripherals, clock system, and software
Additional functions include
Quadrature decoders with rotary filtering
Digital filtering of I/O pin state with flexible prescaler clock options
Simultaneous synchronous and asynchronous events provided to peripheral
Works in all sleep modes
6.2 Overview
The event system enables direct peripheral-to-peripheral communication and signalling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for
short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction
without the use of interrupts, CPU, or EDMA controller resources, and is thus a powerful tool for reducing the complexity,
size and execution time of application code. It allows for synchronized timing of actions in several peripheral modules.
The event system enables also asynchronous event routing for instant actions in peripherals.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing
network. How events are routed and used by the peripherals is configured in software.
Figure 6-1 on page 80 shows a basic diagram of all connected peripherals. The event system can directly connect
together analog to digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR
communication module (IRCOM) and XMEGA Custom Logic (XCL). It can also be used to trigger EDMA transactions
(EDMA controller). Events can also be generated from software and peripheral clock.
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Figure 6-1. Event System Overview and Connected Peripherals
The event routing network consists of eight software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow up to eight parallel event configurations and routings. The maximum
routing latency of an external synchronous event is two peripheral clock cycles due to re-synchronization, but several
peripherals can directly use the asynchronous event without any clock delay. The event system works in all sleep modes,
but only asynchronous events can be routed in sleep modes where the system clock is not available.
6.3 Events
In the context of the event system, an indication that a change of state within a peripheral has occurred is called an
event. There are three main types of events: signalling events, synchronous data events, and asynchronous data events.
Signalling events only indicate a change of state while data events contain additional information about the event.
The peripheral from which the event originates is called the event generator. Within each peripheral (for example, a
timer/counter), there can be several event sources, such as a timer compare match or timer overflow. The peripheral
using the event is called the event user, and the action that is triggered is called the event action.
Figure 6-2. Example of Event Source, Generator, User, and Action
Events can also be generated manually in software.
Timer /
Counters
ADC
Real Time
Counter
CPU /
Software
EDMA
Controller
IRCOM
Event Routing Network
Event
System
Controller
clkPER
Prescaler
AC
Port Pins
DAC
XMEGA
Custom Logic
Event User
Event
Routing
Network
|
Compare Match
Over-/Underflow
Error
Timer/Counter
Syncsweep
Single
Conversion
ADC
Event Generator
Event Source Event Action
Event Action Selection
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6.4 Signalling Events
Signalling events are the most basic type of event. A signalling event does not contain any information apart from the
indication of a change in a peripheral. Most peripherals can only generate and use signalling events. Unless otherwise
stated, all occurrences of the word ”event” are to be understood as meaning signalling events, which is a strobe.
6.5 Data Events
Data events differ from signalling events in that they contain information that event users can decode to decide event
actions based on the receiver information. Data events can be synchronous or asynchronous.
Although the event routing network can route all events to all event users, those that are only meant to use signalling
events do not have decoding capabilities needed to utilize data events.
How event users decode data events is shown in Table 6-1 on page 81.
Event users that can utilize data events can also use signalling events. This is configurable, and is described in the
datasheet module for each peripheral.
6.6 Peripheral Clock Events
Each event channel includes a peripheral clock prescaler with a range from 1 (no prescaling) to 32768. This enables
configurable periodic event generation based on the peripheral clock. It is possible to periodically trigger events in a
peripheral or to periodically trigger synchronized events in several peripherals. Since each event channel include a
prescaler, different peripherals can receive triggers with different intervals.
6.7 Software Events
Events can be generated from software by writing the DATA and STROBE registers. The DATA register must be written
first, since writing the STROBE register triggers the operation. The DATA and STROBE registers contain one bit for each
event channel. Bit n corresponds to event channel n. It is possible to generate events on several channels at the same
time by writing to several bit locations at once.
Software-generated events last for one clock cycle and will overwrite events from other event generators on that event
channel during that clock cycle.
Table 6-1 on page 81 shows the different events, how they can be manually generated, and how they are decoded.
Table 6-1. Manually Generated Events and Decoding of Events
6.8 Event Routing Network
The event routing network routes the events between peripherals. It consists of eight multiplexers (CHnMUX), which can
each be configured to route any event source to any event users. The output from a multiplexer is referred to as an event
channel. For each peripheral, it is selectable if and how incoming events should trigger event actions. Details on
configurations can be found in the datasheet for each peripheral. The event routing network is shown in Figure 6-3 on
page 82.
STROBE DATA Data event user Signalling event user
0 0No Event No Event
0 1 Data Event 01 No Event
1 0 Data Event 02 Signalling Event
1 1Data Event 03 Signalling Event
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Figure 6-3. Event Routing Network
Eight multiplexers means that it is possible to route up to eight events at the same time. It is also possible to route one
event through several multiplexers.
Not all XMEGA devices contain all peripherals. This only means that a peripheral is not available for generating or using
events. The network configuration itself is compatible between all devices.
Event selection for each channel and event type is shown in Table 6-2 on page 83:
PORTA
PORTC
PORTD
ADCA
(PORTD)
TCD5 (4)
(PORTC)
TCC4
TCC5
(6)
(4)
(8)
(8)
(30)
(1)
(3)
(8)
(8)
(8)
(8)
AC0
AC1
RTC
(8)
CH0MUX[7:0]
CH1MUX[7:0]
CH2MUX[7:0]
CH3MUX[7:0]
CH4MUX[7:0]
CH5MUX[7:0]
CH6MUX[7:0]
CH7MUX[7:0]
CH1CTRL[7:0]
CH0CTRL[7:0]
CH2CTRL[7:0]
CH3CTRL[7:0]
CH4CTRL[7:0]
CH5CTRL[7:0]
CH6CTRL[7:0]
CH7CTRL[7:0]
Event Channel 7
Event Channel 6
Event Channel 5
Event Channel 4
Event Channel 3
Event Channel 2
Event Channel 1
Event Channel 0
XCL
(ACA)
(8)
(2)
(8)
ClkPER
(8)
(8)
(24)
(16)
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Table 6-2. Event Selection and Event Type
Event type
Peripheral Event source Strobe event Synchronous data Asynchronous data
RTC
RTC_OVF x x
RTC_CMP x x
AC
AC_CH0 x x
AC_CH1 x x
AC_WIN x
ADC ADC_CH x
PRESCALER PRESC_M x
PORTn
PORTn_PIN0 x x x
PORTn_PIN1 x x x
PORTn_PIN2 x x x
PORTn_PIN3 x x x
PORTn_PIN4 x x x
PORTn_PIN5 x x x
PORTn_PIN6 x x x
PORTn_PIN7 x x x
TC4
TC4_OVF x
TC4_ERR x
TC4_CCA x
TC4_CCB x
TC4_CCC x
TC4_CCD x
TC5
TC5_OVF x
TC5_ERR x
TC5_CCA x
TC5_CCB x
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6.9 Event Timing
An event normally lasts for one peripheral clock cycle, but some event sources, such as a low level on an I/O pin, will
generate events continuously. Details on this are described in the datasheet for each peripheral, but unless otherwise
stated, an event lasts for one peripheral clock cycle.
It takes a maximum of two peripheral clock cycles from when an event is generated until the event actions in other
peripherals are triggered. This ensures short and 100% predictable response times, independent of CPU or EDMA
controller load or software revisions.
An asynchronous event is routed without any peripheral clock delay and it is present as long as the source is generating
this event.
6.10 Filtering
Each event channel includes a digital filter. When this is enabled, an event must be sampled with the same value for a
configurable number of system clock or prescaler clock cycles before it is accepted. This is primarily intended for pin
change events. The default clock for a digital filter is the system clock. Optionally, the clock can be divided by using the
prescaler with individual settings for each channel 0 to channel 3 or channel 4 to channel 7.
Event channels with quadrature decoder extension support rotary filter. Figure 6-4 on page 85 shows the output signals
of the rotary filter. The rotary filter output controls the QDEC up, down and index operation. The digital filter can be
enabled when using the rotary encoder.
XCL
XCL_UNF0 x
XCL_UNF1 x
XCL_CC0 x
XCL_CC1 x
XCL_PEC0 x
XCL_PEC1 x
XCL_LUT0 x x x
XCL_LUT1 x x x
Event type
Peripheral Event source Strobe event Synchronous data Asynchronous data
L L / lffl lfiL LL } H_K_U “—
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Figure 6-4. Rotary Encoder Output Signals
6.11 Quadrature Decoder
The event system includes three quadrature decoders (QDECs), which enable the device to decode quadrature input on
I/O pins and send data events that a timer/counter can decode to count up, count down, or index/reset. Table 6-3 on
page 86 summarizes which quadrature decoder data events are available, how they are decoded by timers, and how
they can be generated. The QDECs and related features and control and status registers are available for event
channels 0, 2, and 4.
DETECTA = Set PHASE0 unglitch when PHASE0 = 1 and PHASE90 = 0
DETECTB = Set PHASE90 unglitch when PHASE0 = 1 and PHASE90 = 1
DETECTC = Clear PHASE0 unglitch when PHASE0 = 0 and PHASE90 = 1
DETECTD = Clear PHASE90 unglitch when PHASE =0 and PHASE90 = 0
FORWARD
PHASE EVENT
BACKWARD
On phase event, update DIRECTION : 0=FORWARD/1=BACKWARD
PH0 rise : PH90
PH0 fall : not(PH90)
PH90 rise : not(PH0)
PH90 fall : PH0
PHASE0
PHASE90 DETECTA
DETECTB DETECTD
DIRECTION
PHASE90
unglitch
DETECTC
PHASE0
unglitch
Q0 Q2 Q3 Q1 Q0 Q2 Q3
PHASE Q1
PHASE0
PHASE90
DETECTA
DETECTB DETECTD
DIRECTION
PHASE90
unglitch
DETECTC
PHASE0
unglitch
Q0 Q1 Q3 Q2 Q0 Q1 Q3
PHASE Q2
1 cycle I 4 states F‘y//"::\\\ J \\ ‘777/yr‘ J/fx J K J \g/ AtmeL
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Table 6-3. Quadrature Decoder Data Events
6.11.1 Quadrature Operation
A quadrature signal is characterized by having two square waves that are phase shifted 90 degrees relative to each
other. Rotational movement can be measured by counting the edges of the two waveforms. The phase relationship
between the two square waves determines the direction of rotation.
Figure 6-5. Quadrature Signals from a Rotary Encoder
Figure 6-5 on page 86 shows typical quadrature signals from a rotary encoder. The signals QDPH0 and QDPH90 are the
two quadrature signals. When QDPH90 leads QDPH0, the rotation is defined as positive or forward. When QDPH0 leads
QDPH90, the rotation is defined as negative or reverse. The concatenation of the two phase signals is called the
quadrature state or the phase state.
In order to know the absolute rotary displacement, a third index signal (QDINDX) can be used. This gives an indication
once per revolution.
6.11.2 QDEC Setup
For a full QDEC setup, the following is required:
Two or three I/O port pins for quadrature signal input
Two event system channels for quadrature decoding
One timer/counter for up, down, and optional index count
The following procedure should be used for QDEC setup:
1. Choose two successive pins on a port as QDEC phase inputs.
2. Set the pin direction for QDPH0 and QDPH90 as input.
STROBE DATA Data event user Signalling event user
0 0No Event No Event
0 1 Index/reset No Event
1 0 Count down Signalling Event
1 1Count up Signalling Event
00 10 11 01
QDPH0
QDPH90
QDINDX
Forward Direction
Backward
Direction
01 11 10 00
1 cycle / 4 states
QDPH0
QDPH90
QDINDX
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3. Set the pin configuration for QDPH0 and QDPH90 to low level sense.
4. Select the QDPH0 pin as a multiplexer input for an event channel, n.
5. Enable quadrature decoding and digital filtering in the event channel.
6. Optional:
1. Set the digital filter control register (DFCTRL) options.
2. Set up a QDEC index (QINDX).
3. Select a third pin for QINDX input.
4. Set the pin direction for QINDX as input.
5. Set the pin configuration for QINDX to sense both edges.
6. Select QINDX as a multiplexer input for event channel n+1.
7. Set the quadrature index enable bit in event channel n+1.
8. Select the index recognition mode for event channel n+1.
9. Set quadrature decoding as the event action for a timer/counter.
10. Select event channel n as the event source for the timer/counter.
Set the period register of the timer/counter to ('line count' * 4 - 1), the line count of the quadrature encoder
Enable the timer/counter without clock prescaling
The angle of a quadrature encoder attached to QDPH0, QDPH90 (and QINDX) can now be read directly from the
timer/counter count register. If the count register is different from BOTTOM when the index is recognized, the
timer/counter error flag is set. Similarly, the error flag is set if the position counter passes BOTTOM without the
recognition of the index.
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6.12 Register Description
6.12.1 CHnMUX – Event Channel n Multiplexer Register
Bit 7:0 – CHnMUX[7:0]: Channel Multiplexer
These bits select the event source according to Table 6-4 on page 88. This table is valid for all XMEGA devices
regardless of whether the peripheral is present or not. Selecting event sources from peripherals that are not pres-
ent will give the same result as when this register is zero. When this register is zero, no events are routed through.
Manually generated events will override CHnMUX and be routed to the event channel even if this register is zero.
Table 6-4. CHnMUX Bit Settings
Bit 76543210
+n CHnMUX[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
CHnMUX[7:4] CHnMUX[3:0] Group configuration Event source
0000 0 0 0 0 None (manually generated events only)
0000 0 0 0 1 (Reserved)
0000 0 0 1 x (Reserved)
0000 0 1 x x (Reserved)
0000 1 0 0 0 RTC_OVF RTC overflow
0000 1 0 0 1 RTC_CMP RTC compare match
0000 1 0 1 x (Reserved)
0000 1 1 x x (Reserved)
0001 0 0 0 0 ACA_CH0 ACA channel 0
0001 0 0 0 1 ACA_CH1 ACA channel 1
0001 0 0 1 0 ACA_WIN ACA window
0001 0 x x x (Reserved)
0010 0 0 0 0 ADCA_CH ADCA channel
0010 x x x x (Reserved)
0011 x x x X (Reserved)
0100 x x x x (Reserved)
0101 0 n PORTA_PINn(1) PORTA pin n (n = 0,1,2 … or 7)
0101 1 x x x (Reserved)
0110 0 n PORTC_PINn(1) PORTC pin n (n = 0,1,2 … or 7)
0110 1 n PORTD_PINn(1) PORTD pin n (n = 0,1,2 … or 7)
0111 x x x x (Reserved)
1000 MPRESCALER_M ClkPER divide by 2M (M = 0 to 15)
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Note: 1. The description of how the ports generate events is described in “Port Event” on page 146.
Table 6-5. XCL Events
Table 6-6. Timer/counter Events
1001 x x x x (Reserved)
1010 x x x x (Reserved)
1011 0 E See Table 6-5 XCL event type E
1011 1 x x x (Reserved)
1100 0 E See Table 6-6 Timer/counter C4 event type E
1100 1 E See Table 6-6 Timer/counter C5 event type E
1101 0 x X x (Reserved)
1101 1 E See Table 6-6 Timer/counter D5 event type E
1110 x x x x (Reserved)
1111 x x x x (Reserved)
T/C event E Group configuration Event type
0 0 0 XCL_UNF0 BTC0 underflow
0 0 1 XCL_UNF1 BTC1 underflow
0 1 0 XCL_CC0 BTC0 capture or compare
0 1 1 XCL_CC1 BTC1 capture or compare
1 0 0 XCL_PEC0 PEC0 restart
1 0 1 XCL_PEC1 PEC1 restart
1 1 0 XCL_LUT0 LUT0 output
1 1 1 XCL_LUT1 LUT1 output
T/C event E Group configuration Event type
0 0 0 TCxn_OVF Over/Underflow (x = C,D)(n = 4 or 5)
0 0 1 TCxn_ERR Error (x = C,D)(n = 4 or 5)
0 1 x (Reserved)
1 0 0 TCxn_CCA Capture or compare A (x = C,D)(n = 4 or 5)
1 0 1 TCxn_CCB Capture or compare B (x = C,D)(n = 4 or 5)
1 1 0 TCxn_CCC Capture or compare C (x = C)(n = 4)
1 1 1 TCxn_CCD Capture or compare D (x = C)(n = 4)
CHnMUX[7:4] CHnMUX[3:0] Group configuration Event source
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6.12.2 CHnCTRL – Event Channel n Control Register
Bit 7 – ROTARY: Rotary
Setting this bit enables rotary filter. This bit is available only for CH0CTRL.
Bit 6:5 – QDIRM[1:0]: Quadrature Decode Index Recognition Mode
These bits determine the quadrature state for the QDPH0 and QDPH90 signals, where a valid index signal is rec-
ognized and the counter index data event is given according to Table 6-7 on page 90. These bits should only be
set when a quadrature encoder with a connected index signal is used. These bits are available only for CH0CTRL.
Table 6-7. QDIRM Bit Settings
Bit 4 – QDIEN: Quadrature Decode Index Enable
When this bit is set, the event channel will be used as a QDEC index source, and the index data event will be
enabled.
This bit is available only for CH0CTRL.
Bit 3 – QDEN: Quadrature Decode Enable
Setting this bit enables QDEC operation. This bit is ignored if the rotary encoder is enabled.
This bit is available only for CH0CTRL.
Bit 2:0 – DIGFILT[2:0]: Digital Filter Coefficient
These bits define the length of digital filtering used. Events will be passed through to the event channel only when
the event source has been active and sampled with the same level for the number of prescaler peripheral clock
cycles defined by DIGFILT.
Table 6-8. Digital Filter Coefficient Values
Bit 7 6543210
+8x08 +n ROTARY QDIRM[1:0] QDIEN QDEN DIGFILT[2:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value0 0000000
QDIRM[1:0] Index recognition state
0 0 {QDPH0, QDPH90} = 0b00
0 1 {QDPH0, QDPH90} = 0b01
1 0 {QDPH0, QDPH90} = 0b10
1 1 {QDPH0, QDPH90} = 0b11
DIGFILT[2:0] Group configuration Description
000 1SAMPLE One sample
001 2SAMPLES Two samples
010 3SAMPLES Three samples
011 4SAMPLES Four samples
100 5SAMPLES Five samples
101 6SAMPLES Six samples
110 7SAMPLES Seven samples
111 8SAMPLES Eight samples
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6.12.3 STROBE – Event Strobe Register
If the STROBE register location is written, each event channel will be set according to the STROBE[n] and corresponding
DATA[n] bit settings, if any are unequal to zero.
A single event lasting for one peripheral clock cycle will be generated.
6.12.4 DATA – Event DATA Register
This register contains the data value when manually generating a data event. This register must be written before the
STROBE register. For details, see “STROBE – Event Strobe Register” on page 91.
6.12.5 DFCTRL – Digital Filter Control Register
Bit 7:4 – PRESCFILT[3:0]: Prescaler Filter
These bits define the prescaler filter settings, according to Table 6-9 on page 91.
Table 6-9. Prescaler Filter Settings
Bit 3 – FILTSEL: Prescaler Filter Select
Setting this bit enables the prescaler clock option on event channels 4 to 7. Clearing this bit enables the prescaler
clock option on event channels 0 to 3. This bit is used with settings defined by PRESCFILT bits.
Bit 2:0 – PRESC[2:0]: Prescaler
These bits select the digital filter clock prescaler settings, according to Table 6-10 on page 92.
Bit 76543210
+0x10 STROBE[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 76543210
+0x11 DATA[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 7654 3 2 1 0
+0x12 PRESCFILT[3:0] FILTSEL PRESC[2:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value0000 0 0 0 0
PRESCFILT[3:0] Group configuration Description
xxx1 CH04 Enable prescaler filter for either channel 0 or 4
xx1x CH15 Enable prescaler filter for either channel 1 or 5
x1xx CH26 Enable prescaler filter for either channel 2 or 6
1xxx CH37 Enable prescaler filter for either channel 3 or 7
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Table 6-10. Prescaler Options
PRESC[2:0] Group configuration Description
000 CLKPER_8 ClkPER divide by 23
001 CLKPER_64 ClkPER divide by 26
010 CLKPER_512 ClkPER divide by 29
011 CLKPER_4096 ClkPER divide by 212
100 CLKPER_32768 ClkPER divide by 215
101 (Reserved)
110 (Reserved)
1111 (Reserved)
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6.13 Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CH0MUX CH0MUX[7:0] 88
+0x01 CH1MUX CH1MUX[7:0] 88
+0x02 CH2MUX CH2MUX[7:0] 88
+0x03 CH3MUX CH3MUX[7:0] 88
+0x04 CH4MUX CH4MUX[7:0] 88
+0x05 CH5MUX CH5MUX[7:0] 88
+0x06 CH6MUX CH6MUX[7:0] 88
+0x07 CH7MUX CH7MUX[7:0] 88
+0x08 CH0CTRL ROTARY QDIRM[1:0] QDIEN QDEN DIGFILT[2:0] 90
+0x09 CH1CTRL - - - - - DIGFILT[2:0] 90
+0x0A CH2CTRL - - - - - DIGFILT[2:0] 90
+0x0B CH3CTRL - - - - - DIGFILT[2:0] 90
+0x0C CH4CTRL - - - - - DIGFILT[2:0] 90
+0x0D CH5CTRL - - - - - DIGFILT[2:0] 90
+0x0E CH6CTRL - - - - - DIGFILT[2:0] 90
+0x0F CH7CTRL - - - - - DIGFILT[2:0] 90
+0x10 STROBE STROBE[7:0] 91
+0x11 DATA DATA[7:0] 91
+0x12 DFCTRL PRESCFILT[3:0] FILTSEL PRESC[2:0] 91
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7. System Clock and Clock Options
7.1 Features
Fast start-up time
Safe run-time clock switching
Internal oscillators:
32MHz run-time calibrated oscillator
8MHz calibrated oscillator with 2MHz output and fast start-up
32.768kHz calibrated oscillator
32kHz ultra low power (ULP) oscillator with 1kHz output
External clock options
0.4MHz - 16MHz crystal oscillator
32.768kHz crystal oscillator
External clock
PLL with 20MHz - 128MHz output frequency
Internal and external clock options and 1× to 31× multiplication
Lock detector
Clock prescalers with 1× to 2048× division
Fast peripheral clocks running at 2 and 4 times the CPU clock
Automatic run-time calibration of internal 32MHz oscillator
External oscillator and PLL lock failure detection with optional non-maskable interrupt
7.2 Overview
XMEGA devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate
internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and
clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available,
and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and
temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal
oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz output of 8MHz internal oscillator. During normal operation, the system clock
source and prescalers can be changed from software at any time.
Figure 7-1 on page 95 presents the principal clock system in the XMEGA family of devices. Not all of the clocks need to
be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power
reduction registers, as described in “Power Management and Sleep Modes” on page 112.
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Figure 7-1. The Clock System, Clock Sources, and Clock Distribution
7.3 Clock Distribution
Figure 7-1 presents the principal clock distribution system used in XMEGA devices.
7.3.1 System Clock - ClkSYS
The system clock is the output from the main system clock selection. This is fed into the prescalers that are used to
generate all internal clocks except the asynchronous clocks.
Real Time
Counter Peripherals RAM AVR CPU Non-Volatile
Memory
Watchdog
Timer
Brown-out
Detector
System Clock Prescalers
System Clock Multiplexer
(SCLKSEL)
DIV32
32 kHz
Int. ULP
32.768 kHz
Int. OSC
32.768 kHz
TOSC
8MHz
Int. Osc
32 MHz
Int. Osc
0.4 16 MHz
XTAL
DIV32
DIV32
DIV4
PLL
TOSC1
TOSC2
XTAL1
XTAL2
clkSYS
clkRTC
clkPER2
clkPER
clkCPU
clkPER4
PC[4]
XOSCSEL
RTCSRC
PLLSRC
DIV4
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7.3.2 CPU Clock – ClkCPU
The CPU clock is routed to the CPU and nonvolatile memory. Halting the CPU clock inhibits the CPU from executing
instructions.
7.3.3 Peripheral Clock – ClkPER
The majority of peripherals and system modules use the peripheral clock. This includes the DMA controller, event
system, interrupt controller, external bus interface and RAM. This clock is always synchronous to the CPU clock, but may
run even when the CPU clock is turned off.
7.3.4 Peripheral 2x/4x Clocks – ClkPER2/ClkPER4
Modules that can run at two or four times the CPU clock frequency can use the peripheral 2× and peripheral 4× clocks.
7.3.5 Asynchronous Clock – ClkRTC
The asynchronous clock allows the real-time counter (RTC) to be clocked directly from an external 32.768kHz crystal
oscillator or the 32 times prescaled output from the internal 32.768kHz oscillator or ULP oscillator. The dedicated clock
domain allows operation of this peripheral even when the device is in sleep mode and the rest of the clocks are stopped.
7.4 Clock Sources
The clock sources are divided in two main groups; internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz output of 8MHz internal
oscillator. The other clock sources, DFLL and PLL, are turned off by default.
7.4.1 Internal Oscillators
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
7.4.1.1 32kHz Ultra Low Power Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a
1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
This oscillator can be selected as the clock source for the RTC.
7.4.1.2 32.768kHz Calibrated Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output.
7.4.1.3 32MHz Run-time Calibrated Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator
accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz.
7.4.1.4 8MHz Calibrated Oscillator
The 8MHz calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to
provide a default frequency close to its nominal frequency.
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7.4.2 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 or pin 4 from port C (PC4) can be used as input for an external clock signal. The TOSC1 and TOSC2 pins are
dedicated to driving a 32.768kHz crystal oscillator.
7.4.2.1 0.4MHz - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4MHz - 16MHz.
Figure 7-2 shows a typical connection of a crystal oscillator or resonator.
Figure 7-2. Crystal Oscillator Connection
Two capacitors, C1 and C2, may be added to match the required load capacitance for the connected crystal.
7.4.2.2 External Clock Input
To drive the device from an external clock source, XTAL1 pin must be driven as shown in Figure 7-3. In this mode,
XTAL2 can be used as a general I/O pin. Pin 4 from port C can be used as alternative position for external clock input.
Figure 7-3. External Clock Drive Configuration
C1
C2
XTAL2
XTAL1
GND
General
Purpose
I/O
XTAL2
XTAL1 / PC4
External
Clock
Signal
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7.4.2.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A typical connection is shown in Figure 7-4 on page 98. A low power mode with reduced
voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock and RTC, and as
the DFLL reference clock.
Figure 7-4. 32.768kHz Crystal Oscillator Connection
Two capacitors, C1 and C2, may be added to match the required load capacitance for the connected crystal. For details
on recommended TOSC characteristics and capacitor load, refer to device datasheet.
7.5 System Clock Selection and Prescalers
All the calibrated internal oscillators, the external clock sources (XOSC), and the PLL output can be used as the system
clock source. The system clock source is selectable from software, and can be changed during normal operation. Built-in
hardware protection prevents unsafe clock switching. It is not possible to select a non-stable or disabled oscillator as the
clock source, or to disable the oscillator currently used as the system clock source. Each oscillator option has a status
flag that can be read from software to check that the oscillator is ready.
The system clock is fed into a prescaler block that can divide the clock signal by a factor from 1 to 2048 before it is routed
to the CPU and peripherals. The prescaler settings can be changed from software during normal operation. The first
stage, prescaler A, can divide by a factor of from 1 to 512. Then, prescalers B and C can be individually configured to
either pass the clock through or combine divide it by a factor from 1 to 4. The prescaler guarantees that derived clocks
are always in phase, and that no glitches or intermediate frequencies occur when changing the prescaler setting. The
prescaler settings are updated in accordance with the rising edge of the slowest clock.
Figure 7-5. System Clock Selection and Prescalers
Prescaler A divides the system clock, and the resulting clock is clkPER4. Prescalers B and C can be enabled to divide the
clock speed further to enable peripheral modules to run at twice or four times the CPU clock frequency. If Prescalers B
and C are not used, all the clocks will run at the same frequency as the output from Prescaler A.
The system clock selection and prescaler registers are protected by the configuration change protection mechanism,
employing a timed write procedure for changing the system clock and prescaler settings. For details, refer to
“Configuration Change Protection” on page 13.
C1
C2
TOSC2
TOSC1
GND
Prescaler A
1, 2, 4, ... , 512
Prescaler B
1, 2, 4
Prescaler C
1, 2
Internal 8 MHz Osc.
Internal 32 .768 kHz Osc.
Internal 32 MHz Osc.
External Clock .
ClkCPU
Clock Selection
ClkPER
ClkSYS
ClkPER 2
ClkPER 4
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7.6 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-
selectable multiplication factor of from 1 to 31. The output frequency, fOUT, is given by the input frequency, fIN, multiplied
by the multiplication factor, PLL_FAC.
Four different clock sources can be chosen as input to the PLL:
2MHz output from 8MHz internal oscillator
8MHz internal oscillator
32MHz internal oscillator divided by 4
0.4MHz - 16MHz crystal oscillator
External clock
To enable the PLL, the following procedure must be followed:
1. Enable reference clock source.
2. Set the multiplication factor and select the clock reference for the PLL.
3. Wait until the clock reference source is stable.
4. Enable the PLL.
Hardware ensures that the PLL configuration cannot be changed when the PLL is in use. The PLL must be disabled
before a new configuration can be written.
It is not possible to use the PLL before the selected clock source is stable and the PLL has locked.
The reference clock source cannot be disabled while the PLL is running.
7.7 DFLL 32MHz
Built-in digital frequency locked loop (DFLL) can be used to improve the accuracy of the 32MHz internal oscillators. The
DFLL compares the oscillator frequency with a more accurate reference clock to do automatic run-time calibration of the
oscillator and compensate for temperature and voltage drift. The choices for the reference clock sources are:
32.768kHz calibrated internal oscillator
32.768kHz crystal oscillator connected to the TOSC pins
External clock
The DFLL divides the oscillator reference clock by 32 to use a 1.024kHz reference. The reference clock is individually
selected for each DFLL, as shown in Figure 7-6 on page 99.
Figure 7-6. DFLL Reference Clock Selection
FACPLLff INOUT _*
32.768 kHz Crystal Osc
External Clock
32.768 kHz Int. Osc
DFLL32M
32 MHz Int. OSC
clkRC 32MCREF
TOSC1
TOSC2
XTAL1
DIV32
XOSCSEL
PC4
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The value that should be written to the COMP register is given by the following formula:
When the DFLL is enabled, it controls the ratio between the reference clock frequency and the oscillator frequency. If the
internal oscillator runs too fast or too slow, the DFLL will decrement or increment its calibration register value by one to
adjust the oscillator frequency. The oscillator is considered running too fast or too slow when the error is more than a half
calibration step size.
Figure 7-7. Automatic Run-time Calibration
The DFLL will stop when entering a sleep mode where the oscillators are stopped. After wake up, the DFLL will continue
with the calibration value found before entering sleep. The reset value of the DFLL calibration register can be read from
the production signature row.
When the DFLL is disabled, the DFLL calibration register can be written from software for manual run-time calibration of
the oscillator.
7.8 PLL and External Clock Source Failure Monitor
A built-in failure monitor is available for the PLL and external clock source. If the failure monitor is enabled for the PLL
and/or the external clock source, and this clock source fails (the PLL looses lock or the external clock source stops) while
being used as the system clock, the device will:
Switch to run the system clock from the 2MHz output from 8MHz internal oscillator
Reset the oscillator control register and system clock selection register to their default values
Set the failure detection interrupt flag for the failing clock source (PLL or external clock)
Issue a non-maskable interrupt (NMI)
If the PLL or external clock source fails when not being used for the system clock, it is automatically disabled, and the
system clock will continue to operate normally. No NMI is issued. The failure monitor is meant for external clock sources
above 32kHz. It cannot be used for slower external clocks.
When the failure monitor is enabled, it will not be disabled until the next reset.
The failure monitor is stopped in all sleep modes where the PLL or external clock source, are stopped. During wake up
from sleep, it is automatically restarted.
The PLL and external clock source failure monitor settings are protected by the configuration change protection
mechanism, employing a timed write procedure for changing the settings. For details, refer to “Configuration Change
Protection” on page 13.
)(
32MCREFRC
OSC
f
f
hexCOMP
DFLL CNT
COMP
0
tRCnCREF
Frequency
OK RCOSC fast,
CALA decremented
RCOSC slow,
CALA incremented
clkRC32MCREF
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7.9 Register Description – Clock
7.9.1 CTRL – Control Register
This register is write protected if the bit LOCK has been set in the LOCK register.
Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2:0 – SCLKSEL[2:0]: System Clock Selection
These bits are used to select the source for the system clock. See Table 7-1 for the different selections. Changing
the system clock source will take two clock cycles on the old clock source and two more clock cycles on the new
clock source. These bits are protected by the configuration change protection mechanism. For details, refer to
“Configuration Change Protection” on page 13.
SCLKSEL cannot be changed if the new clock source is not stable. The old clock can not be disabled until the
clock switching is completed.
Table 7-1. System Clock Selection
7.9.2 PSCTRL – Prescaler Register
This register is write protected if the bit LOCK has been set in the LOCK register.
Bit 7 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 6:2 – PSADIV[4:0]: Prescaler A Division Factor
These bits define the division ratio of the clock prescaler A according to Table 7-2. These bits can be written at
run-time to change the frequency of the ClkPER4 clock relative to the system clock, ClkSYS.
Bit 76543210
+0x00 ––––– SCLKSEL[2:0]
Read/Write R R R R R R/W R/W R/W
Initial value00000000
SCLKSEL[2:0] Group configuration Description
000 RC2MHZ 2MHz from 8MHz internal oscillator
001 RC32MHZ 32MHz internal oscillator
010 RC32KHZ 32.768kHz internal oscillator
011 XOSC External oscillator or clock
100 PLL Phase locked loop
101 RC8MHZ 8MHz internal oscillator
110 Reserved
111 Reserved
Bit 76543210
+0x01 – PSADIV[4:0] PSBCDIV[1:0]
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
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Table 7-2. Prescaler A Division Factor
Bit 1:0 – PSBCDIV[1:0]: Prescaler B and C Division Factors
These bits define the division ratio of the clock prescalers B and C according to Table 7-3 on page 102. Prescaler
B will set the clock frequency for the ClkPER2 clock relative to the ClkPER4 clock. Prescaler C will set the clock fre-
quency for the ClkPER and ClkCPU clocks relative to the ClkPER2 clock. Refer to Figure 7-5 on page 98 for more
details.
Table 7-3. Prescaler B and C Division Factors
PSADIV[4:0] Group configuration Description
00000 1No division
00001 2Divide by 2
00011 4Divide by 4
00101 8Divide by 8
00111 16 Divide by 16
01001 32 Divide by 32
01011 64 Divide by 64
01101 128 Divide by 128
01111 256 Divide by 256
10001 512 Divide by 512
10011 6Divide by 6
10101 10 Divide by 10
10111 12 Divide by 12
11001 24 Divide by 24
11011 48 Divide by 48
11101 Reserved
11111 Reserved
PSBCDIV[1:0] Group configuration Prescaler B division Prescaler C division
00 1_1 No division No division
01 1_2 No division Divide by 2
10 4_1 Divide by 4 No division
11 2_2 Divide by 2 Divide by 2
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7.9.3 LOCK – Lock Register
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – LOCK: Clock System Lock
When this bit is written to one, the CTRL and PSCTRL registers cannot be changed, and the system clock selec-
tion and prescaler settings are protected against all further updates until after the next reset. This bit is protected
by the configuration change protection mechanism. For details, refer to “Configuration Change Protection” on page
13.
The LOCK bit can be cleared only by a reset.
7.9.4 RTCCTRL – RTC Control Register
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:1 – RTCSRC[2:0]: RTC Clock Source
These bits select the clock source for the real-time counter according to Table 7-4 on page 103.
Table 7-4. RTC Clock Source Selection
Bit 0 – RTCEN: RTC Clock Source Enable
Setting the RTCEN bit enables the selected RTC clock source for the real-time counter.
Bit 76543210
+0x02 – – – – – – –LOCK
Read/Write R R R R R R R R/W
Initial value00000000
Bit 76543210
+0x03 ––– RTCSRC[2:0] RTCEN
Read/Write R R RRRRRR/W
Initial value00000000
RTCSRC[2:0] Group configuration Description
000 ULP 1kHz from 32kHz internal ULP oscillator
001 TOSC 1.024kHz from 32.768kHz crystal oscillator on TOSC
010 RCOSC 1.024kHz from 32.768kHz internal oscillator
011 -Reserved
100 -Reserved
101 TOSC32 32.768kHz from 32.768kHz crystal oscillator on TOSC
110 RCOSC32 32.768kHz from 32.768kHz internal oscillator
111 EXTCLK External clock from TOSC1
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7.10 Register Description – Oscillator
7.10.1 CTRL – Oscillator Control Register
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 6 – RC8MLPM: 8MHz Internal Oscillator Low Power Mode
Setting this bit enables the low power mode for the internal 8MHz oscillator. For details on characteristics and
accuracy of the internal oscillator in this mode, refer to the device datasheet.
Bit 5 – RC8MEN: 8MHz Internal Oscillator Enable
Setting this bit will enable the 8MHz output of the internal oscillator. The oscillator must be stable before it is
selected as the source for the system clock. See “STATUS – Oscillator Status Register” on page 104.
Bit 4 – PLLEN: PLL Enable
Setting this bit enables the PLL. Before the PLL is enabled, it must be configured with the desired multiplication
factor and clock source. See “STATUS – Oscillator Status Register” on page 104.
Bit 3 – XOSCEN: External Oscillator Enable
Setting this bit enables the selected external clock source. Refer to “XOSCCTRL – XOSC Control Register” on
page 105 for details on how to select the external clock source. The external clock source should be allowed time
to stabilize before it is selected as the source for the system clock. See “STATUS – Oscillator Status Register” on
page 104.
Bit 2 – RC32KEN: 32.768kHz Internal Oscillator Enable
Setting this bit enables the 32.768kHz internal oscillator. The oscillator must be stable before it is selected as the
source for the system clock. See “STATUS – Oscillator Status Register” on page 104.
Bit 1 – RC32MEN: 32MHz Internal Oscillator Enable
Setting this bit will enable the 32MHz internal oscillator. The oscillator must be stable before it is selected as the
source for the system clock. See “STATUS – Oscillator Status Register” on page 104.
Bit 0 – RC2MEN: 2MHz Internal Oscillator Enable
Setting this bit will enable the 2MHz output of 8MHz internal oscillator. The oscillator must be stable before it is
selected as the source for the system clock. See “STATUS – Oscillator Status Register” on page 104.
By default, the 2MHz output from RC8MHz internal oscillator is enabled and this bit is set.
7.10.2 STATUS – Oscillator Status Register
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5 – RC8MRDY: 8MHz Internal Oscillator Ready
This flag is set when the 8MHz output from RC8MHz internal oscillator is stable and is ready to be used as the sys-
tem clock source.
Bit 7 6 543 2 1 0
+0x00 RC8MLPM RC8MEN PLLEN XOSCEN RC32KEN RC32MEN RC2MEN
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 1
Bit 7 6 5 4 3 2 1 0
+0x01 RC8MRDY PLLRDY XOSCRDY RC32KRDY RC32MRDY RC2MRDY
Read/Write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
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Bit 4 – PLLRDY: PLL Ready
This flag is set when the PLL has locked on the selected frequency and is ready to be used as the system clock
source.
Bit 3 – XOSCRDY: External Clock Source Ready
This flag is set when the external clock source is stable and is ready to be used as the system clock source.
Bit 2 – RC32KRDY: 32.768kHz Internal Oscillator Ready
This flag is set when the 32.768kHz internal oscillator is stable and is ready to be used as the system clock source.
Bit 1 – RC32MRDY: 32MHz Internal Oscillator Ready
This flag is set when the 32MHz internal oscillator is stable and is ready to be used as the system clock source.
Bit 0 – RC2MRDY: 2MHz Internal Oscillator Ready
This flag is set when the 2MHz output from RC8MHz internal oscillator is stable and is ready to be used as the sys-
tem clock source.
7.10.3 XOSCCTRL – XOSC Control Register
Bit 7:6 – FRQRANGE[1:0]: 0.4 - 16MHz Crystal Oscillator Frequency Range Select
These bits select the frequency range for the connected crystal oscillator according to Table 7-5 on page 105.
Table 7-5. 16MHz Crystal Oscillator Frequency Range Selection(1)
Note: 1. Refer to Electrical Characteristics in device datasheet for finding the best setting for a given frequency.
Bit 5 – X32KLPM: Crystal Oscillator 32.768kHz Low Power Mode
Setting this bit enables the low power mode for the 32.768kHz crystal oscillator. This will reduce the swing on the
TOSC2 pin.
Bit 4 – XOSCPWR: Crystal Oscillator Drive
Setting this bit will increase the current in the 0.4MHz - 16MHz crystal oscillator and increase the swing on the
XTAL2 pin. This allows for driving crystals with higher load or higher frequency than specified by the FRQRANGE
bits.
Bit 4 – XOSCSEL[4]: Crystal Oscillator Selection
This bit selects the pin position from which the external clock is used. When cleared, the external clock pin is
XTAL1 pin. When set, the external clock pin is port C, pin 4. The selection is ignored if XOSCSEL[3:0] settings do
not select the external clock option. For more details, refer to Table 7-6.
Bit 3:0 – XOSCSEL[3:0]: Crystal Oscillator Selection
These bits select the type and start-up time for the crystal or resonator that is connected to the XTAL or TOSC
pins. See Table 7-6 for crystal selections. If an external clock or external oscillator is selected as the source for the
system clock, see “CTRL – Oscillator Control Register” on page 104. This configuration cannot be changed.
Bit 7 6 5 4 3210
+0x02 FRQRANGE[1:0] X32KLPM XOSCPWR XOSCSEL[3:0]
XOSCSEL[4]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value0 0 0 0 0000
FRQRANGE[1:0] Group configuration Typical frequency range
[MHz] Recommended range for capacitors
C1 and C2 [pF]
00 04TO2 0.4 - 2 100-300
01 2TO9 2 - 9 10-40
10 9TO12 9 - 12 10-40
11 12TO16 12 - 16 10-30
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Table 7-6. 16MHz Crystal Oscillator Frequency Range Selection
Notes: 1. This option should be used only when frequency stability at startup is not important for the application. The option is not suitable for crystals.
2. This option is intended for use with ceramic resonators. It can also be used when the frequency stability at startup is not important for the
application.
3. When the external oscillator is used as the reference for a DFLL, only EXTCLK and 32KHZ can be selected.
7.10.4 XOSCFAIL – XOSC Failure Detection Register
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3 – PLLFDIF: PLL Fault Detection Flag
If PLL failure detection is enabled, PLLFDIF is set when the PLL looses lock. Writing logic one to this location will
clear PLLFDIF.
Bit 2 – PLLFDEN: PLL Fault Detection Enable
Setting this bit will enable PLL failure detection. A non-maskable interrupt will be issued when PLLFDIF is set.
This bit is protected by the configuration change protection mechanism. Refer to “Configuration Change Protec-
tion” on page 13 for details.
Bit 1 – XOSCFDIF: Failure Detection Interrupt Flag
If the external clock source oscillator failure monitor is enabled, XOSCFDIF is set when a failure is detected. Writ-
ing logic one to this location will clear XOSCFDIF.
Bit 0 – XOSCFDEN: Failure Detection Enable
Setting this bit will enable the failure detection monitor, and a non-maskable interrupt will be issued when
XOSCFDIF is set.
This bit is protected by the configuration change protection mechanism. Refer to “Configuration Change Protec-
tion” on page 13 for details. Once enabled, failure detection can only be disabled by a reset.
XOSCSEL[3:0] Group configuration Selected clock source Start-up time
0000 EXTCLK (3) External Clock from XTAL1 pin 6 CLK
0010 32KHZ (3) 32.768kHz TOSC 16K CLK
0011 XTAL_256CLK (1) 0.4MHz - 16MHz XTAL 256 CLK
0111 XTAL_1KCLK (2) 0.4MHz - 16MHz XTAL 1K CLK
1011 XTAL_16KCLK 0.4MHz - 16MHz XTAL 16K CLK
Bit 765432 1 0
+0x03 ––– PLLFDIF PLLFDEN XOSCFDIF XOSCFDEN
Read/Write RRRRR/WR/WR/WR/W
Initial value000000 0 0
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7.10.5 RC32KCAL – 32kHz Oscillator Calibration Register
Bit 7:0 – RC32KCAL[7:0]: 32.768kHz Internal Oscillator Calibration Bits
This register is used to calibrate the 32.768kHz internal oscillator. A factory-calibrated value is loaded from the sig-
nature row of the device and written to this register during reset, giving an oscillator frequency close to 32.768kHz.
The register can also be written from software to calibrate the oscillator frequency during normal operation.
7.10.6 PLLCTRL – PLL Control Register
Bit 7:6 – PLLSRC[1:0]: Clock Source
The PLLSRC bits select the input source for the PLL according to Table 7-7.
Table 7-7. PLL Clock Source
Note: 1. The 32.768kHz TOSC cannot be selected as the source for the PLL. An external clock must be a minimum 0.4MHz to be used as the source clock.
Bit 5 – PLLDIV: PLL Divided Output Enable
Setting this bit will divide the output from the PLL by 2.
Bit 4:0 – PLLFAC[4:0]: Multiplication Factor
These bits select the multiplication factor for the PLL. The multiplication factor can be in the range of from 1x to
31x.
7.10.7 DFLLCTRL – DFLL Control Register
Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 76543210
+0x04 RC32KCAL[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 76543210
+0x05 PLLSRC[1:0] PLLDIV PLLFAC[4:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
PLLSRC[1:0] Group configuration Description
00 RC2M 2MHz output from 8MHz internal oscillator.
01 RC8M 8MHz output from 8MHz internal oscillator.
10 RC32M 32MHz internal oscillator.
11 XOSC External clock source (1)
Bit 765432 1 0
+0x06 ––––– RC32MCREF[1:0]
Read/Write RRRRRR/W R/W R
Initial value000000 0 0
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Bit 2:1 – RC32MCREF[1:0]: 32MHz Oscillator Calibration Reference
These bits are used to select the calibration source for the 32MHz DFLL according to the Table 7-8 on page 108.
These bits will select only which calibration source to use for the DFLL. In addition, the actual clock source that is
selected must enabled and configured for the calibration to function.
Table 7-8. 32MHz Oscillator Reference Selection
Bit 0 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
7.10.8 RC8MCAL – 8MHz Internal Oscillator Calibration Register
Bit 7:0 – RC8MCAL[7:0]: 8MHz Internal Oscillator Calibration Bits
This register is used to calibrate the 8MHz internal oscillator. A factory-calibrated value is loaded from the signa-
ture row of the device and written to this register during reset, giving an oscillator frequency close to 8MHz. The
register can also be written from software to calibrate the oscillator frequency during normal operation.
7.11 Register Description – DFLL32M
7.11.1 CTRL – DFLL Control Register
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – ENABLE: DFLL Enable
Setting this bit enables the DFLL and auto-calibration of the internal oscillator. The reference clock must be
enabled and stable before the DFLL is enabled.
After disabling the DFLL, the reference clock can not be disabled before the ENABLE bit is read as zero.
RC32MCREF[1:0] Group configuration Description
00 RC32K 32.768kHz internal oscillator.
01 XOSC32 32.768kHz crystal oscillator on TOSC.
1x Reserved
Bit 76543210
+0x07 RC8MCAL[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Bit 7654321 0
+0x00 ––––––– ENABLE
Read/Write R R R R R R R R/W
Initial value0000000 0
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7.11.2 CALA – DFLL Calibration Register A
The CALA and CALB registers hold the 13-bit DFLL calibration value that is used for automatic run-time calibration of the
internal oscillator. When the DFLL is disabled, the calibration registers can be written by software for manual run-time
calibration of the oscillator. The oscillators will also be calibrated according to the calibration value in these registers
when the DFLL is disabled.
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 6:0 – CALA[6:0]: DFLL Calibration Bits
These bits hold the part of the oscillator calibration value that is used for automatic runtime calibration. A factory-
calibrated value is loaded from the signature row of the device and written to this register during reset, giving an
oscillator frequency approximate to the nominal frequency for the oscillator. The bits cannot be written when the
DFLL is enabled.
7.11.3 CALB – DFLL Calibration Register B
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5:0 – CALB[5:0]: DFLL Calibration Bits
These bits hold the part of the oscillator calibration value that is used to select the oscillator frequency. A factory-
calibrated value is loaded from the signature row of the device and written to this register during reset, giving an
oscillator frequency approximate to the nominal frequency for the oscillator. These bits are not changed during
automatic run-time calibration of the oscillator. The bits cannot be written when the DFLL is enabled. When cali-
brating to a frequency different from the default, the CALA bits should be set to a middle value to maximize the
range for the DFLL.
7.11.4 COMP1 – DFLL Compare Register 1
The COMP1 and COMP2 register pair represent the frequency ratio between the oscillator and the reference clock. The
initial value for these registers is the ratio between the internal oscillator frequency and a 1.024kHz reference.
Bit 7:0 – COMP1[7:0]: Compare Value Byte 1
These bits hold byte 1 of the 16-bit compare register.
Bit 76543210
+0x02 – CALA[6:0]
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial value0xxxxxxx
Bit 76543210
+0x03 – CALB[5:0]
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial value 0 0 x x x x x x
Bit 7 6 5 4 3 2 1 0
+0x05 COMP[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
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7.11.5 COMP2 – DFLL Compare Register 2
Bit 7:0 – COMP2[15:8]: Compare Value Byte 2
These bits hold byte 2 of the 16-bit compare register.
Table 7-9. Nominal DFLL32M COMP Values for Different Output Frequencies
Bit 76543210
+0x06 COMP[15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
Oscillator frequency [MHz] COMP value (ClkRC32MCREF = 1.024kHz)
30.0 0x7270
32.0 0x7A12
34.0 0x81B3
36.0 0x8954
38.0 0x90F5
40.0 0x9896
42.0 0xA037
44.0 0xA7D8
46.0 0xAF79
48.0 0xB71B
50.0 0xBEBC
52.0 0xC65D
54.0 0xCDFE
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7.12 Register Summary - Clock
7.13 Register Summary - Oscillator
7.14 Register Summary – DFLL32M
7.15 Interrupt Vector Summary
Table 7-10. Oscillator Failure Interrupt Vector and its Word Offset Address PLL and External Oscillator Failure Interrupt Base
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL – – SCLKSEL[2:0] 101
+0x01 PSCTRL PSADIV[4:0] PSBCDIV[1:0] 101
+0x02 LOCK – – –LOCK103
+0x03 RTCCTRL – – RTCSRC[2:0] RTCEN 103
+0x04 Reserved – –
+0x05 Reserved – –
+0x06 Reserved – –
+0x07 Reserved – –
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL RC8MLPM RC8MEN PLLEN XOSCEN RC32KEN RC32MEN RC2MEN 104
+0x01 STATUS RC8MRDY PLLRDY XOSCRDY RC32KRDY RC32MRDY RC2MRDY 104
+0x02 XOSCCTRL FRQRANGE[1:0] X32KLPM XOSCPWR XOSCSEL[3:0] 105
XOSCSEL[4]
+0x03 XOSCFAIL – – PLLFDIF PLLFDEN XOSCFDIF XOSCFDEN 106
+0x04 RC32KCAL RC32KCAL[7:0] 107
+0x05 PLLCTRL PLLSRC[1:0] PLLDIV PLLFAC[4:0] 107
+0x06 DFLLCTRL – – – RC32MMCREF[1:0] 107
+0x07 RC8MCAL RC8MCAL[7:0] 108
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL – – ENABLE 108
+0x01 Reserved – –
+0x02 CALA CALA[6:0] 109
+0x03 CALB CALB[5:0] 109
+0x04 Reserved – –
+0x05 COMP1 COMP[7:0] 109
+0x06 COMP2 COMP[15:8] 110
+0x07 Reserved – –
Offset Source Interrupt description
0x00 OSCF_vect PLL and external oscillator failure interrupt vector (NMI)
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8. Power Management and Sleep Modes
8.1 Features
Power management for adjusting power consumption and functions
Five sleep modes:
Idle
Power down
Power save
Standby
Extended standby
Power reduction register to disable clock and turn off unused peripherals in active and idle modes
8.2 Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
8.3 Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
Table 8-1 on page 113 shows the different sleep modes and the active clock domains, oscillators, and wake-up sources.
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Table 8-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Note: 1. Only from internal 8MHz oscillator in low power mode.
The wake-up time for the device is dependent on the sleep mode and the main clock source. The startup time for the
system clock source must be added to the wake-up time for sleep modes where the system clock source is not kept
running. For details on the startup time for the different oscillator options, refer to “System Clock and Clock Options” on
page 94.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
8.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled
interrupt will wake the device.
8.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-
wire interface address match interrupt, and asynchronous port interrupts.
8.3.3 Power-save Mode
Power-save mode is identical to power down, with two exceptions. If the real-time counter (RTC) is enabled, it will keep
running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.
If the UART start frame detector is enabled, the device can also wake-up from any UART interrupt, including start frame
interrupt. The internal 8MHz in low power mode must be used to wake-up the device from UART interrupts.
Active clock domain Oscillators Wake-up sources
Sleep modes
CPU clock
Peripheral clock
RTC clock
System clock source
RTC clock source
UART start of frame
Asynchronous port interrupts
TWI address match interrupts
Real time clock interrupts
All interrupts
Idle X X X X X X X X
Power down X X
Power save X X X(1) X X X
Standby X X X X
Extended standby X X X X X X X
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8.3.4 Standby Mode
Standby mode is identical to power down, with two exceptions.
To reduce the wake-up time, the enabled system clock sources are kept running while the CPU, peripheral, and RTC
clocks are stopped. If the UART start frame detector is enabled, the device can also wake-up from any UART interrupt,
including start frame interrupt.
8.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
If the UART start frame detector is enabled, the device can also wake-up from any UART interrupt, including start frame
interrupt.
8.4 Power Reduction Registers
The power reduction (PR) registers provide a method to stop the clock to individual peripherals. When this is done, the
current state of the peripheral is frozen and the associated I/O registers cannot be read or written. Resources used by the
peripheral will remain occupied; hence, the peripheral should be disabled before stopping the clock. Enabling the clock to
a peripheral again puts the peripheral in the same state as before it was stopped. This can be used in idle mode and
active modes to reduce the overall power consumption. In all other sleep modes, the peripheral clock is already stopped.
Not all devices have all the peripherals associated with a bit in the power reduction registers. Setting a power reduction
bit for a peripheral that is not available will have no effect.
8.5 Minimizing Power Consumption
There are several possibilities to consider when trying to minimize the power consumption in an AVR MCU controlled
system. In general, correct sleep modes should be selected and used to ensure that only the modules required for the
application are operating.
All unneeded functions should be disabled. In particular, the following modules may need special consideration when
trying to achieve the lowest possible power consumption.
8.5.1 Analog-to-Digital Converter - ADC
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any
sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to
“ADC – Analog to Digital Converter” on page 349 for details on ADC operation.
8.5.2 Analog Comparator - AC
When entering idle mode, the analog comparator should be disabled if not used. In other sleep modes, the analog
comparator is automatically disabled. However, if the analog comparator is set up to use the internal voltage reference as
input, the analog comparator should be disabled in all sleep modes. Otherwise, the internal voltage reference will be
enabled, irrespective of sleep mode. Refer to “AC – Analog Comparator” on page 391 for details on how to configure the
analog comparator.
8.5.3 Brownout Detector
If the brownout detector is not needed by the application, this module should be turned off. If the brownout detector is
enabled by the BODLEVEL fuses, it will be enabled in all sleep modes, and always consume power. In the deeper sleep
modes, it can be turned off and set in sampled mode to reduce current consumption. Refer to “Brownout Detection” on
page 122 for details on how to configure the brownout detector.
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8.5.4 Watchdog Timer
If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled,
it will be enabled in all sleep modes and, hence, always consume power. Refer to “WDT – Watchdog Timer” on page 127
for details on how to configure the watchdog timer.
8.5.5 Internal 8MHz Oscillator
If the low power mode is not needed by the application, this feature should be turned off. If the lower mode is enabled, it
will be enabled in all sleep modes, and always consume power. Refer to “8MHz Calibrated Oscillator” on page 96 for
details on how to enable the low power mode.
8.5.6 UART Start Frame Detector
When entering the standby, extended standby or power save mode, the UART start frame detector should be disabled if
not used. When entering the power down sleep mode, the UART start frame detector must be disabled. In all other sleep
modes, the UART start frame detector is ignored. Refer to “USART” on page 279 for details on how to enable the start
frame detector.
8.5.7 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. Most important is to ensure that
no pins drive resistive loads. If the pin input sense is forced enabled, the corresponding pin input buffer will be enabled in
all sleep modes, and always consume power. If the input sense is not forced enabled, in sleep modes where the
Peripheral Clock (ClkPER) is stopped, the input buffers of the device will be disabled. This ensures that no power is
consumed by the input logic when not needed.
When the UART start frame detector is enabled, the input buffers of the corresponding UART pins are forced enabled
when entering sleep modes, and always consume power.
8.5.8 On-chip Debug System
If the On-chip debug system is enabled and the chip enters sleep mode, the main clock source is enabled and hence
always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.
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8.6 Register Description – Sleep
8.6.1 CTRL – Control Register
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:1 – SMODE[2:0]: Sleep Mode Selection
These bits select sleep modes according to Table 8-2 on page 116.
Table 8-2. Sleep Mode
Bit 0 – SEN: Sleep Enable
This bit must be set to make the MCU enter the selected sleep mode when the SLEEP instruction is executed. To
avoid unintentional entering of sleep modes, it is recommended to write SEN just before executing the SLEEP
instruction and clear it immediately after waking up.
Bit 76543210
+0x00 ––– SMODE[2:0] SEN
Read/Write R R R R R/W R/W R/W R/W
Initial Value00000000
SMODE[2:0] Group configuration Description
000 IDLE Idle mode
001 Reserved
010 PDOWN Power-down mode
011 PSAVE Power-save mode
100 Reserved
101 Reserved
110 STDBY Standby mode
111 ESTDBY Extended standby mode
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8.7 Register Description – Power Reduction
8.7.1 PRGEN – General Power Reduction Register
Bit 7 – XCL: XMEGA Custom Logic
Setting this bit stops the clock to the XMEGA Custom Logic. When this bit is cleared, the peripheral should be rein-
itialized to ensure proper operation.
Bit 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2 – RTC: Real-Time Counter
Setting this bit stops the clock to the real-time counter. When this bit is cleared, the peripheral should be reinitial-
ized to ensure proper operation.
Bit 1 – EVSYS: Event System
Setting this stops the clock to the event system. When this bit is cleared, the module will continue as before it was
stopped.
Bit 0 –EDMA: EDMA Controller
Setting this bit stops the clock to the EDMA controller. This bit can be set only if the EDMA controller is disabled.
8.7.2 PRPA – Power Reduction Port A Register
Note: Disabling of analog modules stops the clock to the analog blocks themselves and not only the interfaces.
Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2 – DAC: Power Reduction DAC
Setting this bit stops the clock to the DAC. The DAC should be disabled before stopped.
Bit 1 – ADC: Power Reduction ADC
Setting this bit stops the clock to the ADC. The ADC should be disabled before stopped.
Bit 0 – AC: Power Reduction Analog Comparator
Setting this bit stops the clock to the analog comparator. The AC should be disabled before shutdown.
Bit 76543210
+0x00 XCL ––– RTC EVSYS EDMA
Read/Write R/W R R R R R/W R/W R/W
Initial Value00000000
Bit 765432 1 0
+0x01 –––– DAC ADC AC
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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8.7.3 PRPC/D – Power Reduction Port C/D Register
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 6 – TWI: Two-Wire Interface
Setting this bit stops the clock to the two-wire interface. When this bit is cleared, the peripheral should be reinitial-
ized to ensure proper operation.
Bit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 4 – USART0
Setting this bit stops the clock to USART0. When this bit is cleared, the peripheral should be reinitialized to ensure
proper operation.
Bit 3 – SPI: Serial Peripheral Interface
Setting this bit stops the clock to the SPI. When this bit is cleared, the peripheral should be reinitialized to ensure
proper operation.
Bit 2 – HIRES: High-Resolution Extension
Setting this bit stops the clock to the high-resolution extension for the timer/counters. When this bit is cleared, the
peripheral should be reinitialized to ensure proper operation.
Bit 1 – TC5: Timer/Counter 5
Setting this bit stops the clock to timer/counter 5. When this bit is cleared, the peripheral will continue like before
the shut down.
Bit 0 – TC4: Timer/Counter 4
Setting this bit stops the clock to timer/counter 4. When this bit is cleared, the peripheral will continue like before
the shut down.
Bit 76543210
+0x03/+0x04 –TWI USART0 SPI HIRES TC5 TC4
Read/Write R R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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8.8 Register Summary – Sleep
8.9 Register Summary – Power Reduction
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL – – – SMODE[2:0] SEN 116
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 PRGEN XCL – – RTC EVSYS EDMA 117
+0x01 PRPA – – – DAC ADC AC 117
+0x02 Reserved – – –
+0x03 PRPC –TWI USART0 SPI HIRES TC5 TC4 118
+0x04 PRPD – – – USART0 –TC5 118
+0x05 Reserved – – –
+0x06 Reserved – – –
+0x07 Reserved – – –
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9. Reset System
9.1 Features
Reset the microcontroller and set it to initial state when a reset source goes active
Multiple reset sources that cover different situations
Power-on reset
External reset
Watchdog reset
Brownout reset
PDI reset
Software reset
Asynchronous operation
No running system clock in the device is required for reset
Reset status register for reading the reset source from the application code
9.2 Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontrollers operates below its power supply rating. If a
reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O
pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to
their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the
content of the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
An overview of the reset system is shown in Figure 9-1 on page 121.
Ewmm #2132. a s R j \ Ewwm mmpzzoo 17W, Vcc RESET
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Figure 9-1. Reset System Overview
9.3 Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
Reset counter delay
Oscillator startup
Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
9.3.1 Reset Counter
The reset counter can delay reset release with a programmable period from when all reset requests are released. The
reset delay is timed from the 1kHz output of the ultra low power (ULP) internal oscillator, and in addition 24 system clock
cycles (clkSYS) are counted before reset is released. The reset delay is set by the STARTUPTIME fuse bits. The
selectable delays are shown in Table 9-1 on page 121.
Table 9-1. Reset Delay
Whenever a reset occurs, the clock system is reset and the 2MHz output from the internal 8MHz oscillator is chosen as
the source for ClkSYS.
MCU Status
Register (MCUSR)
Brown-out
Reset
BODLEVEL [2:0]
Delay Counters TIMEOUT
WDRF
BORF
EXTRF
PORF
ULP
Oscillator
SPIKE
FILTER
Pull-up Resistor
JTRF
Watchdog
Reset
SUT[1:0]
Power-on Reset
Software
Reset
External
Reset
PDI
Reset
SUT[1:0] Number of 1kHz ULP oscillator clock cycles Recommended usage
00 64K ClkULP+ 24 ClkSYS Stable frequency at startup
01 4K ClkULP + 24 ClkSYS Slowly rising power
10 Reserved
11 24 ClkSYS Fast rising power or BOD enabled
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9.3.2 Oscillator Startup
After the reset delay, the 8MHz internal oscillator clock is started, and its calibration values are automatically loaded from
the production signature row to the calibration registers.
9.4 Reset Sources
9.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.
Figure 9-2. MCU Startup, RESET Tied to VCC
Figure 9-3. MCU Startup, RESET Extended Externally
9.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
When the BOD is enabled and VCC decreases to a value below the trigger level (VBOT- in Figure 9-4 on page 123), the
brownout reset is immediately activated.
When VCC increases above the trigger level (VBOT+ in Figure 9-4 on page 123), the reset counter starts the MCU after the
timeout period, tTOUT has expired.
The trigger level has a hysteresis to ensure spike free brownout detection. The hysteresis on the detection level should
be interpreted as VBOT+= VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
The BOD circuit will detect a drop in VCC only if the voltage stays below the trigger level for longer than tBOD.
V
RESET
TIME-OUT
INTERNAL
RESET
tTOUT
VPOT
VRST
CC
RESET
TIME-OUT
INTERNAL
RESET
tTOUT
VPOT
VRST
VCC
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Figure 9-4. Brownout Detection Reset
For BOD characterization data consult the device datasheet. The programmable BODLEVEL setting is shown in Table 9-
2.
Table 9-2. Programmable BODLEVEL Setting
Notes: 1. The values are nominal values only. For accurate, actual numbers, consult the device datasheet.
2. Changing these fuse bits will have no effect until leaving programming mode.
The BOD circuit has three modes of operation:
Disabled: In this mode, there is no monitoring of the VCC level.
Enabled: In this mode, the VCC level is continuously monitored, and a drop in VCC below VBOT for a period of tBOD
will give a brownout reset.
Sampled: In this mode, the BOD circuit will sample the VCC level with a period identical to that of the 1kHz output
from the ultra low power (ULP) internal oscillator. Between each sample, the BOD is turned off. This mode will
reduce the power consumption compared to the enabled mode, but a fall in the VCC level between two positive
edges of the 1kHz ULP oscillator output will not be detected. If a brownout is detected in this mode, the BOD circuit
is set in enabled mode to ensure that the device is kept in reset until VCC is above VBOT again.
The BODACT fuse determines the BOD setting for active mode and idle mode, while the BODPD fuse determines the
brownout detection setting for all sleep modes, except idle mode.
BOD level Fuse BODLEVEL[2:0](2) VBOT(1) Unit
BOD level 0 111 1.6
V
BOD level 1 110 1.8
BOD level 2 101 2.0
BOD level 3 100 2.2
BOD level 4 011 2.4
BOD level 5 010 2.6
BOD level 6 001 2.8
BOD level 7 000 3.0
V
CC
T
IME-OUT
I
NTERNAL
RESET
V
BOT-
V
BOT+
t
TOUT
t
BOD
RESET TIMEOUT INTERNAL RESET WDT TIMEOUT RESET TIMEOUT \NTERNAL RESET AtmeL
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Table 9-3. BOD Setting Fuse Decoding
9.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
Figure 9-5. External Reset Characteristics
For external reset characterization data consult the device datasheet.
9.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timout period, a watchdog reset will be given. The watchdog reset is active for one to
two 2MHz clock cycles from the 8MHz internal oscillator.
Figure 9-6. Watchdog Reset
For information on configuration and use of the WDT, refer to the “WDT – Watchdog Timer” on page 127.
BODACT[1:0]/ BODPD[1:0] Mode
00 Reserved
01 Sampled
10 Enabled
11 Disabled
CC
tEXT
1-2 2MHz
CC
cycles
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9.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
Figure 9-7. Software Reset
9.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
1-2 2MHz
CC
cycles
SOFTWARE
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9.5 Register Description
9.5.1 STATUS – Status Register
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5 – SRF: Software Reset Flag
This flag is set if a software reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
Bit 4 – PDIRF: Program and Debug Interface Reset Flag
This flag is set if a programming interface reset occurs. The flag will be cleared by a power-on reset or by writing a
one to the bit location.
Bit 3 – WDRF: Watchdog Reset Flag
This flag is set if a watchdog reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
Bit 2 – BORF: Brownout Reset Flag
This flag is set if a brownout reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
Bit 1 – EXTRF: External Reset Flag
This flag is set if an external reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
Bit 0 – PORF: Power On Reset Flag
This flag is set if a power-on reset occurs. Writing a one to the flag will clear the bit location.
9.5.2 CTRL – Control Register
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – SWRST: Software Reset
When this bit is set, a software reset will occur. The bit is cleared when a reset is issued. This bit is protected by
the configuration change protection mechanism. For details, refer to “Configuration Change Protection” on page
13.
9.6 Register Summary
Bit 76543210
+0x00 SRF PDIRF WDRF BORF EXTRF PORF
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value––––––––
Bit 76543210
+0x01 –––––––SWRST
Read/Write RRRRRRRR/W
Initial Value00000000
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 STATUS SRF PDIRF WDRF BORF EXTRF PORF 126
+0x01 CTRL – – – –SWRST126
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10. WDT – Watchdog Timer
10.1 Features
Issues a device reset if the timer is not reset before its timeout period
Asynchronous operation from dedicated oscillator
1kHz output of the 32kHz ultra low power oscillator
11 selectable timeout periods, from 8ms to 8s
Two operation modes:
Normal mode
Window mode
Configuration lock to prevent unwanted changes
10.2 Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
10.3 Normal Mode Operation
In normal mode operation, a single timeout period is set for the WDT. If the WDT is not reset from the application code
before the timeout occurs, then the WDT will issue a system reset. There are 11 possible WDT timeout (TOWDT) periods,
selectable from 8ms to 8s, and the WDT can be reset at any time during the timeout period. A new WDT timeout period
will be started each time the WDT is reset by the WDR instruction. The default timeout period is controlled by fuses.
Normal mode operation is illustrated in Figure 10-1 on page 127.
Figure 10-1. Normal Mode Operation
WDT Count A Time‘y WDT Reset F Early WDT Reset Syslem Reset 5 1o 15 20 25 so 35 .[ms] +70~uwr>+1oww> a s 3 l m Towmw = 8 +6‘osed—H70pen4» AtmeL
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10.4 Window Mode Operation
In window mode operation, the WDT uses two different timeout periods, a "closed" window timeout period (TOWDTW) and
the normal timeout period (TOWDT). The closed window timeout period defines a duration of from 8ms to 8s where the
WDT cannot be reset. If the WDT is reset during this period, the WDT will issue a system reset. The normal WDT timeout
period, which is also 8ms to 8s, defines the duration of the "open" period during which the WDT can (and should) be
reset. The open period will always follow the closed period, and so the total duration of the timeout period is the sum of
the closed window and the open window timeout periods. The default closed window timeout period is controlled by fuses
(both open and closed periods are controlled by fuses). The window mode operation is illustrated in Figure 10-2.
Figure 10-2. Window Mode Operation
10.5 Watchdog Timer Clock
The WDT is clocked from the 1kHz output from the 32kHz ultra low power (ULP) internal oscillator. Due to the ultra low
power design, the oscillator is not very accurate, and so the exact timeout period may vary from device to device. When
designing software which uses the WDT, this device-to-device variation must be kept in mind to ensure that the timeout
periods used are valid for all devices. For more information on ULP oscillator accuracy, consult the device datasheet.
10.6 Configuration Protection and Lock
The WDT is designed with two security mechanisms to avoid unintentional changes to the WDT settings.
The first mechanism is the configuration change protection mechanism, employing a timed write procedure for changing
the WDT control registers. In addition, for the new configuration to be written to the control registers, the register’s
change enable bit must be written at the same time.
The second mechanism locks the configuration by setting the WDT lock fuse. When this fuse is set, the watchdog time
control register cannot be changed; hence, the WDT cannot be disabled from software. After system reset, the WDT will
resume at the configured operation. When the WDT lock fuse is programmed, the window mode timeout period cannot
be changed, but the window mode itself can still be enabled or disabled.
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10.7 Register Description
10.7.1 CTRL – Control Register
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bits 5:2 – PER[3:0]: Timeout Period
These bits determine the watchdog timeout period as a number of 1kHz ULP oscillator cycles. In window mode
operation, these bits define the open window period. The different typical timeout periods are found in Table 10-1.
The initial values of these bits are set by the watchdog timeout period (WDP) fuses, which are loaded at power-on.
In order to change these bits, the CEN bit must be written to 1 at the same time. These bits are protected by the
configuration change protection mechanism. For a detailed description, refer to “Configuration Change Protection”
on page 13.
Table 10-1. Watchdog Timeout Periods
Note: Reserved settings will not give any timeout.
Bit 76543210
+0x00 PER[3:0] ENABLE CEN
Read/Write (unlocked) R R R/W R/W R/W R/W R/W R/W
Read/Write (locked) RRRRRRRR
Initial value (x = fuse) 0 0 X X X X X 0
PER[3:0] Group configuration Typical timeout periods
0000 8CLK 8ms
0001 16CLK 16ms
0010 32CLK 32ms
0011 64CLK 64ms
0100 128CLK 0.128s
0101 256CLK 0.256s
0110 512CLK 0.512s
0111 1KCLK 1.0s
1000 2KCLK 2.0s
1001 4KCLK 4.0s
1010 8KCLK 8.0s
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
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Bit 1 – ENABLE: Enable
This bit enables the WDT. Clearing this bit disables the watchdog timer.
In order to change this bit, the CEN bit in “CTRL – Control Register” on page 129 must be written to one at the
same time. This bit is protected by the configuration change protection mechanism. For a detailed description,
refer to “Configuration Change Protection” on page 13.
Bit 0 – CEN: Change Enable
This bit enables the ability to change the configuration of the “CTRL – Control Register” on page 129. When writing
a new value to this register, this bit must be written to one at the same time for the changes to take effect. This bit
is protected by the configuration change protection mechanism. For a detailed description, refer to “Configuration
Change Protection” on page 13.
10.7.2 WINCTRL – Window Mode Control Register
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5:2 – WPER[3:0]: Window Mode Timeout Period
These bits determine the closed window period as a number of 1kHz ULP oscillator cycles in window mode opera-
tion. The typical different closed window periods are found in Table 10-2. The initial values of these bits are set by
the watchdog window timeout period (WDWP) fuses, and are loaded at power-on. In normal mode these bits are
not in use.
In order to change these bits, the WCEN bit must be written to one at the same time. These bits are protected by
the configuration change protection mechanism. For a detailed description, refer to “Configuration Change Protec-
tion” on page 13.
Table 10-2. Watchdog Closed Window Periods
Bit 76543210
+0x01 WPER[3:0] WEN WCEN
Read/Write (unlocked) R R R/W R/W R/W R/W R/W R/W
Read/Write (locked) RRRRRRR/WR/W
Initial value (x = fuse)00XXXXX0
WPER[3:0] Group configuration Typical closed window periods
0000 8CLK 8ms
0001 16CLK 16ms
0010 32CLK 32ms
0011 64CLK 64ms
0100 128CLK 0.128s
0101 256CLK 0.256s
0110 512CLK 0.512s
0111 1KCLK 1.0s
1000 2KCLK 2.0s
1001 4KCLK 4.0s
1010 8KCLK 8.0s
1011 Reserved
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Note: Reserved settings will not give any timeout for the window.
Bit 1 – WEN: Window Mode Enable
This bit enables the window mode. In order to change this bit, the WCEN bit in “WINCTRL – Window Mode Control
Register” on page 130 must be written to one at the same time. This bit is protected by the configuration change
protection mechanism. For a detailed description, refer to “Configuration Change Protection” on page 13.
Bit 0 – WCEN: Window Mode Change Enable
This bit enables the ability to change the configuration of the “WINCTRL – Window Mode Control Register” on
page 130. When writing a new value to this register, this bit must be written to one at the same time for the
changes to take effect. This bit is protected by the configuration change protection mechanism, but not protected
by the WDT lock fuse.
10.7.3 STATUS – Status Register
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – SYNCBUSY: Synchronization Busy Flag
This flag is set after writing to the CTRL or WINCTRL registers and the data are being synchronized from the sys-
tem clock to the WDT clock domain. This bit is automatically cleared after the synchronization is finished.
Synchronization will take place only when the ENABLE bit for the Watchdog Timer is set.
10.8 Register Summary
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
WPER[3:0] Group configuration Typical closed window periods
Bit 7654321 0
+0x02 ––––––– SYNCBUSY
Read/Write R R RRRRR R
Initial value 0000000 0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL PER[3:0] ENABLE CEN 129
+0x01 WINCTRL WPER[3:0] WEN WCEN 130
+0x02 STATUS – – SYNCBUSY 131
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11. PMIC – Interrupts and Programmable Multilevel Interrupt Controller
11.1 Features
Short and predictable interrupt response time
Separate interrupt configuration and vector address for each interrupt
Programmable multilevel interrupt controller
Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium and high
Selectable, round-robin priority scheme within low-level interrupts
Non-maskable interrupts for critical functions
Interrupt vectors optionally placed in the application section or the boot loader section
11.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
11.3 Operation
Interrupts must be globally enabled for any interrupts to be generated. This is done by setting the global interrupt enable
( I ) bit in the CPU “SREG – Status Register” on page 17. The I bit will not be cleared when an interrupt is acknowledged.
Each interrupt level must also be enabled before interrupts with the corresponding level can be generated.
When an interrupt is enabled and the interrupt condition is present, the PMIC will receive the interrupt request. Based on
the interrupt level and interrupt priority of any ongoing interrupts, the interrupt is either acknowledged or kept pending
until it has priority. When the interrupt request is acknowledged, the program counter is updated to point to the interrupt
vector. The interrupt vector is normally a jump to the interrupt handler; the software routine that handles the interrupt.
After returning from the interrupt handler, program execution continues from where it was before the interrupt occurred.
One instruction is always executed before any pending interrupt is served.
The PMIC status register contains state information that ensures that the PMIC returns to the correct interrupt level when
the RETI (interrupt return) instruction is executed at the end of an interrupt handler. Returning from an interrupt will return
the PMIC to the state it had before entering the interrupt. The status register (SREG) is not saved automatically upon an
interrupt request. The RET (subroutine return) instruction cannot be used when returning from the interrupt handler
routine, as this will not return the PMIC to its correct state.
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Figure 11-1. Interrupt Controller Overview
11.4 Interrupts
All interrupts and the reset vector each have a separate program vector address in the program memory space. The
lowest address in the program memory space is the reset vector. All interrupts are assigned with individual control bits for
enabling and setting the interrupt level, and this is set in the control registers for each peripheral that can generate
interrupts. Details on each interrupt are described in the peripheral where the interrupt is available.
Each interrupt has an interrupt flag associated with it. When the interrupt condition is present, the interrupt flag will be set,
even if the corresponding interrupt is not enabled. For most interrupts, the interrupt flag is automatically cleared when
executing the interrupt vector. Writing a logical one to the interrupt flag will also clear the flag. Some interrupt flags are
not cleared when executing the interrupt vector, and some are cleared automatically when an associated register is
accessed (read or written). This is described for each individual interrupt flag.
If an interrupt condition occurs while another, higher priority interrupt is executing or pending, the interrupt flag will be set
and remembered until the interrupt has priority. If an interrupt condition occurs while the corresponding interrupt is not
enabled, the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by software.
Similarly, if one or more interrupt conditions occur while global interrupts are disabled, the corresponding interrupt flag
will be set and remembered until global interrupts are enabled. All pending interrupts are then executed according to their
order of priority.
Interrupts can be blocked when executing code from a locked section; e.g., when the boot lock bits are programmed.
This feature improves software security. Refer to “Memory Programming” on page 411 for details on lock bit settings.
Interrupts are automatically disabled for up to four CPU clock cycles when the configuration change protection register is
written with the correct signature. Refer to “Configuration Change Protection” on page 13 for more details.
11.4.1 NMI – Non-maskable Interrupts
Which interrupts represent NMI and which represent regular interrupts cannot be selected. Non-maskable interrupts
must be enabled before they can be used. Refer to the device datasheet for NMI present on each device.
An NMI will be executed regardless of the setting of the I bit in the CPU status register, and it will never change the I bit.
No other interrupts can interrupt a NMI handler. If more than one NMI is requested at the same time, priority is static
according to the interrupt vector address, where the lowest address has highest priority.
11.4.2 Interrupt Response Time
The interrupt response time for all the enabled interrupts is three CPU clock cycles, minimum; one cycle to finish the
ongoing instruction and two cycles to store the program counter to the stack. After the program counter is pushed on the
stack, the program vector for the interrupt is executed. The jump to the interrupt handler takes three clock cycles.
If an interrupt occurs during execution of a multicycle instruction, this instruction is completed before the interrupt is
served. See Figure 11-2 on page 134 for more details.
Peripheral 1
Interrupt Controller
INT REQ
INT LEVEL
INT REQ
INT LEVEL CPU INT REQ
CTRL
LEVEL Enable
CPU.SREG
Global
Interrupt
Enable
Priority
decoder
STATUS
INTPRI
INT ACK
INT ACK
Peripheral n
INT LEVEL
INT REQ
INT ACK
CPU
CPU INT ACK
CPU ”RETI”
Sleep
Controller
Wake-up
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Figure 11-2. Interrupt Execution of a Multi-cycle Instruction
If an interrupt occurs when the device is in sleep mode, the interrupt execution response time is increased by five clock
cycles. In addition, the response time is increased by the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four to five clock cycles, depending on the size of the program counter.
During these clock cycles, the program counter is popped from the stack and the stack pointer is incremented.
11.5 Interrupt Level
The interrupt level is independently selected for each interrupt source. For any interrupt request, the PMIC also receives
the interrupt level for the interrupt. The interrupt levels and their corresponding bit values for the interrupt level
configuration of all interrupts are shown in Table 11-1 on page 135.
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Table 11-1. Interrupt Levels
The interrupt level of an interrupt request is compared against the current level and status of the interrupt controller. An
interrupt request of a higher level will interrupt any ongoing interrupt handler from a lower level interrupt. When returning
from the higher level interrupt handler, the execution of the lower level interrupt handler will continue.
11.6 Interrupt Priority
Within each interrupt level, all interrupts have a priority. When several interrupt requests are pending, the order in which
interrupts are acknowledged is decided both by the level and the priority of the interrupt request. Interrupts can be
organized in a static or dynamic (round-robin) priority scheme. High- and medium-level interrupts and the NMI will always
have static priority. For low-level interrupts, static or dynamic priority scheduling can be selected.
11.6.1 Static Priority
Interrupt vectors (IVEC) are located at fixed addresses. For static priority, the interrupt vector address decides the priority
within one interrupt level, where the lowest interrupt vector address has the highest priority. Refer to the device datasheet
for the interrupt vector table with the base address for all modules and peripherals with interrupt capability. Refer to the
interrupt vector summary of each module and peripheral in this manual for a list of interrupts and their corresponding
offset address within the different modules and peripherals.
Figure 11-3. Static Priority
11.6.2 Round-robin Scheduling
To avoid the possible starvation problem for low-level interrupts with static priority, where some interrupts might never be
served, the PMIC offers round-robin scheduling for low-level interrupts. When round-robin scheduling is enabled, the
interrupt vector address for the last acknowledged low-level interrupt will have the lowest priority the next time one or
more interrupts from the low level is requested.
Interrupt level configuration Group configuration Description
00 OFF Interrupt disabled.
01 LO Low-level interrupt
10 MED Medium-level interrupt
11 HI High-level interrupt
IVEC 0
:
:
:
IVEC x
IVEC x+1
:
:
:
IVEC N Lowest Priority
Highest Priority
Lowest Address
Highest Address
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Figure 11-4. Round-robin Scheduling
11.7 Interrupt Vector Locations
Table 11-2 shows reset and Interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings.
If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be
placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors
are in the Boot section or vice versa.
Table 11-2. Reset and Interrupt Vectors Placement
Highest Priority
IV EC 0
:
:
:
IV EC x
IV EC x +1
:
:
:
IV EC N
IV EC 0
:
:
:
IV EC x
IV EC x +1
:
:
:
IV EC N
Highest Priority
Low est Priority
IV EC x +2
IVEC x+1 last acknow ledged
interrupt
Low est Priority
IVEC x last acknow ledged
interrupt
BOOTRST IVSEL Reset address Interrupt vectors start address
1 0 0x0000 0x0002
1 1 0x0000 Boot Reset Address + 0x0002
0 0 Boot Reset Address 0x0002
0 1 Boot Reset Address Boot Reset Address + 0x0002
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11.8 Register Description
11.8.1 STATUS – Status Register
Bit 7 – NMIEX: Non-Maskable Interrupt Executing
This flag is set if a non-maskable interrupt is executing. The flag will be cleared when returning (RETI) from the
interrupt handler.
Bit 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2 – HILVLEX: High-level Interrupt Executing
This flag is set when a high-level interrupt is executing or when the interrupt handler has been interrupted by an
NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
Bit 1 – MEDL