C8051F310/1/2/3/4/5/6/7 Datasheet by Silicon Labs

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Rev. 1.8 10/17 Copyright © 2017 by Silicon Laboratories C8051F31x
8/16 kB ISP Flash MCU Family
C8051F310/1/2/3/4/5/6/7
Analog Peripherals
-10-Bit ADC (C8051F310/1/2/3/6 only)
Up to 200 ksps
Up to 21, 17, or 13 external single-ended or differen-
tial inputs
VREF from external pin or VDD
Built-in temperature sensor
External conversion start input
-Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source (Compara-
tor0)
Low current ( 0.5 µA)
On-Chip Debug
-On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug
(no emulator required)
-Provides breakpoints, single stepping,
inspect/modify memory and registers
-Superior performance to emulation systems using
ICE-Chips, target pods, and sockets
-Complete development kit
Supply Voltage 2.7 to 3.6 V
-Typical operating current: 5 mA at 25 MHz;
11 µA at 32 kHz
-Typical stop mode current: 0.1 µA
-Temperature range: –40 to +85 °C
High Speed 8051 µC Core
-Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-Up to 25 MIPS throughput with 25 MHz clock
-Expanded interrupt handler
Memory
-1280 bytes internal data RAM (1024 + 256)
-
16 kB (C8051F310/1/6/7) or 8 kB (C8051F312/3/4/5)
Flash; In-system programmable in 512-byte sectors
Digital Peripherals
-29/25/21 Port I/O;
All 5 V tolerant with high sink current
-Hardware enhanced UART, SMBus™, and SPI™
serial ports
-Four general purpose 16-bit counter/timers
-16-bit programmable counter array (PCA) with five
capture/compare modules
-Real time clock capability using PCA or timer and
external clock source
Clock Sources
-Internal oscillator: 24.5 MHz with ±2% accuracy
supports crystal-less UART operation
-External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
-Can switch between clock sources on-the-fly; useful
in power saving modes
Packages
-32-pin LQFP (C8051F310/2/4)
-28-pin QFN (C8051F311/3/5)
-24-pin QFN (C8051F316/7)
ANALOG
PERIPHERALS
10-bit
200ksps
ADC
16 kB/8 kB
ISP FLASH 1280 B
SRAM
POR
DEBUG
CIRCUITRY
14
INTERRUPTS
8051 CPU
(25MIPS)
TEMP
SENSOR
DIGITAL I/O
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
A
M
U
X
CROSSBAR
VOLTAGE
COMPARATORS
+
-
WDT
Port 0
+
-
UART
SMBus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 1
Port 2
Port 3
SPI
C8051F310/1/2/3/6 only
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
2 Rev. 1.8
NOTES:
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 3
Table Of Contents
1. System Overview.................................................................................................... 17
1.1. CIP-51™ Microcontroller Core.......................................................................... 27
1.1.1. Fully 8051 Compatible.............................................................................. 27
1.1.2. Improved Throughput............................................................................... 27
1.1.3. Additional Features .................................................................................. 28
1.2. On-Chip Memory............................................................................................... 29
1.3. On-Chip Debug Circuitry................................................................................... 30
1.4. Programmable Digital I/O and Crossbar........................................................... 31
1.5. Serial Ports ....................................................................................................... 32
1.6. Programmable Counter Array........................................................................... 32
1.7. 12-Bit Analog to Digital Converter..................................................................... 33
1.8. Comparators ..................................................................................................... 34
2. Absolute Maximum Ratings .................................................................................. 35
3. Global DC Electrical Characteristics .................................................................... 36
4. Pinout and Package Definitions............................................................................ 39
5. 12-Bit ADC (ADC0, C8051F310/1/2/3/6 only) ........................................................ 51
5.1. Analog Multiplexer ............................................................................................ 51
5.2. Temperature Sensor......................................................................................... 52
5.3. Modes of Operation .......................................................................................... 54
5.3.1. Starting a Conversion............................................................................... 54
5.3.2. Tracking Modes........................................................................................ 55
5.3.3. Settling Time Requirements..................................................................... 56
5.4. Programmable Window Detector...................................................................... 61
5.4.1. Window Detector In Single-Ended Mode ................................................. 63
5.4.2. Window Detector In Differential Mode...................................................... 64
6. Voltage Reference (C8051F310/1/2/3/6 only)........................................................ 67
7. Comparators........................................................................................................... 69
8. CIP-51 Microcontroller .......................................................................................... 79
8.1. Instruction Set................................................................................................... 80
8.1.1. Instruction and CPU Timing ..................................................................... 80
8.1.2. MOVX Instruction and Program Memory ................................................. 81
8.2. Memory Organization........................................................................................ 85
8.2.1. Program Memory...................................................................................... 85
8.2.2. Data Memory............................................................................................ 86
8.2.3. General Purpose Registers...................................................................... 86
8.2.4. Bit Addressable Locations........................................................................ 86
8.2.5. Stack ....................................................................................................... 86
8.2.6. Special Function Registers....................................................................... 87
8.2.7. Register Descriptions ............................................................................... 90
8.3. Interrupt Handler............................................................................................... 93
8.3.1. MCU Interrupt Sources and Vectors ........................................................ 94
8.3.2. External Interrupts.................................................................................... 95
8.3.3. Interrupt Priorities..................................................................................... 95
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8.3.4. Interrupt Latency ...................................................................................... 95
8.3.5. Interrupt Register Descriptions................................................................. 97
8.4. Power Management Modes............................................................................ 102
8.4.1. Idle Mode................................................................................................ 102
8.4.2. Stop Mode.............................................................................................. 103
9. Reset Sources....................................................................................................... 105
9.1. Power-On Reset ............................................................................................. 106
9.2. Power-Fail Reset / VDD Monitor..................................................................... 106
9.3. External Reset ................................................................................................ 107
9.4. Missing Clock Detector Reset......................................................................... 108
9.5. Comparator0 Reset......................................................................................... 108
9.6. PCA Watchdog Timer Reset........................................................................... 108
9.7. Flash Error Reset............................................................................................ 108
9.8. Software Reset ............................................................................................... 108
10.Flash Memory ..................................................................................................... 111
10.1.Programming The Flash Memory................................................................... 111
10.1.1.Flash Lock and Key Functions............................................................... 111
10.1.2.Flash Erase Procedure .......................................................................... 111
10.1.3.Flash Write Procedure ........................................................................... 112
10.2.Non-volatile Data Storage .............................................................................. 112
10.3.Security Options............................................................................................. 113
10.4.Flash Write and Erase Guidelines.................................................................. 115
10.4.1.VDD Maintenance and the VDD Monitor ................................................. 115
10.4.2.PSWE Maintenance............................................................................... 115
10.4.3.System Clock ......................................................................................... 116
11.External RAM........................................................................................................ 119
12.Oscillators............................................................................................................. 121
12.1.Programmable Internal Oscillator................................................................... 121
12.2.External Oscillator Drive Circuit...................................................................... 124
12.3.System Clock Selection.................................................................................. 124
12.4.External Crystal Example ............................................................................... 126
12.5.External RC Example ..................................................................................... 127
12.6.External Capacitor Example........................................................................... 127
13.Port Input/Output ................................................................................................ 129
13.1.Priority Crossbar Decoder .............................................................................. 131
13.2.Port I/O Initialization ....................................................................................... 133
13.3.General Purpose Port I/O............................................................................... 135
14.SMBus ................................................................................................................... 145
14.1.Supporting Documents................................................................................... 146
14.2.SMBus Configuration...................................................................................... 146
14.3.SMBus Operation........................................................................................... 146
14.3.1.Arbitration............................................................................................... 147
14.3.2.Clock Low Extension.............................................................................. 148
14.3.3.SCL Low Timeout................................................................................... 148
14.3.4.SCL High (SMBus Free) Timeout .......................................................... 148
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14.4.Using the SMBus............................................................................................ 149
14.4.1.SMBus Configuration Register............................................................... 150
14.4.2.SMB0CN Control Register ..................................................................... 153
14.4.3.Data Register ......................................................................................... 156
14.5.SMBus Transfer Modes.................................................................................. 157
14.5.1.Master Transmitter Mode....................................................................... 157
14.5.2.Master Receiver Mode........................................................................... 158
14.5.3.Slave Receiver Mode............................................................................. 159
14.5.4.Slave Transmitter Mode......................................................................... 160
14.6.SMBus Status Decoding................................................................................. 161
15.UART0.................................................................................................................... 163
15.1.Enhanced Baud Rate Generation................................................................... 164
15.2.Operational Modes ......................................................................................... 165
15.2.1.8-Bit UART............................................................................................. 165
15.2.2.9-Bit UART............................................................................................. 166
15.3.Multiprocessor Communications .................................................................... 167
16.Enhanced Serial Peripheral Interface (SPI0)...................................................... 173
16.1.Signal Descriptions......................................................................................... 174
16.1.1.Master Out, Slave In (MOSI).................................................................. 174
16.1.2.Master In, Slave Out (MISO).................................................................. 174
16.1.3.Serial Clock (SCK) ................................................................................. 174
16.1.4.Slave Select (NSS) ................................................................................ 174
16.2.SPI0 Master Mode Operation......................................................................... 175
16.3.SPI0 Slave Mode Operation........................................................................... 177
16.4.SPI0 Interrupt Sources................................................................................... 177
16.5.Serial Clock Timing......................................................................................... 178
16.6.SPI Special Function Registers...................................................................... 180
17.Timers ................................................................................................................... 187
17.1.Timer 0 and Timer 1 ....................................................................................... 187
17.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 187
17.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 189
17.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 189
17.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 190
17.2.Timer 2 .......................................................................................................... 195
17.2.1.16-bit Timer with Auto-Reload................................................................ 195
17.2.2.8-bit Timers with Auto-Reload................................................................ 196
17.3.Timer 3 .......................................................................................................... 199
17.3.1.16-bit Timer with Auto-Reload................................................................ 199
17.3.2.8-bit Timers with Auto-Reload................................................................ 200
18.Programmable Counter Array ............................................................................ 203
18.1.PCA Counter/Timer ........................................................................................ 204
18.2.Capture/Compare Modules ............................................................................ 205
18.2.1.Edge-triggered Capture Mode................................................................ 206
18.2.2.Software Timer (Compare) Mode........................................................... 207
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18.2.3.High-Speed Output Mode ...................................................................... 208
18.2.4.Frequency Output Mode ........................................................................ 209
18.2.5.8-Bit Pulse Width Modulator Mode......................................................... 210
18.2.6.16-Bit Pulse Width Modulator Mode....................................................... 211
18.3.Watchdog Timer Mode ................................................................................... 212
18.3.1.Watchdog Timer Operation.................................................................... 212
18.3.2.Watchdog Timer Usage ......................................................................... 213
18.4.Register Descriptions for PCA........................................................................ 215
19.Revision Specific Behavior ................................................................................. 221
19.1.Revision Identification..................................................................................... 221
19.2.Reset Behavior............................................................................................... 221
19.2.1.Weak Pullups on GPIO Pins.................................................................. 221
19.2.2.VDD Monitor and the RST Pin ............................................................... 221
19.3.PCA Counter .................................................................................................. 222
20.C2 Interface........................................................................................................... 223
20.1.C2 Interface Registers.................................................................................... 223
20.2.C2 Pin Sharing ............................................................................................... 225
Document Change List............................................................................................. 226
Contact Information.................................................................................................. 228
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Rev. 1.8 7
List of Figures
1. System Overview
Figure 1.1. C8051F310 Block Diagram.................................................................... 19
Figure 1.2. C8051F311 Block Diagram.................................................................... 20
Figure 1.3. C8051F312 Block Diagram.................................................................... 21
Figure 1.4. C8051F313 Block Diagram.................................................................... 22
Figure 1.5. C8051F314 Block Diagram.................................................................... 23
Figure 1.6. C8051F315 Block Diagram.................................................................... 24
Figure 1.7. C8051F316 Block Diagram.................................................................... 25
Figure 1.8. C8051F317 Block Diagram.................................................................... 26
Figure 1.9. Comparison of Peak MCU Execution Speeds ....................................... 27
Figure 1.10. On-Chip Clock and Reset..................................................................... 28
Figure 1.11. On-Board Memory Map........................................................................ 29
Figure 1.12. Development/In-System Debug Diagram............................................. 30
Figure 1.13. Digital Crossbar Diagram ..................................................................... 31
Figure 1.14. PCA Block Diagram.............................................................................. 32
Figure 1.15. 12-Bit ADC Block Diagram................................................................... 33
Figure 1.16. Comparator0 Block Diagram................................................................ 34
2. Absolute Maximum Ratings
3. Global DC Electrical Characteristics
4. Pinout and Package Definitions
Figure 4.1. LQFP-32 Pinout Diagram (Top View) .................................................... 41
Figure 4.2. LQFP-32 Package Diagram................................................................... 42
Figure 4.3. Typical LQFP-32 Landing Diagram........................................................ 43
Figure 4.4. QFN-28 Pinout Diagram (Top View) ...................................................... 44
Figure 4.5. QFN-28 Package Drawing ..................................................................... 45
Figure 4.6. Typical QFN-28 Landing Diagram.......................................................... 46
Figure 4.7. QFN-24 Pinout Diagram (Top View) ...................................................... 47
Figure 4.8. QFN-24 Package Drawing ..................................................................... 48
Figure 4.9. Typical QFN-24 Landing Diagram.......................................................... 49
Figure 4.10. QFN-24 Solder Paste Recommendation.............................................. 50
5. 12-Bit ADC (ADC0, C8051F310/1/2/3/6 only)
Figure 5.1. ADC0 Functional Block Diagram............................................................ 51
Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 52
Figure 5.3. Temperature Sensor Error with 1-Point Calibration ............................... 53
Figure 5.4. 12-Bit ADC Track and Conversion Example Timing.............................. 55
Figure 5.5. ADC0 Equivalent Input Circuits.............................................................. 56
Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data... 63
Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 63
Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data ....... 64
Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data.......... 64
6. Voltage Reference (C8051F310/1/2/3/6 only)
Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 67
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8 Rev. 1.8
7. Comparators
Figure 7.1. Comparator0 Functional Block Diagram ................................................ 69
Figure 7.2. Comparator1 Functional Block Diagram ................................................ 70
Figure 7.3. Comparator Hysteresis Plot ................................................................... 71
8. CIP-51 Microcontroller
Figure 8.1. CIP-51 Block Diagram............................................................................ 79
Figure 8.2. Memory Map .......................................................................................... 85
9. Reset Sources
Figure 9.1. Reset Sources...................................................................................... 105
Figure 9.2. Power-On and VDD Monitor Reset Timing .......................................... 106
10.Flash Memory
Figure 10.1. Flash Program Memory Map.............................................................. 113
11.External RAM
12.Oscillators
Figure 12.1. Oscillator Diagram.............................................................................. 121
Figure 12.2. 32.768 kHz External Crystal Example................................................ 126
13.Port Input/Output
Figure 13.1. Port I/O Functional Block Diagram..................................................... 129
Figure 13.2. Port I/O Cell Block Diagram ............................................................... 130
Figure 13.3. Crossbar Priority Decoder with No Pins Skipped............................... 131
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 132
14.SMBus
Figure 14.1. SMBus Block Diagram ....................................................................... 145
Figure 14.2. Typical SMBus Configuration............................................................. 146
Figure 14.3. SMBus Transaction............................................................................ 147
Figure 14.4. Typical SMBus SCL Generation......................................................... 151
Figure 14.5. Typical Master Transmitter Sequence................................................ 157
Figure 14.6. Typical Master Receiver Sequence.................................................... 158
Figure 14.7. Typical Slave Receiver Sequence...................................................... 159
Figure 14.8. Typical Slave Transmitter Sequence.................................................. 160
15.UART0
Figure 15.1. UART0 Block Diagram ....................................................................... 163
Figure 15.2. UART0 Baud Rate Logic.................................................................... 164
Figure 15.3. UART Interconnect Diagram .............................................................. 165
Figure 15.4. 8-Bit UART Timing Diagram............................................................... 165
Figure 15.5. 9-Bit UART Timing Diagram............................................................... 166
Figure 15.6. UART Multi-Processor Mode Interconnect Diagram .......................... 167
16.Enhanced Serial Peripheral Interface (SPI0)
Figure 16.1. SPI Block Diagram ............................................................................. 173
Figure 16.2. Multiple-Master Mode Connection Diagram....................................... 176
Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram............. 176
Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram............. 176
Figure 16.5. Master Mode Data/Clock Timing........................................................ 178
Figure 16.6. Slave Mode Data/Clock Timing (CKPHA = 0).................................... 179
Figure 16.7. Slave Mode Data/Clock Timing (CKPHA = 1).................................... 179
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Rev. 1.8 9
Figure 16.8. SPI Master Timing (CKPHA = 0)........................................................ 183
Figure 16.9. SPI Master Timing (CKPHA = 1)........................................................ 183
Figure 16.10. SPI Slave Timing (CKPHA = 0)........................................................ 184
Figure 16.11. SPI Slave Timing (CKPHA = 1)........................................................ 184
17.Timers
Figure 17.1. T0 Mode 0 Block Diagram.................................................................. 188
Figure 17.2. T0 Mode 2 Block Diagram.................................................................. 189
Figure 17.3. T0 Mode 3 Block Diagram.................................................................. 190
Figure 17.4. Timer 2 16-Bit Mode Block Diagram .................................................. 195
Figure 17.5. Timer 2 8-Bit Mode Block Diagram .................................................... 196
Figure 17.6. Timer 3 16-Bit Mode Block Diagram .................................................. 199
Figure 17.7. Timer 3 8-Bit Mode Block Diagram .................................................... 200
18.Programmable Counter Array
Figure 18.1. PCA Block Diagram............................................................................ 203
Figure 18.2. PCA Counter/Timer Block Diagram.................................................... 204
Figure 18.3. PCA Interrupt Block Diagram ............................................................. 205
Figure 18.4. PCA Capture Mode Diagram.............................................................. 206
Figure 18.5. PCA Software Timer Mode Diagram.................................................. 207
Figure 18.6. PCA High Speed Output Mode Diagram............................................ 208
Figure 18.7. PCA Frequency Output Mode ............................................................ 209
Figure 18.8. PCA 8-Bit PWM Mode Diagram ......................................................... 210
Figure 18.9. PCA 16-Bit PWM Mode...................................................................... 211
Figure 18.10. PCA Module 4 with Watchdog Timer Enabled ................................. 212
19.Revision Specific Behavior
Figure 19.1. Reading Package Marking ................................................................. 221
20.C2 Interface
Figure 20.1. Typical C2 Pin Sharing....................................................................... 225
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
10 Rev. 1.8
NOTES:
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C8051F310/1/2/3/4/5/6/7
Rev. 1.8 11
List of Tables
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 18
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings* .................................................................. 35
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics ....................................................... 36
Table 3.2. Electrical Characteristics Quick Reference ............................................ 38
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F31x .......................................................... 39
Table 4.2. LQFP-32 Package Dimensions .............................................................. 42
Table 4.3. LQFP-32 Landing Pattern Dimensions ................................................... 43
Table 4.4. QFN-28 Package Dimensions ................................................................ 45
Table 4.5. QFN-28 Landing Pattern Dimensions ..................................................... 46
Table 4.6. QFN-24 Package Dimensions ................................................................ 48
5. 12-Bit ADC (ADC0, C8051F310/1/2/3/6 only)
Table 5.1. ADC0 Electrical Characteristics .............................................................. 65
6. Voltage Reference (C8051F310/1/2/3/6 only)
Table 6.1. External Voltage Reference Circuit Electrical Characteristics ................ 68
7. Comparators
Table 7.1. Comparator Electrical Characteristics .................................................... 78
8. CIP-51 Microcontroller
Table 8.1. CIP-51 Instruction Set Summary ............................................................ 81
Table 8.2. Special Function Register (SFR) Memory Map ...................................... 87
Table 8.3. Special Function Registers ..................................................................... 88
Table 8.4. Interrupt Summary .................................................................................. 96
9. Reset Sources
Table 9.1. Reset Electrical Characteristics ............................................................ 110
10.Flash Memory
Table 10.1. Flash Electrical Characteristics .......................................................... 112
Table 10.2. Flash Security Summary .................................................................... 114
11.External RAM
12.Oscillators
Table 12.1. Internal Oscillator Electrical Characteristics ....................................... 123
13.Port Input/Output
Table 13.1. Port I/O DC Electrical Characteristics ................................................ 143
14.SMBus
Table 14.1. SMBus Clock Source Selection .......................................................... 150
Table 14.2. Minimum SDA Setup and Hold Times ................................................ 151
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Table 14.3. Sources for Hardware Changes to SMB0CN ..................................... 155
Table 14.4. SMBus Status Decoding ..................................................................... 161
15.UART0
Table 15.1. Timer Settings for Standard Baud Rates
Using the Internal Oscillator ............................................................... 170
Table 15.2. Timer Settings for Standard Baud Rates
Using an External 25 MHz Oscillator .................................................. 170
Table 15.3. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 171
Table 15.4. Timer Settings for Standard Baud Rates
Using an External 18.432 MHz Oscillator ........................................... 171
Table 15.5. Timer Settings for Standard Baud Rates
Using an External 11.0592 MHz Oscillator ......................................... 172
Table 15.6. Timer Settings for Standard Baud Rates
Using an External 3.6864 MHz Oscillator ........................................... 172
16.Enhanced Serial Peripheral Interface (SPI0)
Table 16.1. SPI Slave Timing Parameters ............................................................ 185
17.Timers
18.Programmable Counter Array
Table 18.1. PCA Timebase Input Options ............................................................. 204
Table 18.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 205
Table 18.3. Watchdog Timer Timeout Intervals1 ..................................................................214
19.Revision Specific Behavior
20.C2 Interface
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Rev. 1.8 13
List of Registers
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 57
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 58
SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 61
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 61
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 62
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . . 62
SFR Definition 6.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 73
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 74
SFR Definition 7.4. CPT1CN: Comparator1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection . . . . . . . . . . . . . . . . . . . . 76
SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection . . . . . . . . . . . . . . . . . . . . 77
SFR Definition 8.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SFR Definition 8.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 8.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 8.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 8.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 8.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 8.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SFR Definition 8.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 8.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 99
SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . 100
SFR Definition 8.11. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 101
SFR Definition 8.12. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SFR Definition 9.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 9.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 10.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 116
SFR Definition 10.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SFR Definition 10.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SFR Definition 11.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 119
SFR Definition 12.1. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . 122
SFR Definition 12.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 122
SFR Definition 12.3. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SFR Definition 12.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 125
SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 134
SFR Definition 13.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 135
SFR Definition 13.3. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SFR Definition 13.4. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
14 Rev. 1.8
SFR Definition 13.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 137
SFR Definition 13.6. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SFR Definition 13.7. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SFR Definition 13.8. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SFR Definition 13.9. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 139
SFR Definition 13.10. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SFR Definition 13.11. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SFR Definition 13.12. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SFR Definition 13.13. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 141
SFR Definition 13.14. P2SKIP: Port2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SFR Definition 13.15. P3: Port3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SFR Definition 13.16. P3MDIN: Port3 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SFR Definition 13.17. P3MDOUT: Port3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 143
SFR Definition 14.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 152
SFR Definition 14.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 14.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 15.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 168
SFR Definition 15.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 169
SFR Definition 16.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 180
SFR Definition 16.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
SFR Definition 16.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
SFR Definition 17.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
SFR Definition 17.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
SFR Definition 17.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
SFR Definition 17.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
SFR Definition 17.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
SFR Definition 17.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
SFR Definition 17.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
SFR Definition 17.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
SFR Definition 17.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 198
SFR Definition 17.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 198
SFR Definition 17.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
SFR Definition 17.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
SFR Definition 17.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
SFR Definition 17.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 202
SFR Definition 17.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 202
SFR Definition 17.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
SFR Definition 17.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
SFR Definition 18.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
SFR Definition 18.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 18.3. PCA0CPMn: PCA Capture/Compare Mode Registers . . . . . . . 217
SFR Definition 18.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 218
SFR Definition 18.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 218
SFR Definition 18.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 218
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 15
SFR Definition 18.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 219
C2 Register Definition 20.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
C2 Register Definition 20.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 223
C2 Register Definition 20.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 224
C2 Register Definition 20.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 224
C2 Register Definition 20.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 224
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
16 Rev. 1.8
NOTES:
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 17
1. System Overview
C8051F31x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are
listed below. Refer to Table 1.1 for specific product feature selection.
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 12-bit 200 ksps 25-channel single-ended/differential ADC with analog multiplexer
(C8051F310/1/2/3/6)
Precision programmable 25 MHz internal oscillator
16k kB (C8051F310/1/6/7) or 8 kB (C8051F312/3/4/5) of on-chip Flash memory
1280 bytes of on-chip RAM
SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, VDD Monitor, and Temperature Sensor
On-chip Voltage Comparators (2)
29/25/21 Port I/O (5 V tolerant)
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the C8051F31x devices
are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-cir-
cuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User soft-
ware has complete control of all peripherals, and may individually shut down any or all peripherals for
power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system programming
and debugging without occupying package pins.
Each device is specified for 2.7-to-3.6 V operation over the industrial temperature range (–45 to +85 °C).
The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F31x are available in 32-pin
LQFP, 28-pin QFN, and 24-pin QFN packages. See Table 1.1 for ordering part numbers. Note: QFN pack-
ages are also referred to as MLP or MLF packages.
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
18 Rev. 1.8
Table 1.1. Product Selection Guide
Ordering Part Number
MIPS (Peak)
Flash Memory
RAM
Calibrated Internal 24.5 MHz Oscillator
SMBus/I2C
Enhanced SPI
UART
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
10-bit 200 ksps ADC
Temperature Sensor
Analog Comparators
Lead-free (RoHS Compliant)
Package
C8051F310 25 16 1280 29   2 - LQFP-32
C8051F310-GQ 25 16 1280 29   2LQFP-32
C8051F311 25 16 1280 25   2 - QFN-28
C8051F311-GM 25 16 1280 25   2QFN-28
C8051F312 25 81280 29   2 - LQFP-32
C8051F312-GQ 25 81280 29   2LQFP-32
C8051F313 25 81280 25   2 - QFN-28
C8051F313-GM 25 81280 25   2QFN-28
C8051F314 25 81280 29 - - 2 - LQFP-32
C8051F314-GQ 25 81280 29 - - 2 LQFP-32
C8051F315 25 81280 25 - - 2 - QFN-28
C8051F315-GM 25 81280 25 - - 2 QFN-28
C8051F316-GM 25 16 1280 21   2QFN-24
C8051F317-GM 25 16 1280 21 - - 2 QFN-24
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 19
Figure 1.1. C8051F310 Block Diagram
UART
16kbyte
FLASH
256 byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Reset
/RST/C2CK
External
Oscillator
Circuit
Debug HW
Brown-
Out
Analog/Digital
Power
P
0
D
r
v
1K byte
SRAM
XTAL1
XTAL2
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
SPI
VDD
GND
C
R
O
S
S
B
A
R
P
1
D
r
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 0
Latch
SMBus
Timer
0,1,2,3 /
RTC
Port 1
Latch
2%
Internal
Oscillator
System Clock
P
2
D
r
v
P
3
D
r
v
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
P3.1
P3.2
P3.3
P3.4
10-bit
200ksps
ADC
A
M
U
X
AIN0-AIN20
VREF
VDD
CP1
+
-
Temp
VDD
CP0
+
-
C2D
Port 2
Latch
Port 3
Latch
PCA/
WDT
PM“ u ‘ rrL, 255 byte , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
20 Rev. 1.8
Figure 1.2. C8051F311 Block Diagram
UART
16kbyte
FLASH
256 byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Reset
/RST/C2CK
External
Oscillator
Circuit
Debug HW
Brown-
Out
Analog/Digital
Power
P
0
D
r
v
1K byte
SRAM
XTAL1
XTAL2
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
SPI
VDD
GND
C
R
O
S
S
B
A
R
P
1
D
r
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 0
Latch
SMBus
Timer
0,1,2,3 /
RTC
Port 1
Latch
2%
Internal
Oscillator
System Clock
P
2
D
r
v
P
3
D
r
v
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
10-bit
200ksps
ADC
A
M
U
X
AIN0-AIN20
VREF
VDD
CP1
+
-
Temp
VDD
CP0
+
-
C2D
Port 2
Latch
Port 3
Latch
PCA/
WDT
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 21
Figure 1.3. C8051F312 Block Diagram
UART
8 kB
FLASH
256 byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Reset
/RST/C2CK
External
Oscillator
Circuit
Debug HW
Brown-
Out
Analog/Digital
Power P
0
D
r
v
1K byte
SRAM
XTAL1
XTAL2
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
SPI
VDD
GND
C
R
O
S
S
B
A
R
P
1
D
r
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 0
Latch
SMBus
Timer
0,1,2,3 /
RTC
Port 1
Latch
2%
Internal
Oscillator
System Clock
P
2
D
r
v
P
3
D
r
v
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
P3.1
P3.2
P3.3
P3.4
10-bit
200ksps
ADC
A
M
U
X
AIN0-AIN20
VREF
VDD
CP1 +
-
Temp
VDD
CP0 +
-
C2D
Port 2
Latch
Port 3
Latch
PCA/
WDT
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
22 Rev. 1.8
Figure 1.4. C8051F313 Block Diagram
UART
8 kB
FLASH
256 byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Reset
/RST/C2CK
External
Oscillator
Circuit
Debug HW
Brown-
Out
Analog/Digital
Power P
0
D
r
v
1K byte
SRAM
XTAL1
XTAL2
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
SPI
VDD
GND
C
R
O
S
S
B
A
R
P
1
D
r
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 0
Latch
SMBus
Timer
0,1,2,3 /
RTC
Port 1
Latch
2%
Internal
Oscillator
System Clock
P
2
D
r
v
P
3
D
r
v
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
10-bit
200ksps
ADC
A
M
U
X
AIN0-AIN20
VREF
VDD
CP1 +
-
Temp
VDD
CP0 +
-
C2D
Port 2
Latch
Port 3
Latch
PCA/
WDT
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 23
Figure 1.5. C8051F314 Block Diagram
UART
8 kB
FLASH
256 byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Reset
/RST/C2CK
External
Oscillator
Circuit
Debug HW
Brown-
Out
Analog/Digital
Power P
0
D
r
v
1K byte
SRAM
XTAL1
XTAL2
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
SPI
VDD
GND
C
R
O
S
S
B
A
R
P
1
D
r
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 0
Latch
SMBus
Timer
0,1,2,3 /
RTC
Port 1
Latch
2%
Internal
Oscillator
System Clock
P
2
D
r
v
P
3
D
r
v
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
P3.1
P3.2
P3.3
P3.4
CP1 +
-
CP0 +
-
C2D
Port 2
Latch
Port 3
Latch
PCA/
WDT
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
24 Rev. 1.8
Figure 1.6. C8051F315 Block Diagram
UART
8 kB
FLASH
256 byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Reset
/RST/C2CK
External
Oscillator
Circuit
Debug HW
Brown-
Out
Analog/Digital
Power P
0
D
r
v
1K byte
SRAM
XTAL1
XTAL2
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
SPI
VDD
GND
C
R
O
S
S
B
A
R
P
1
D
r
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 0
Latch
SMBus
Timer
0,1,2,3 /
RTC
Port 1
Latch
2%
Internal
Oscillator
System Clock
P
2
D
r
v
P
3
D
r
v
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
CP1 +
-
CP0 +
-
C2D
Port 2
Latch
Port 3
Latch
PCA/
WDT
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 25
Figure 1.7. C8051F316 Block Diagram
UART
16 kB
FLASH
256 byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Reset
/RST/C2CK
External
Oscillator
Circuit
Debug HW
Brown-
Out
Analog/Digital
Power P
0
D
r
v
1 kB
SRAM
XTAL1
XTAL2
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
SPI
VDD
GND
C
R
O
S
S
B
A
R
P
1
D
r
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
Port 0
Latch
SMBus
Timer
0,1,2,3 /
RTC
Port 1
Latch
2%
Internal
Oscillator
System Clock
P
2
D
r
v
P
3
D
r
v
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P3.0/C2D
10-bit
200 ksps
ADC
A
M
U
X
AIN0–AIN20
VREF
VDD
CP1 +
-
Temp
VDD
CP0 +
-
C2D
Port 2
Latch
Port 3
Latch
PCA/
WDT
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
26 Rev. 1.8
Figure 1.8. C8051F317 Block Diagram
UART
16 kB
FLASH
256 byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Reset
/RST/C2CK
External
Oscillator
Circuit
Debug HW
Brown-
Out
Analog/Digital
Power P
0
D
r
v
1 kB
SRAM
XTAL1
XTAL2
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
SPI
VDD
GND
C
R
O
S
S
B
A
R
P
1
D
r
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
Port 0
Latch
SMBus
Timer
0,1,2,3 /
RTC
Port 1
Latch
2%
Internal
Oscillator
System Clock
P
2
D
r
v
P
3
D
r
v
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P3.0/C2D
CP1 +
-
CP0 +
-
C2D
Port 2
Latch
Port 3
Latch
PCA/
WDT
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 27
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F31x family utilizes Silicon Laboratories' proprietary CIP-51 microcontroller core. The CIP-51 is
fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be
used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, includ-
ing four 16-bit counter/timers, a full-duplex UART with extended baud rate configuration, an enhanced SPI
port, 1280 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and 29/25/21
I/O pins.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core exe-
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.9
shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum sys-
tem clocks.
Figure 1.9. Comparison of Peak MCU Execution Speeds
Clocks to Execute 1 2 2/3 33/4 44/5 5 8
Number of Instructions 26 50 514 73121
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
28 Rev. 1.8
1.1.3. Additional Features
The C8051F31x SoC family includes several key enhancements to the CIP-51 core and peripherals to
improve performance and ease of use in end applications.
The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as opposed to 7 for the stan-
dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below VRST as given in Table 9.1 on page 110), a Watchdog Timer, a
Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external
reset pin, and an errant Flash read/write protection circuit. Each reset source except for the POR, Reset
Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently enabled
in software after a power-on reset during MCU initialization.
The internal oscillator is factory calibrated to 24.5 MHz ±2%. An external oscillator drive circuit is also
included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate
the system clock. If desired, the system clock source may be switched on-the-fly between the internal and
external oscillator circuits. An external oscillator can be extremely useful in low power applications, allow-
ing the MCU to run from a slow (power saving) external crystal source, while periodically switching to the
fast internal oscillator as needed.
Figure 1.10. On-Chip Clock and Reset
PCA
WDT
Missing
Clock
Detector
(one-
shot) (Software Reset)
System Reset
Reset
Funnel
Px.x
Px.x
EN
SWRSF
Internal
Oscillator System
Clock
CIP-51
Microcontroller
Core
Extended Interrupt
Handler
Clock Select
EN
WDT
Enable
MCD
Enable
XTAL1
XTAL2
External
Oscillator
Drive
Errant
FLASH
Operation
/RST
(wired-OR)
Power On
Reset
'0'
+
-
Comparator 0
C0RSEF
VDD
+
-
Supply
Monitor
Enable
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 29
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 8 or 16k kB of Flash. This memory may be reprogrammed in-system in 512
byte sectors, and requires no special off-chip programming voltage. See Figure 1.11 for the MCU system
memory map.
Figure 1.11. On-Board Memory Map
PROGRAM/DATA MEMORY
(Flash)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF Special Function
Register's
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
XRAM - 1024 Bytes
(accessable using MOVX
instruction)
0x0000
0x03FF
Same 1024 bytes as from
0x0000 to 0x03FF, wrapped
on 1 kB boundaries
0x0400
0xFFFF
16 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x3E00
0x3DFF
8 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x2000
0x1FFF
C8051F310/1/6/7
C8051F312/3/4/5
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
30 Rev. 1.8
1.3. On-Chip Debug Circuitry
The C8051F31x devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intru-
sive, full speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, break-
points, and single stepping. No additional target RAM, program memory, timers, or communications chan-
nels are required. All the digital and analog peripherals are functional and work correctly while debugging.
All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single
stepping, or at a breakpoint in order to keep them synchronized.
The C8051F310DK development kit provides all the hardware and software necessary to develop applica-
tion code and perform in-circuit debugging with the C8051F31x MCUs. The kit includes software with a
developer's studio and debugger, an integrated 8051 assembler, a debug adapter, a target application
board with the associated MCU installed, and the required cables and wall-mount power supply.
The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to
standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to
be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the
precision analog peripherals.
Figure 1.12. Development/In-System Debug Diagram
TARGET PCB
Debug
Adapter
VDD GND
C2 (x2), VDD, GND
Windows 98SE or later
Silicon Laboratories Integrated
Development Environment
C8051F31x
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 31
1.4. Programmable Digital I/O and Crossbar
C8051F310/2/4 devices include 29 I/O pins (three byte-wide Ports and one 5-bit-wide Port);
C8051F311/3/5 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F316/7
devices include 21 I/O pins (one byte-wide Port, two 6-bit-wide Ports and one 1-bit-wide Port). The
C8051F31x Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be config-
ured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for
push-pull or open-drain output. The “weak pullups” that are fixed on typical 8051 devices may be globally
disabled, providing power savings capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.13).
On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the
controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This
allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the
particular application.
Figure 1.13. Digital Crossbar Diagram
XBR0, XBR1,
PnSKIP Registers
Digital
Crossbar
Priority
Decoder
2
P0.0
P0.7
PnMDOUT,
PnMDIN Registers
UART
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1 2
6
PCA
CP1
Outputs 2
4
SPI
CP0
Outputs 2
P1.0
P1.7
P2.0
P2.7
P3.0
P3.4
(Port Latches)
P0 (P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.3)
(P2.4-P2.7)
8
8
4
4
P1
P2
Notes:
1. P3.1–P3.4 only available on the
C8051F310/2/4.
2. P1.6, P1.7, P2.6, P2.7 only
available on the C8051F310/1/2/3/4/5
(P3.0-P3.4)
5
P3
5
P2
I/O
Cells
P3
I/O
Cells
P1
I/O
Cells
P0
I/O
Cells
8
8
84
4
SSSSSSSSSSS
C8051F310/1/2/3/4/5/6/7
32 Rev. 1.8
1.5. Serial Ports
The C8051F31x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate
configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware
and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.6. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur-
pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with five programma-
ble capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or
the external oscillator clock source divided by 8. The external clock source selection is useful for real-time
clock functionality, where the PCA is clocked by an external source while the internal oscillator drives the
system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
Figure 1.14. PCA Block Diagram
Capture/Compare
Module 1
Capture/Compare
Module 0 Capture/Compare
Module 2 Capture/Compare
Module 3 Capture/Compare
Module 4 / WDT
CEX1
ECI
Crossbar
CEX2
CEX3
CEX4
CEX0
Port I/O
16-Bit Counter/Timer
PCA
CLOCK
MUX
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
44M P2 7 Fax» , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 33
1.7. 12-Bit Analog to Digital Converter
The C8051F310/1/2/3/6 devices include an on-chip 12-bit SAR ADC with a 25-channel differential input
multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 12-bit accuracy with an INL of
±1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and nega-
tive ADC inputs. Ports1-3 are available as an ADC inputs; additionally, the on-chip Temperature Sensor
output and the power supply voltage (VDD) are available as ADC inputs. User firmware may shut down the
ADC to save power.
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal. This flexibility allows the start of conversion to be triggered by software
events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated
by a status bit and an interrupt (if enabled). The resulting 12-bit data word is latched into the ADC data
SFRs upon completion of a conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in back-
ground mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Figure 1.15. 12-Bit ADC Block Diagram
10-Bit
SAR
ADC
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
(+)
(-)
Configuration, Control, and Data Registers
23-to-1
AMUX
Temp
Sensor
23-to-1
AMUX
VDD
P1.0
P1.7
P2.0
P2.7
GND
P1.0
P1.7
P2.0
P2.7
P3.0
P3.4
P3.0
P3.4
P3.1-3.4
available on
C8051F310/2
P3.1-3.4
available on
C8051F310/2
Analog Multiplexer
Timer 0 Overflow
Timer 2 Overflow
Start
Conversion
000 AD0BUSY (W)
001
010
011
100
101
16
Window Compare
Logic
Window
Compare
Interrupt
ADC Data
Registers
End of
Conversion
Interrupt
P1.6, P1.7 available on
C8051F310/1/2/3/4/5
P2.6, P2.7 available on
C8051F310/1/2/3/4/5
P1.6, P1.7 available on
C8051F310/1/2/3/4/5
P2.6, P2.7 available on
C8051F310/1/2/3/4/5
VREF
SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
34 Rev. 1.8
1.8. Comparators
C8051F31x devices include two on-chip voltage comparators that are enabled/disabled and configured via
user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator
outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output.
Comparator response time is programmable, allowing the user to select between high-speed and low-
power modes. Positive and negative hysteresis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-
rupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Figure 1.16 shows he Comparator0 block diagram.
Figure 1.16. Comparator0 Block Diagram
VDD
CPT0CN
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
P1.0
P1.4
P2.0
P2.4
CP0 -
P1.1
P1.5
P2.1
P2.5
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CPT0MX
CMX0N1
CMX0N0
CMX0P1
CMX0P0
CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0
CP0A
CP0
Rising-edge CP0
Falling-edge
CP0
Interrupt
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 35
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 125 °C
Storage Temperature –65 150 °C
Voltage on any Port I/O Pin or RST with
respect to GND –0.3 — 5.8 V
Voltage on VDD with respect to GND –0.3 4.2 V
Maximum Total current through VDD and
GND
——500mA
Maximum output current sunk by RST or any
Port pin ——100mA
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the devices at those or any other condi-
tions above those indicated in the operation listings of this specification is not implied. Exposure to maxi-
mum rating conditions for extended periods may affect device reliability.
IA IA m m , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
36 Rev. 1.8
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
–40°C to +85°C, 25 MHz System Clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Digital Supply Voltage VRST13.0 3.6 V
Digital Supply RAM Data Retention
Voltage —1.5— V
Specified Operating Temperature
Range –40 — +85 °C
SYSCLK (system clock frequency) 02—25MHz
Tsysl (SYSCLK low time) 18 ns
Tsysh (SYSCLK high time) 18 — ns
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
IDD (Note 3) VDD = 3.0 V, F = 25 MHz 7.8 8.6 mA
VDD = 3.0 V, F = 1 MHz 0.38 mA
VDD = 3.0 V, F = 80 kHz 31 µA
VDD = 3.6 V, F = 25 MHz 10.7 12.1 mA
IDD Supply Sensitivity (Note 3,
Note 4)
F = 25 MHz 67 %/V
F = 1 MHz 62 %/V
IDD Frequency Sensitivity (Note 3,
Note 5)
VDD = 3.0 V, F < 15 MHz, T = 25 ºC 0.39 mA/MHz
VDD = 3.0 V, F > 15 MHz, T = 25 ºC 0.21 mA/MHz
VDD = 3.6 V, F < 15 MHz, T = 25 ºC 0.55 mA/MHz
VDD = 3.6 V, F > 15 MHz, T = 25 ºC 0.27 mA/MHz
Notes:
1. Given in Table 9.1 on page 110.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Based on device characterization data, not production tested.
4. Active and Inactive IDD at voltages and frequencies other than those specified can be calculated
using the IDD Supply Sensitivity. For example, if the VDD is 3.3 V instead of 3.0 V at 25 MHz: IDD =
7.8 mA typical at 3.0 V and f = 25 MHz. From this, IDD = 7.8 mA + 0.67 x (3.3 V – 3.0 V) = 8 mA at
3.3 V and f = 25 MHz.
5. IDD can be estimated for frequencies < 15 MHz by multiplying the frequency of interest by the fre-
quency sensitivity number for that range. When using these numbers to estimate IDD for > 15 MHz,
the estimate should be the current at 25 MHz minus the difference in current indicated by the fre-
quency sensitivity number. For example:
VDD = 3.0 V; F = 20 MHz, IDD = 7.8 mA – (25 MHz – 20 MHz) x 0.21 mA/MHz = 6.75 mA.
6. Idle IDD can be estimated for frequencies < 1 MHz by multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for > 1
MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the
frequency sensitivity number. For example:
VDD = 3.0 V; F = 5 MHz, Idle IDD = 4.8 mA – (25 MHz – 5 MHz) x 0.15 mA/MHz = 1.8 mA.
\A \A m m , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 37
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
IDD (Note 3) VDD = 3.0 V, F = 25 MHz —3.84.3mA
VDD = 3.0 V, F = 1 MHz —0.20— mA
VDD = 3.0 V, F = 80 kHz —16— µA
VDD = 3.6 V, F = 25 MHz —4.85.3mA
IDD Supply Sensitivity (Note 3,
Note 4) F = 25 MHz —44—%/V
F = 1 MHz —56—%/V
IDD Frequency Sensitivity (Note 3,
Note 6) VDD = 3.0 V, F < 1 MHz, T = 25 °C 0.21 — mA/MHz
VDD = 3.0 V, F > 1 MHz, T = 25 °C 0.15 — mA/MHz
VDD = 3.6 V, F < 1 MHz, T = 25 °C 0.28 — mA/MHz
VDD = 3.6 V, F > 1 MHz, T = 25 °C 0.19 mA/MHz
Digital Supply Current
(Stop Mode, shutdown) Oscillator not running,
VDD Monitor Disabled
—< 0.1— µA
Table 3.1. Global DC Electrical Characteristics (Continued)
–40°C to +85°C, 25 MHz System Clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Notes:
1. Given in Table 9.1 on page 110.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Based on device characterization data, not production tested.
4. Active and Inactive IDD at voltages and frequencies other than those specified can be calculated
using the IDD Supply Sensitivity. For example, if the VDD is 3.3 V instead of 3.0 V at 25 MHz: IDD =
7.8 mA typical at 3.0 V and f = 25 MHz. From this, IDD = 7.8 mA + 0.67 x (3.3 V – 3.0 V) = 8 mA at
3.3 V and f = 25 MHz.
5. IDD can be estimated for frequencies < 15 MHz by multiplying the frequency of interest by the fre-
quency sensitivity number for that range. When using these numbers to estimate IDD for > 15 MHz,
the estimate should be the current at 25 MHz minus the difference in current indicated by the fre-
quency sensitivity number. For example:
VDD = 3.0 V; F = 20 MHz, IDD = 7.8 mA – (25 MHz – 20 MHz) x 0.21 mA/MHz = 6.75 mA.
6. Idle IDD can be estimated for frequencies < 1 MHz by multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for > 1
MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the
frequency sensitivity number. For example:
VDD = 3.0 V; F = 5 MHz, Idle IDD = 4.8 mA – (25 MHz – 5 MHz) x 0.15 mA/MHz = 1.8 mA.
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
38 Rev. 1.8
Other electrical characteristics tables are found in the data sheet section corresponding to the associated
peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page
indicated in Table 3.2.
Table 3.2. Electrical Characteristics Quick Reference
Peripheral Electrical Characteristics Page No.
ADC0 Electrical Characteristics 65
External Voltage Reference Circuit Electrical Characteristics 68
Comparator Electrical Characteristics 78
Reset Electrical Characteristics 110
Flash Electrical Characteristics 112
Internal Oscillator Electrical Characteristics 123
Port I/O DC Electrical Characteristics 143
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 39
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F31x
Name Pin Numbers Type Description
‘F310/2/4 ‘F311/3/5 ‘F316/7
VDD 4 4 4 Power Supply Voltage.
GND 3 3 3 Ground.
RST/
C2CK
5 5 5
D I/O
D I/O
Device Reset. Open-drain output of internal POR. An
external source can initiate a system reset by driving
this pin low for at least 10 µs.
Clock signal for the C2 Debug Interface.
P3.0/
C2D 6 6 6 D I/O
D I/O
Port 3.0. See Section 13 for a complete description.
Bi-directional data signal for the C2 Debug Interface.
P0.0/
VREF 2 2 2 D I/O
A In
Port 0.0. See Section 13 for a complete description.
External VREF input. (‘F310/1/2/3 only)
P0.1 1 1 1 D I/O Port 0.1. See Section 13 for a complete description.
P0.2/
XTAL1
32 28 24
D I/O
A In
Port 0.2. See Section 13 for a complete description.
External Clock Input. This pin is the external oscillator
return for a crystal or resonator.
P0.3/
XTAL2
31 27 23
D I/O
A Out or
D In
Port 0.3. See Section 13 for a complete description.
External Clock Output. For an external crystal or reso-
nator, this pin is the excitation driver. This pin is the
external clock input for CMOS, capacitor, or RC oscil-
lator configurations.
P0.4 30 26 22 D I/O Port 0.4. See Section 13 for a complete description.
P0.5 29 25 21 D I/O Port 0.5. See Section 13 for a complete description.
P0.6/
CNVSTR 28 24 20 Port 0.6. See Section 13 for a complete description.
ADC0 External Convert Start Input. (‘F310/1/2/3 only)
P0.7 27 23 19 D I/O Port 0.7. See Section 13 for a complete description.
P1.0 26 22 18 D I/O or
A In Port 1.0. See Section 13 for a complete description.
P1.1 25 21 17 D I/O or
A In Port 1.1. See Section 13 for a complete description.
P1.2 24 20 16 D I/O or
A In Port 1.2. See Section 13 for a complete description.
P1.3 23 19 15 D I/O or
A In Port 1.3. See Section 13 for a complete description.
P1.4 22 18 14 D I/O or
A In Port 1.4. See Section 13 for a complete description.
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
40 Rev. 1.8
P1.5 21 17 13 D I/O or
A In Port 1.5. See Section 13 for a complete description.
P1.6 20 16 D I/O or
A In Port 1.6. See Section 13 for a complete description.
P1.7 19 15 D I/O or
A In Port 1.7. See Section 13 for a complete description.
P2.0 18 14 12 D I/O or
A In Port 2.0. See Section 13 for a complete description.
P2.1 17 13 11 D I/O or
A In Port 2.1. See Section 13 for a complete description.
P2.2 16 12 10 D I/O or
A In Port 2.2. See Section 13 for a complete description.
P2.3 15 11 9D I/O or
A In Port 2.3. See Section 13 for a complete description.
P2.4 14 10 8D I/O or
A In Port 2.4. See Section 13 for a complete description.
P2.5 13 9 7 D I/O or
A In Port 2.5. See Section 13 for a complete description.
P2.6 12 8D I/O or
A In Port 2.6. See Section 13 for a complete description.
P2.7 11 7D I/O or
A In Port 2.7. See Section 13 for a complete description.
P3.1 7D I/O or
A In Port 3.1. See Section 13 for a complete description.
P3.2 8D I/O or
A In Port 3.2. See Section 13 for a complete description.
P3.3 9D I/O or
A In Port 3.3. See Section 13 for a complete description.
P3.4 10 D I/O or
A In Port 3.4. See Section 13 for a complete description.
Table 4.1. Pin Definitions for the C8051F31x (Continued)
Name Pin Numbers Type Description
‘F310/2/4 ‘F311/3/5 ‘F316/7
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 41
Figure 4.1. LQFP-32 Pinout Diagram (Top View)
1
P3.2
P1.2
P1.7
P1.4
P1.3
P1.5VDD
/RST/C2CK
GND
P0.1
P0.0
P2.0
P2.1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
P1.6
C8051F310/2/4
Top View
P3.0/C2D
P3.1
P3.3
P3.4
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2 P1.1
P1.0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
C8051F310/1/2/3/4/5/6/7
42 Rev. 1.8
Figure 4.2. LQFP-32 Package Diagram
Table 4.2. LQFP-32
Package Dimensions
MM
MIN TYP MAX
A--1.60
A1 0.05 - 0.15
A2 1.35 1.40 1.45
b 0.30 0.37 0.45
D-9.00-
D1 - 7.00 -
e-0.80-
E-9.00-
E1 - 7.00 -
L 0.45 0.60 0.75
PIN 1
IDENTIFIER
A1
eb
1
32
E1
D1
D
E
A2
A
L
L IT HHHH WEN ,_‘ WWW JL q”WM SSSSSSSSSSS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 43
Figure 4.3. Typical LQFP-32 Landing Diagram
Table 4.3. LQFP-32 Landing Pattern Dimensions
Dimension Min Max
C1 8.40 8.50
C2 8.40 8.50
E 0.80 BSC.
X1 0.40 0.50
Y1 1.25 1.35
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
pad is to be 60?m minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
solder paste release.
5. The stencil thickness should be 0.125mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
44 Rev. 1.8
Figure 4.4. QFN-28 Pinout Diagram (Top View)
4
5
6
7
2
1
3
11
12
13
14
9
8
10
18
17
16
15
20
21
19
25
26
27
28
23
22
24
C8051F311/3/5
Top View
P0.1
P0.0
GND
VDD
/RST/C2CK
P3.0/C2D
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
GND
GND
«war \\\\\\\\\\\\\\ , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 45
Figure 4.5. QFN-28 Package Drawing
Table 4.4. QFN-28 Package Dimensions
MM MM
Dimension Min Nom Max Dimension Min Nom Max
A 0.80 0.90 1.00 L0.35 0.55 0.65
A1 0.00 0.02 0.05 L1 0.00 0.15
A3 0.25 REF aaa 0.15
b 0.18 0.23 0.30 bbb 0.10
D 5.00 BSC. ddd 0.05
D2 2.90 3.15 3.35 eee 0.08
e 0.50 BSC. Z0.44
E 5.00 BSC. Y0.18
E2 2.90 3.15 3.35
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VHHD except for custom features D2,
E2, L, Z, and Y which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
. 4% 7 ESE? i 4%— MUM mm” i Egg
C8051F310/1/2/3/4/5/6/7
46 Rev. 1.8
Figure 4.6. Typical QFN-28 Landing Diagram
Table 4.5. QFN-28 Landing Pattern Dimensions
Dimension Min Max
C1 4.80
C2 4.80
E0.50
X1 0.20 0.30
X2 3.20 3.30
Y1 0.85 0.95
Y2 3.20 3.30
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
pad is to be 60?m minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
solder paste release.
6. The stencil thickness should be 0.125mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 3x3 array of 0.90mm openings on a 1.1mm pitch should be used for the center pad to assure the proper
paste volume.
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
6" SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 47
Figure 4.7. QFN-24 Pinout Diagram (Top View)
GND P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
15
14
13
17
18
16
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
10
11
12
8
7
9
P0.1
P0.0
GND
VDD
/RST / C2CK
P3.0 / C2D
4
5
6
2
1
3
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
22
23
24
20
19
21
C8051F316/7
Top View
3—3—31 , F j 333333333337' ADP 3 3: 3g 3: 33, 3g 3 33 3333 333 3333 333 33 333 333353 E3 E3 [3 333733 , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
48 Rev. 1.8
Figure 4.8. QFN-24 Package Drawing
Table 4.6. QFN-24 Package Dimensions
MM MM
Dimension Min Nom Max Dimension Min Nom Max
A 0.70 0.75 0.80 L0.30 0.40 0.50
A1 0.00 0.02 0.05 L1 0.00 0.15
b 0.18 0.25 0.30 aaa 0.15
D 4.00 BSC. bbb 0.10
D2 2.55 2.70 2.80 ddd 0.05
e 0.50 BSC. eee 0.08
E 4.00 BSC. Z0.24
E2 2.55 2.70 2.80 Y0.18
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation WGGD except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
]IIII\E ‘ , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 49
Figure 4.9. Typical QFN-24 Landing Diagram
Table 4.7. QFN-24 Landing Pattern Dimensions
Dimension Min Max
C1 3.90 4.00
C2 3.90 4.00
E 0.50 BSC.
X1 0.20 0.30
X2 2.70 2.80
Y1 0.65 0.75
Y2 2.70 2.80
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
pad is to be 60?m minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
solder paste release.
5. The stencil thickness should be 0.125mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10mm x 1.10mm openings on 1.30mm pitch should be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
50 Rev. 1.8
F27 <4w pzj="" f31}="" ,="" .="" silieun="" labs="">
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 51
5. 12-Bit ADC (ADC0, C8051F310/1/2/3/6 only)
The ADC0 subsystem for the C8051F310/1/2/3/6 consists of two analog multiplexers (referred to collec-
tively as AMUX0) with 25 total input selections, and a 200 ksps, 12-bit successive-approximation-register
ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion
modes, and window detector are all configurable under software control via the Special Function Registers
shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured
to measure P1.0–P3.4, the Temperature Sensor output, or VDD with respect to P1.0–P3.4, VREF, or GND.
The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set
to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
Figure 5.1. ADC0 Functional Block Diagram
5.1. Analog Multiplexer
AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the
positive input: P1.0-P3.4, the on-chip temperature sensor, or the positive power supply (VDD). Any of the
following may be selected as the negative input: P1.0-P3.4, VREF, or GND. When GND is selected as
the negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differ-
ential Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in
SFR Definition 5.1 and SFR Definition 5.2.
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit
(ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 12-bit unsigned integers.
ADC0CF
AD0LJST
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
10-Bit
SAR
ADC
REF
SYSCLK
ADC0H
32
ADC0CN
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0BUSY
AD0INT
AD0TM
AD0EN
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Start
Conversion
000 AD0BUSY (W)
VDD
ADC0LTH
23-to-1
AMUX
AD0WINT
Temp
Sensor
23-to-1
AMUX
VDD
P1.0
P1.7
001
010
011
100 CNVSTR Input
Window
Compare
Logic
P2.0
P2.7
GND
P1.0
P1.7
P2.0
P2.7
P3.0
P3.4
101 Timer 3 Overflow
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
AMX0P
AMX0P4
AMX0P3
AMX0P2
AMX0P1
AMX0P0
AMX0N
AMX0N4
AMX0N3
AMX0N2
AMX0N1
AMX0N0
P3.0
P3.4
P3.1-3.4
available on
C8051F310/2
P3.1-3.4
available on
C8051F310/2
(+)
(-)
VREF
P2.6-2.7 available on
C8051F310/1/2/3/4/5
P1.6-1.7 available on
C8051F310/1/2/3/4/5
P2.6-2.7 available on
C8051F310/1/2/3/4/5
P1.6-1.7 available on
C8051F310/1/2/3/4/5
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
52 Rev. 1.8
Inputs are measured from ‘0’ to VREF * 1023/1024. Example codes are shown below for both right-justified
and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’.
When in Differential Mode, conversion codes are represented as 12-bit signed 2’s complement numbers.
Inputs are measured from -VREF to VREF * 511/512. Example codes are shown below for both right-justi-
fied and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a
Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2). See Section “13. Port Input/
Output” on page 129 for more Port I/O configuration details.
5.2. Temperature Sensor
The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the
positive ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P.
Figure 5.2. Typical Temperature Sensor Transfer Function
Input Voltage Right-Justified ADC0H:ADC0L
(AD0LJST = 0) Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF x 1023/1024 0x03FF 0xFFC0
VREF x 512/1024 0x0200 0x8000
VREF x 256/1024 0x0100 0x4000
0 0x0000 0x0000
Input Voltage Right-Justified ADC0H:ADC0L
(AD0LJST = 0) Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF x 511/512 0x01FF 0x7FC0
VREF x 256/512 0x0100 0x4000
0 0x0000 0x0000
–VREF x 256/512 0xFF00 0xC000
–VREF 0xFE00 0x8000
0-50 50 100
(Celsius)
V
TEMP
= 3.35*(TEMP
C
) + 897 mV
700
800
900
1000
1100
(mV)
1200
40 no 720 no 000 20 on «o no so on an on , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 53
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea-
surements (see Table 5.1 for linearity specifications). For absolute temperature measurements, gain and/
or offset calibration is recommended. Typically a 1-point calibration includes the following steps:
Step 1. Control/measure the ambient temperature (this temperature must be known).
Step 2. Power the device, and delay for a few seconds to allow for self-heating.
Step 3. Perform an ADC conversion with the temperature sensor selected as the positive input
and GND selected as the negative input.
Step 4. Calculate the offset and/or gain characteristics, and store these values in non-volatile
memory for use with subsequent temperature sensor measurements.
Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that
parameters which affect ADC measurement, in particular the voltage reference value, will also
affect temperature measurement.
Figure 5.3. Temperature Sensor Error with 1-Point Calibration
-40.00 -20.00 0.00 20.00 40.00 60.00 80.00
Temperature (degrees C)
Error (degrees C)
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
54 Rev. 1.8
5.3. Modes of Operation
ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by
(AD0SC + 1) for 0 AD0SC 31).
5.3.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2-0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
6. A Timer 3 overflow
Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte over-
flows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See
Section “17. Timers” on page 187 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register P0SKIP. See Section “13. Port
Input/Output” on page 129 for details on Port I/O configuration.
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 55
5.3.2. Tracking Modes
According to Table 5.1, each ADC0 conversion must be preceded by a minimum tracking time for the con-
verted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode.
In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When
the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion
is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR
signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low;
conversion begins on the rising edge of CNVSTR (see Figure 5.4). Tracking can also be disabled (shut-
down) when the device is in low power standby or sleep modes. Low-power track-and-hold mode is also
useful when AMUX settings are frequently changed, due to the settling time requirements described in
Section “5.3.3. Settling Time Requirements” on page 56.
Figure 5.4. 12-Bit ADC Track and Conversion Example Timing
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
AD0TM=1 Track Convert Low Power Mode
AD0TM=0 Track or
Convert Convert Track
Low Power
or Convert
SAR Clocks
123456789101112
123456789
SAR Clocks
B. ADC0 Timing for Internal Trigger Source
123456789
CNVSTR
(AD0CM[2:0]=100)
AD0TM=1
A. ADC0 Timing for External Trigger Source
SAR Clocks
Track or Convert Convert TrackAD0TM=0
Track Convert Low Power
Mode
Low Power
or Convert
10 11
13 14
10 11
% HQ , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
56 Rev. 1.8
5.3.3. Settling Time Requirements
When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum
tracking time is required before an accurate conversion can be performed. This tracking time is determined
by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accu-
racy required for the conversion. In low-power tracking mode, three SAR clocks are used for tracking at the
start of every conversion. For most applications, these three SAR clocks will meet the minimum tracking
time requirements.
Figure 5.5 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature
Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Table 5.1 for ADC0 minimum
settling time requirements.
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (12).
Figure 5.5. ADC0 Equivalent Input Circuits
Equation 5.1. ADC0 Settling Time Requirements
t2n
SA
-------

RTOTALCSAMPLE
ln=
R
MUX
= 5k
RC
Input
= R
MUX
* C
SAMPLE
R
MUX
= 5k
C
SAMPLE
= 5pF
C
SAMPLE
= 5pF
MUX Select
MUX Select
Differential Mode
Px.x
Px.x
R
MUX
= 5k
C
SAMPLE
= 5pF
RC
Input
= R
MUX
* C
SAMPLE
MUX Select
Single-Ended Mode
Px.x
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 57
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select
Bits7–5: UNUSED. Read = 000b; Write = don’t care.
Bits4–0: AMX0P4–0: AMUX0 Positive Input Selection
R R R R/W R/W R/W R/W R/W Reset Value
- - - AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBB
AMX0P4–0 ADC0 Positive Input
00000 P1.0
00001 P1.1
00010 P1.2
00011 P1.3
00100 P1.4
00101 P1.5
00110 P1.6(1)
00111 P1.7(1)
01000 P2.0
01001 P2.1
01010 P2.2
01011 P2.3
01100 P2.4
01101 P2.5
01110 P2.6(1)
01111 P2.7(1)
10000 P3.0
10001(2) P3.1(2)
10010(2) P3.2(2)
10011(2) P3.3(2)
10100(2) P3.4(2)
10101–11101 RESERVED
11110 Temp Sensor
11111 VDD
Notes:
1. Only applies to C8051F310/1/2/3/4/5; selection
RESERVED on C8051F316/7 devices.
2. Only applies to C8051F310/2; selection RESERVED on
C8051F311/3/6/7 devices.
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
58 Rev. 1.8
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select
Bits7–5: UNUSED. Read = 000b; Write = don’t care.
Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection.
Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended
mode. For all other Negative Input selections, ADC0 operates in Differential mode.
R R R R/W R/W R/W R/W R/W Reset Value
- - - AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBA
AMX0N4–0 ADC0 Negative Input
00000 P1.0
00001 P1.1
00010 P1.2
00011 P1.3
00100 P1.4
00101 P1.5
00110 P1.6(1)
00111 P1.7(1)
01000 P2.0
01001 P2.1
01010 P2.2
01011 P2.3
01100 P2.4
01101 P2.5
01110 P2.6(1)
01111 P2.7(1)
10000 P3.0
10001(2) P3.1(2)
10010(2) P3.2(2)
10011(2) P3.3(2)
10100(2) P3.4(2)
10101–11101 RESERVED
11110 VREF
11111 GND (ADC in Single-Ended Mode)
Notes:
1. Only applies to C8051F310/1/2/3/4/5; selection
RESERVED on C8051F316/7 devices.
2. Only applies to C8051F310/2; selection RESERVED on
C8051F311/3/6/7 devices.
SAR , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 59
SFR Definition 5.3. ADC0CF: ADC0 Configuration
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock require-
ments are given in Table 5.1.
Bit2: AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Bits1–0: UNUSED. Read = 00b; Write = don’t care.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJST - - 11111000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBC
AD0SC SYSCLK
CLKSAR
----------------------1=
Bits7–0: ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7–2 are the sign extension of Bit1. Bits 1–0 are the upper 2 bits of the
12-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 12-bit ADC0 Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBE
Bits7–0: ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 12-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 12-bit Data Word. Bits 5–0 will always
read ‘0’.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBD
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
60 Rev. 1.8
SFR Definition 5.6. ADC0CN: ADC0 Control
Bit7: AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6: AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion is
in progress.
1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below).
Bit5: AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4: AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set to
logic 1 on the falling edge of AD0BUSY.
1: ADC0 conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2-0 = 000b
Bit3: AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bits20: AD0CM20: ADC0 Start of Conversion Mode Select.
When AD0TM = 0:
000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
100: ADC0 conversion initiated on rising edge of external CNVSTR.
101: ADC0 conversion initiated on overflow of Timer 3.
11x: Reserved.
When AD0TM = 1:
000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by con-
version.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion.
100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR
edge.
101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion.
11x: Reserved.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xE8
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 61
5.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte
Bits7–0: High byte of ADC0 Greater-Than Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xC4
Bits7–0: Low byte of ADC0 Greater-Than Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xC3
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
62 Rev. 1.8
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte
Bits7–0: High byte of ADC0 Less-Than Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xC6
Bits7–0: Low byte of ADC0 Less-Than Data Word.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xC5
I}? x i ,,,,,,,,,,,,,,,,,, I% |:| |:| n -% l H IH , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 63
5.4.1. Window Detector In Single-Ended Mode
Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode,
the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a
10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0
conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt
will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and
ADC0LT registers (if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.7 shows an exam-
ple using left-justified data with the same comparison values.
Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data
Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
fl *************** i? a w EEEEEEEEEEEEEEEEEE I? 1 *************** i H w EEEEEEEEEEEEEEEEEE I? SSSSSSSSSSS
C8051F310/1/2/3/4/5/6/7
64 Rev. 1.8
5.4.2. Window Detector In Differential Mode
Figure 5.8 shows two example window comparisons for right-justified, differential data, with
ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the
measurable voltage between the input pins is between -VREF and VREF*(511/512). Output codes are rep-
resented as 12-bit 2’s complement signed integers. In the left example, an AD0WINT interrupt will be gen-
erated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL
and ADC0LTH:ADC0LTL (if 0xFFFF (-1d) < ADC0H:ADC0L < 0x0040 (64d)). In the right example, an
AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the
ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0xFFFF (-1d) or ADC0H:ADC0L > 0x0040 (+64d)).
Figure 5.9 shows an example using left-justified data with the same comparison values.
Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data
Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data
0x01FF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
-VREF
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x01FF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
-VREF
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0LADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
0x8000
-VREF
Input Voltage
(Px.x - Px.y)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
0x8000
-VREF
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0GTH:ADC0GTL
AD0WINT=1
AD0WINT=1
ADC0H:ADC0LADC0H:ADC0L
ADC0LTH:ADC0LTL
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 65
Table 5.1. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 12 bits
Integral Nonlinearity —±0.5±1LSB
Differential Nonlinearity Guaranteed Monotonic ±0.5 ±1 LSB
Offset Error –12 1 +12 LSB
Full Scale Error Differential mode –15 –5 +5 LSB
Offset Temperature Coefficient 3.6 — ppm/°C
Dynamic Performance (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion 53 55.5 — dB
Total Harmonic Distortion Up to the 5th harmonic —–67—dB
Spurious-Free Dynamic Range —78—dB
Conversion Rate
SAR Conversion Clock —— 3MHz
Conversion Time in SAR Clocks 10 — clocks
Track/Hold Acquisition Time 300 — ns
Throughput Rate 200 ksps
Analog Inputs
Input Voltage Range 0—VREFV
Input Capacitance —5—pF
Temperature Sensor ———
Linearity* —±0.5—°C
Gain* 3350 ± 10 µV / °C
Offset* (Temp = 0 °C) 897 ± 31 mV
Power Specifications
Power Supply Current
(VDD supplied to ADC0) Operating Mode, 200 ksps 400 900 µA
Power Supply Rejection —±0.3—mV/V
*Note: Represents one standard deviation from the mean. Includes ADC offset, gain, and linearity variations.
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
66 Rev. 1.8
NOTES:
SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 67
6. Voltage Reference (C8051F310/1/2/3/6 only)
The voltage reference MUX on C8051F310/1/2/3/6 devices is configurable to use an externally connected
voltage reference, or the power supply voltage (see Figure 6.1). The REFSL bit in the Reference Control
register (REF0CN) selects the reference source. For an external source, REFSL should be set to ‘0’; For
VDD as the reference source, REFSL should be set to ‘1’.
The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor,
and Internal Oscillator. This bit is forced to logic 1 when any of the aforementioned peripherals is enabled.
The bias generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see
SFR Definition 6.1 for REF0CN register details. The electrical specifications for the voltage reference cir-
cuit are given in Table 6.1.
Important Note About the VREF Input: Port pin P0.0 is used as the external VREF input. When using an
external voltage reference, P0.0 should be configured as analog input and skipped by the Digital Crossbar.
To configure P0.0 as analog input, set to ‘0’ Bit0 in register P0MDIN. To configure the Crossbar to skip
P0.0, set to ‘1’ Bit0 in register P0SKIP. Refer to Section “13. Port Input/Output” on page 129 for com-
plete Port I/O configuration details.
The temperature sensor connects to the highest order input of the ADC0 positive input multiplexer (see
Section “5.1. Analog Multiplexer” on page 51 for details). The TEMPE bit in register REF0CN
enables/disables the temperature sensor. While disabled, the temperature sensor defaults to a high imped-
ance state and any ADC0 measurements performed on the sensor result in meaningless data.
Figure 6.1. Voltage Reference Functional Block Diagram
Internal
VREF
(to ADC)
To Analog Mux
VDD
VREF
R1
VDD External
Voltage
Reference
Circuit
GND
REF0CN
REFSL
TEMPE
BIASE
Temp Sensor
EN
Bias Generator To ADC, Internal
Oscillator
EN
IOSCEN
0
1
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
68 Rev. 1.8
SFR Definition 6.1. REF0CN: Reference Control
Table 6.1. External Voltage Reference Circuit Electrical Characteristics
VDD = 3.0 V; –40 to +85 °C unless otherwise specified
Parameter Conditions Min Typ Max Units
Input Voltage Range 0V
DD V
Input Current Sample Rate = 200 ksps;
VREF = 3.0 V 12 µA
Bits7–4: UNUSED. Read = 0000b; Write = don’t care.
Bit3: REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: VREF input pin used as voltage reference.
1: VDD used as voltage reference.
Bit2: TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Bit1: BIASE: Internal Analog Bias Generator Enable Bit. (Must be ‘1’ if using ADC).
0: Internal Bias Generator off.
1: Internal Bias Generator on.
Bit0: UNUSED. Read = 0b. Write = don’t care.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
REFSL TEMPE BIASE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xD1
SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 69
7. Comparators
C8051F31x devices include two on-chip programmable voltage comparators: Comparator0 is shown in
Figure 7.1; Comparator1 is shown in Figure 7.2. The two comparators operate identically with the following
exceptions: (1) Their input selections differ as shown in Figure 7.1 and Figure 7.2; (2) Comparator0 can be
used as a reset source.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output with the device
in STOP mode. When assigned to a Port pin, the Comparator output may be configured as open drain or
push-pull (see Section “13.2. Port I/O Initialization” on page 133). Comparator0 may also be used as a
reset source (see Section “9.5. Comparator0 Reset” on page 108).
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1-CMX0P0
bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative
input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 7.5). The CMX1P1-
CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the Comparator1
negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “13.3. General Purpose Port I/O” on page 135).
Figure 7.1. Comparator0 Functional Block Diagram
VDD
CPT0CN
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
P1.0
P1.4
P2.0
P2.4
CP0 -
P1.1
P1.5
P2.1
P2.5
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CPT0MX
CMX0N1
CMX0N0
CMX0P1
CMX0P0
CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0
CP0A
CP0
Rising-edge CP0
Falling-edge
CP0
Interrupt
SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
70 Rev. 1.8
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and its supply current falls to less than 100 nA. See Section “13.1. Priority Crossbar Decoder” on
page 131 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator elec-
trical specifications are given in Table 7.1.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Defini-
tion 7.3 and SFR Definition 7.6). Selecting a longer response time reduces the Comparator supply current.
See Table 7.1 for complete timing and current consumption specifications.
Figure 7.2. Comparator1 Functional Block Diagram
VDD
CPT1CN
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP1 +
P1.2
P1.6
P2.2
P2.6
CP1 -
P1.3
P1.7
P2.3
P2.7
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CPT1MX
CMX1N1
CMX1N0
CMX1P1
CMX1P0
CPT1MD
CP1RIE
CP1FIE
CP1MD1
CP1MD0
CP1
CP1A
CP1
Rising-edge CP1
Falling-edge
CP1
Interrupt
HL , . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 71
Figure 7.3. Comparator Hysteresis Plot
The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for
n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage) and
the positive and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN
(shown in SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hysteresis voltage is
determined by the settings of the CPnHYN bits. As shown in Table 7.1, settings of 20, 10 or 5 mV of
negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the
amount of positive hysteresis is determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section “8.3. Interrupt Handler” on page 93). The CPnFIF flag is set
to logic 1 upon a Comparator falling-edge interrupt, and the CPnRIF flag is set to logic 1 upon the Compar-
ator rising-edge interrupt. Once set, these bits remain set until cleared by software. The output state of the
Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by set-
ting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Compar-
ator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered-on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed. This Power Up Time is specified in Table 7.1 on page 78.
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CP0+
CP0- CP0
VIN+
VIN- OUT
V
OH
Positive Hysteresis
Disabled Maximum
Positive Hysteresis
Negative Hysteresis
Disabled Maximum
Negative Hysteresis
OUTPUT
V
OL
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
72 Rev. 1.8
SFR Definition 7.1. CPT0CN: Comparator0 Control
Bit7: CP0EN: Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
Bit6: CP0OUT: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Bit5: CP0RIF: Comparator0 Rising-Edge Interrupt Flag.
0: No Comparator0 Rising Edge Interrupt has occurred since this flag was last cleared.
1: Comparator0 Rising Edge Interrupt has occurred.
Bit4: CP0FIF: Comparator0 Falling-Edge Interrupt Flag.
0: No Comparator0 Falling-Edge Interrupt has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge Interrupt has occurred.
Bits3–2: CP0HYP1-0: Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP0HYN1-0: Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
R/W R R/W R/W R/W R/W R/W R/W Reset Value
CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x9B
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 73
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bits5–4: CMX0N1–CMX0N0: Comparator0 Negative Input MUX Select.
These bits select which Port pin is used as the Comparator0 negative input.
Bits3–2: UNUSED. Read = 00b, Write = don’t care.
Bits1–0: CMX0P1–CMX0P0: Comparator0 Positive Input MUX Select.
These bits select which Port pin is used as the Comparator0 positive input.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - CMX0N1 CMX0N0 - - CMX0P1 CMX0P0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x9F
CMX0N1 CMX0N0 Negative Input
00 P1.1
01 P1.5
10 P2.1
11 P2.5
CMX0P1 CMX0P0 Positive Input
00 P1.0
01 P1.4
10 P2.0
11 P2.4
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
74 Rev. 1.8
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
Bits7–6: UNUSED. Read = 00b. Write = don’t care.
Bit5: CP0RIE: Comparator Rising-Edge Interrupt Enable.
0: Comparator rising-edge interrupt disabled.
1: Comparator rising-edge interrupt enabled.
Bit4: CP0FIE: Comparator Falling-Edge Interrupt Enable.
0: Comparator falling-edge interrupt disabled.
1: Comparator falling-edge interrupt enabled.
Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select
These bits select the response time for Comparator0.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - CP0RIE CP0FIE - - CP0MD1 CP0MD0 00000010
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x9D
Mode CP0MD1 CP0MD0 CP0 Response Time (TYP)
0 0 0 Fastest Response Time
101 —
210 —
3 1 1 Lowest Power Consumption
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 75
SFR Definition 7.4. CPT1CN: Comparator1 Control
Bit7: CP1EN: Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
Bit6: CP1OUT: Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
Bit5: CP1RIF: Comparator1 Rising-Edge Interrupt Flag.
0: No Comparator1 Rising Edge Interrupt has occurred since this flag was last cleared.
1: Comparator1 Rising Edge Interrupt has occurred.
Bit4: CP1FIF: Comparator1 Falling-Edge Interrupt Flag.
0: No Comparator1 Falling-Edge Interrupt has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge Interrupt has occurred.
Bits3–2: CP1HYP1–0: Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP1HYN1–0: Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
R/W R R/W R/W R/W R/W R/W R/W Reset Value
CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x9A
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
76 Rev. 1.8
SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bits5–4: CMX1N1–CMX1N0: Comparator1 Negative Input MUX Select.
These bits select which Port pin is used as the Comparator1 negative input.
Bits3–2: UNUSED. Read = 00b, Write = don’t care.
Bits1–0: CMX1P1–CMX1P0: Comparator1 Positive Input MUX Select.
These bits select which Port pin is used as the Comparator1 positive input.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - CMX1N1 CMX1N0 - - CMX1P1 CMX1P0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x9E
CMX1N1 CMX1N0 Negative Input
00 P1.3
01 P1.7
10 P2.3
11 P2.7
CMX1P1 CMX1P0 Positive Input
00 P1.2
01 P1.6
10 P2.2
11 P2.6
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 77
SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bit5: CP1RIE: Comparator Rising-Edge Interrupt Enable.
0: Comparator rising-edge interrupt disabled
1: Comparator rising-edge interrupt enabled.
Bit4: CP1FIE: Comparator Falling-Edge Interrupt Enable.
0: Comparator falling-edge interrupt disabled.
1: Comparator falling-edge interrupt enabled.
Bits1–0: CP1MD1–CP1MD0: Comparator1 Mode Select.
These bits select the response time for Comparator1.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - CP1RIE CP1FIE - - CP1MD1 CP1MD0 00000010
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x9C
Mode CP1MD1 CP1MD0 CP1 Response Time (TYP)
0 0 0 Fastest Response Time
101 —
210 —
3 1 1 Lowest Power Consumption
, ‘ SILIEIJN LABS
C8051F310/1/2/3/4/5/6/7
78 Rev. 1.8
Table 7.1. Comparator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise noted.
All specifications apply to both Comparator0 and Comparator1 unless otherwise noted.
Parameter Conditions Min Typ Max Units
Response Time:
Mode 0, Vcm1 = 1.5 V
CP0+ – CP0– = 100 mV 100 ns
CP0+ – CP0– = –100 mV 250 ns
Response Time:
Mode 1, Vcm1 = 1.5 V
CP0+ – CP0– = 100 mV 175 ns
CP0+ – CP0– = –100 mV 500 ns
Response Time:
Mode 2, Vcm1 = 1.5 V
CP0+ – CP0– = 100 mV 320 ns
CP0+ – CP0– = –100 mV 1100 ns
Response Time:
Mode 3, Vcm1 = 1.5 V
CP0+ – CP0– = 100 mV 1050 ns
CP0+ – CP0– = –100 mV 5200 ns
Common-Mode Rejection Ratio —1.5 4 mV/V
Positive Hysteresis 1 CP0HYP1-0 = 00 0 1 mV
Positive Hysteresis 2 CP0HYP1-0 = 01 2 5 7 mV
Positive Hysteresis 3 CP0HYP1-0 = 10 5 10 13 mV
Positive Hysteresis 4 CP0HYP1-0 = 11 12 20 25 mV
Negative Hysteresis 1 CP0HYN1-0 = 00 0 1 mV
Negative Hysteresis 2 CP0HYN1-0 = 01 2 5 7 mV
Negative Hysteresis 3 CP0HYN1-0 = 10 5 10 13 mV
Negative Hysteresis 4 CP0HYN1-0 = 11 12 20 25 mV
Inverting or Non-Inverting Input
Voltage Range –0.25 — VDD +
0.25
V
Input Capacitance —7— pF
Input Bias Current —1— nA
Input Offset Voltage –5 — +5 mV
Power Supply
Power Supply Rejection2 —0.1 1 mV/V
Power-up Time —10— µs
Supply Current at DC
Mode 0 7.6 20 µA
Mode 1 3.2 10 µA
Mode 2 1.3 5 µA
Mode 3 0.4 2.5 µA
Notes:
1. Vcm is the common-mode voltage on CP0+ and CP0–.
2. Guaranteed by design and/or characterization.
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 79
8. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
four 16-bit counter/timers (see description in Section 17), an enhanced full-duplex UART (see description
in Section 15), an Enhanced SPI (see description in Section 16), 256 bytes of internal RAM, 128 byte
Special Function Register (SFR) address space (Section 8.2.6), and 29 Port I/O (see description in Sec-
tion 13). The CIP-51 also includes on-chip debug hardware (see description in Section 20), and interfaces
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 includes the following features:
Figure 8.1. CIP-51 Block Diagram
- Fully Compatible with MCS-51 Instruction
Set
- 25 MIPS Peak Throughput with 25 MHz
Clock
- 0 to 25 MHz Clock Frequency
- 256 Bytes of Internal RAM
-29 Port I/O
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Logic
- Program and Data Memory Security
DATA BUS
TMP1 TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE POWER CONTROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
D8
STACK POINTER
D8
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
80 Rev. 1.8
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). The re-programmable Flash
can also be read and changed a single byte at a time by the application software using the MOVC and
MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well
as updating program code under software control.
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “20. C2 Interface” on page 223.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including an editor, evaluation compiler, assembler,
debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 inter-
face to provide fast and efficient in-system device programming and debugging. Third party macro assem-
blers and C compilers are also available.
8.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
8.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 8.1 is the
Clocks to Execute 1 2 2/3 33/4 44/5 5 8
Number of Instructions 26 50 514 73121
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 81
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
8.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory (Note: the C8051F31x does not
support external data or program memory). In the CIP-51, the MOVX write instruction is used to accesses
external RAM and the on-chip program memory space implemented as re-programmable Flash memory.
The Flash access feature provides a mechanism for the CIP-51 to update program code and use the pro-
gram memory space for non-volatile data storage. Refer to Section “10. Flash Memory” on page 111 for
further details.
Table 8.1. CIP-51 Instruction Set Summary
Mnemonic Description Bytes Clock
Cycles
Arithmetic Operations
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with borrow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2
SUBB A, #data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement direct byte 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
Logical Operations
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
, ‘ SILIEIJN LABS
C8051F310/1/2/3/4/5/6/7
82 Rev. 1.8
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 1 2
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #data OR immediate to direct byte 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
RL A Rotate A left 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 83
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carry 1 1
CPL bit Complement direct bit 2 2
ANL C, bit AND direct bit to Carry 2 2
ANL C, /bit AND complement of direct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to direct bit 2 2
JC rel Jump if Carry is set 22/3
JNC rel Jump if Carry is not set 22/3
JB bit, rel Jump if direct bit is set 33/4
JNB bit, rel Jump if direct bit is not set 33/4
JBC bit, rel Jump if direct bit is set and clear bit 33/4
Program Branching
ACALL addr11 Absolute subroutine call 2 3
LCALL addr16 Long subroutine call 3 4
RET Return from subroutine 1 5
RETI Return from interrupt 1 5
AJMP addr11 Absolute jump 2 3
LJMP addr16 Long jump 3 4
SJMP rel Short jump (relative address) 2 3
JMP @A+DPTR Jump indirect relative to DPTR 1 3
JZ rel Jump if A equals zero 22/3
JNZ rel Jump if A does not equal zero 22/3
CJNE A, direct, rel Compare direct byte to A and jump if not equal 33/4
CJNE A, #data, rel Compare immediate to A and jump if not equal 33/4
CJNE Rn, #data, rel Compare immediate to Register and jump if not
equal 33/4
CJNE @Ri, #data, rel Compare immediate to indirect and jump if not
equal 34/5
DJNZ Rn, rel Decrement Register and jump if not zero 22/3
DJNZ direct, rel Decrement direct byte and jump if not zero 33/4
NOP No operation 1 1
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
84 Rev. 1.8
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0–R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 85
8.2. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 8.2.
Figure 8.2. Memory Map
8.2.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F310/1 and C8051F312/3/4/5 imple-
ment 16k and 8 kB, respectively, of this program memory space as in-system, re-programmable Flash
memory, organized in a contiguous block from addresses 0x0000 to 0x3FFF or 0x0000 to 0x1FFF.
Addresses above 0x3E00 are reserved on the 16 kB devices.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to Section “10. Flash Memory” on page 111 for further details.
PROGRAM/DATA MEMORY
(Flash)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF Special Function
Register's
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
XRAM - 1024 Bytes
(accessable using MOVX
instruction)
0x0000
0x03FF
Same 1024 bytes as from
0x0000 to 0x03FF, wrapped
on 1 kB boundaries
0x0400
0xFFFF
16 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x3E00
0x3DFF
8 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x2000
0x1FFF
C8051F310/1
C8051F312/3/4/5
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
86 Rev. 1.8
8.2.2. Data Memory
The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through
0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem-
ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca-
tions 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting
of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
bytes or as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 8.2 illustrates the data memory organization of the CIP-51.
8.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 8.4). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
8.2.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
8.2.5. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 87
8.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 8.2 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 8.3,
for a detailed description of each register.
Table 8.2. Special Function Register (SFR) Memory Map
F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
F0 BP0MDIN P1MDIN P2MDIN P3MDIN EIP1
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC
E0 ACC XBR0 XBR1 IT01CF EIE1
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4
D0 PSW REF0CN P0SKIP P1SKIP P2SKIP
C8 TMR2CN TMR2RLL TMR2RLH TMR2L TMR2H
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH
B8 IP AMX0N AMX0P ADC0CF ADC0L ADC0H
B0 P3 OSCXCN OSCICN OSCICL FLSCL FLKEY
A8 IE CLKSEL EMI0CN
A0 P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT P3MDOUT
98 SCON0 SBUF0 CPT1CN CPT0CN CPT1MD CPT0MD CPT1MX CPT0MX
90 P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL
80 P0 SP DPL DPH PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
, ‘ SILIEIJN LABS
C8051F310/1/2/3/4/5/6/7
88 Rev. 1.8
Table 8.3. Special Function Registers
Register Address Description Page
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
ACC 0xE0 Accumulator 92
ADC0CF 0xBC ADC0 Configuration 59
ADC0CN 0xE8 ADC0 Control 60
ADC0GTH 0xC4 ADC0 Greater-Than Compare High 61
ADC0GTL 0xC3 ADC0 Greater-Than Compare Low 61
ADC0H 0xBE ADC0 High 59
ADC0L 0xBD ADC0 Low 59
ADC0LTH 0xC6 ADC0 Less-Than Compare Word High 62
ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low 62
AMX0N 0xBA AMUX0 Negative Channel Select 58
AMX0P 0xBB AMUX0 Positive Channel Select 57
B0xF0 B Register 93
CKCON 0x8E Clock Control 193
CLKSEL 0xA9 Clock Select 123
CPT0CN 0x9B Comparator0 Control 72
CPT0MD 0x9D Comparator0 Mode Selection 74
CPT0MX 0x9F Comparator0 MUX Selection 73
CPT1CN 0x9A Comparator1 Control 75
CPT1MD 0x9C Comparator1 Mode Selection 77
CPT1MX 0x9E Comparator1 MUX Selection 76
DPH 0x83 Data Pointer High 91
DPL 0x82 Data Pointer Low 90
EIE1 0xE6 Extended Interrupt Enable 1 99
EIP1 0xF6 Extended Interrupt Priority 1 100
EMI0CN 0xAA External Memory Interface Control 119
FLKEY 0xB7 Flash Lock and Key 117
FLSCL 0xB6 Flash Scale 117
IE 0xA8 Interrupt Enable 97
IP 0xB8 Interrupt Priority 98
IT01CF 0xE4 INT0/INT1 Configuration 101
OSCICL 0xB3 Internal Oscillator Calibration 122
OSCICN 0xB2 Internal Oscillator Control 122
OSCXCN 0xB1 External Oscillator Control 125
P0 0x80 Port 0 Latch 136
P0MDIN 0xF1 Port 0 Input Mode Configuration 136
P0MDOUT 0xA4 Port 0 Output Mode Configuration 137
P0SKIP 0xD4 Port 0 Skip 137
P1 0x90 Port 1 Latch 138
P1MDIN 0xF2 Port 1 Input Mode Configuration 138
P1MDOUT 0xA5 Port 1 Output Mode Configuration 139
P1SKIP 0xD5 Port 1 Skip 139
P2 0xA0 Port 2 Latch 140
P2MDIN 0xF3 Port 2 Input Mode Configuration 140
P2MDOUT 0xA6 Port 2 Output Mode Configuration 141
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 89
P2SKIP 0xD6 Port 2 Skip 141
P3 0xB0 Port 3 Latch 142
P3MDIN 0xF4 Port 3 Input Mode Configuration 142
P3MDOUT 0xA7 Port 3 Output Mode Configuration 143
PCA0CN 0xD8 PCA Control 215
PCA0CPH0 0xFC PCA Capture 0 High 219
PCA0CPH1 0xEA PCA Capture 1 High 219
PCA0CPH2 0xEC PCA Capture 2 High 219
PCA0CPH3 0xEE PCA Capture 3High 219
PCA0CPH4 0xFE PCA Capture 4 High 219
PCA0CPL0 0xFB PCA Capture 0 Low 218
PCA0CPL1 0xE9 PCA Capture 1 Low 218
PCA0CPL2 0xEB PCA Capture 2 Low 218
PCA0CPL3 0xED PCA Capture 3Low 218
PCA0CPL4 0xFD PCA Capture 4 Low 218
PCA0CPM0 0xDA PCA Module 0 Mode 217
PCA0CPM1 0xDB PCA Module 1 Mode 217
PCA0CPM2 0xDC PCA Module 2 Mode 217
PCA0CPM3 0xDD PCA Module 3 Mode 217
PCA0CPM4 0xDE PCA Module 4 Mode 217
PCA0H 0xFA PCA Counter High 218
PCA0L 0xF9 PCA Counter Low 218
PCA0MD 0xD9 PCA Mode 216
PCON 0x87 Power Control 103
PSCTL 0x8F Program Store R/W Control 116
PSW 0xD0 Program Status Word 92
REF0CN 0xD1 Voltage Reference Control 68
RSTSRC 0xEF Reset Source Configuration/Status 109
SBUF0 0x99 UART0 Data Buffer 169
SCON0 0x98 UART0 Control 168
SMB0CF 0xC1 SMBus Configuration 152
SMB0CN 0xC0 SMBus Control 154
SMB0DAT 0xC2 SMBus Data 156
SP 0x81 Stack Pointer 91
SPI0CFG 0xA1 SPI Configuration 180
SPI0CKR 0xA2 SPI Clock Rate Control 182
SPI0CN 0xF8 SPI Control 181
SPI0DAT 0xA3 SPI Data 182
TCON 0x88 Timer/Counter Control 191
TH0 0x8C Timer/Counter 0 High 194
TH1 0x8D Timer/Counter 1 High 194
TL0 0x8A Timer/Counter 0 Low 194
TL1 0x8B Timer/Counter 1 Low 194
TMOD 0x89 Timer/Counter Mode 192
TMR2CN 0xC8 Timer/Counter 2 Control 197
TMR2H 0xCD Timer/Counter 2 High 198
Table 8.3. Special Function Registers (Continued)
Register Address Description Page
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
90 Rev. 1.8
8.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic 1. Future product versions may use these bits to implement new features in
which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descrip-
tions of the remaining SFRs are included in the sections of the data sheet associated with their corre-
sponding system function.
SFR Definition 8.1. DPL: Data Pointer Low Byte
TMR2L 0xCC Timer/Counter 2 Low 198
TMR2RLH 0xCB Timer/Counter 2 Reload High 198
TMR2RLL 0xCA Timer/Counter 2 Reload Low 198
TMR3CN 0x91 Timer/Counter 3Control 201
TMR3H 0x95 Timer/Counter 3 High 202
TMR3L 0x94 Timer/Counter 3Low 202
TMR3RLH 0x93 Timer/Counter 3 Reload High 202
TMR3RLL 0x92 Timer/Counter 3 Reload Low 202
VDM0CN 0xFF VDD Monitor Control 107
XBR1 0xE2 Port I/O Crossbar Control 1 135
XBR0 0xE1 Port I/O Crossbar Control 0 134
0x84-0x86, 0x96-0x97,
0xAB-0xAF, 0xB4, 0xB9,
0xBF, 0xC7, 0xC9, 0xCE,
0xCF, 0xD2, 0xD3, 0xD7,
0xDF, 0xE3, 0xE5, 0xF5
Reserved
Table 8.3. Special Function Registers (Continued)
Register Address Description Page
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x82
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 91
SFR Definition 8.2. DPH: Data Pointer High Byte
SFR Definition 8.3. SP: Stack Pointer
Bits7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x83
Bits7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x81
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
92 Rev. 1.8
SFR Definition 8.4. PSW: Program Status Word
SFR Definition 8.5. ACC: Accumulator
Bit7: CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
Bit6: AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic opera-
tions.
Bit5: F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4–3: RS1–RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
Bit2: OV: Overflow Flag.
This bit is set to 1 under the following circumstances: an ADD, ADDC, or SUBB instruction
causes a sign-change overflow, a MUL instruction results in an overflow (result is greater
than 255), or a DIV instruction causes a divide-by-zero condition. The OV bit is cleared to 0
by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases.
Bit1: F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
Bit0: PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
R/WR/WR/WR/WR/WR/WR/W RReset Value
CY AC F0 RS1 RS0 OV F1 PARITY 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xD0
RS1 RS0 Register Bank Address
0 0 0 0x00–0x07
0 1 1 0x08–0x0F
1 0 2 0x10–0x17
1 1 3 0x18–0x1F
Bits7–0: ACC: Accumulator.
This register is the accumulator for arithmetic operations.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xE0
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 93
SFR Definition 8.6. B: B Register
8.3. Interrupt Handler
The CIP-51 includes an extended interrupt system supporting a total of 14 interrupt sources with two prior-
ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated interrupt-
pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition,
the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE-EIE1). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables
all interrupt sources regardless of the individual interrupt-enable settings.
Note: Any instruction that clears the EA bit should be immediately followed by an instruction that
has two or more opcode bytes. For example:
// in 'C':
EA = 0; // clear EA bit
EA = 0; // ... followed by another 2-byte opcode
; in assembly:
CLR EA ; clear EA bit
CLR EA ; ... followed by another 2-byte opcode
If an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears
the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. How-
ever, a read of the EA bit will return a '0' inside the interrupt service routine. When the "CLR EA" opcode is
followed by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
Bits7–0: B: B Register.
This register serves as a second accumulator for certain arithmetic operations.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xF0
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
94 Rev. 1.8
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
8.3.1. MCU Interrupt Sources and Vectors
The MCUs support 14 interrupt sources. Software can simulate an interrupt by setting any interrupt-pend-
ing flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU
will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associ-
ated vector addresses, priority order and control bits are summarized in Table 8.4 on page 96. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 95
8.3.2. External Interrupts
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “17.1. Timer 0 and Timer 1” on page 187) select level
or edge sensitive. The table below lists the possible configurations.
/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 8.11).
Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and
/INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin
via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the
selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section
“13.1. Priority Crossbar Decoder” on page 131 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external
interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corre-
sponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR.
When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as
defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inac-
tive. The external interrupt source must hold the input active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
8.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 8.4.
8.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
IT0 IN0PL /INT0 Interrupt IT1 IN1PL /INT1 Interrupt
10
Active low, edge sensitive 10Active low, edge sensitive
11Active high, edge sensitive 11Active high, edge sensitive
00Active low, level sensitive 00Active low, level sensitive
01Active high, level sensitive 01Active high, level sensitive
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
96 Rev. 1.8
Table 8.4. Interrupt Summary
Interrupt Source Interrupt
Vector Priority
Order Pending Flag
Bit addressable?
Cleared by HW?
Enable
Flag Priority
Control
Reset 0x0000 Top None N/A N/A Always
Enabled Always
Highest
External Interrupt 0 (/INT0) 0x0003 0IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow 0x000B 1TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1)
External Interrupt 1 (/INT1) 0x0013 2IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow 0x001B 3TF1 (TCON.7) Y Y ET1 (IE.3) PT1 (IP.3)
UART0 0x0023 4RI0 (SCON0.0)
TI0 (SCON0.1) Y N ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow 0x002B 5TF2H (TMR2CN.7)
TF2L (TMR2CN.6) Y N ET2 (IE.5) PT2 (IP.5)
SPI0 0x0033 6
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN
(SPI0CN.4)
Y N ESPI0
(IE.6) PSPI0
(IP.6)
SMB0 0x003B 7SI (SMB0CN.0) Y N ESMB0
(EIE1.0) PSMB0
(EIP1.0)
RESERVED 0x0043 8 N/A N/A N/A N/A N/A
ADC0 Window Compare 0x004B 9AD0WINT
(ADC0CN.3) Y N EWADC0
(EIE1.2) PWADC0
(EIP1.2)
ADC0 Conversion
Complete 0x0053 10 AD0INT
(ADC0CN.5) Y N EADC0
(EIE1.3) PADC0
(EIP1.3)
Programmable Counter
Array 0x005B 11 CF (PCA0CN.7)
CCFn (PCA0CN.n) Y N EPCA0
(EIE1.4) PPCA0
(EIP1.4)
Comparator0 0x0063 12
CP0FIF
(CPT0CN.4)
CP0RIF
(CPT0CN.5)
N N ECP0
(EIE1.5) PCP0
(EIP1.5)
Comparator1 0x006B 13
CP1FIF
(CPT1CN.4)
CP1RIF
(CPT1CN.5)
N N ECP1
(EIE1.6) PCP1
(EIP1.6)
Timer 3 Overflow 0x0073 14 TF3H (TMR3CN.7)
TF3L (TMR3CN.6) N N ET3
(EIE1.7) PT3
(EIP1.7)
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 97
8.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
SFR Definition 8.7. IE: Interrupt Enable
Bit7: EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set-
tings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Bit6: ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
Bit5: ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Bit4: ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Bit3: ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Bit2: EX1: Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
Bit1: ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Bit0: EX0: Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xA8
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
98 Rev. 1.8
SFR Definition 8.8. IP: Interrupt Priority
Bit7: UNUSED. Read = 1, Write = don't care.
Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
Bit5: PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupts set to low priority level.
1: Timer 2 interrupts set to high priority level.
Bit4: PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupts set to low priority level.
1: UART0 interrupts set to high priority level.
Bit3: PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupts set to low priority level.
1: Timer 1 interrupts set to high priority level.
Bit2: PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
Bit1: PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
Bit0: PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- PSPI0 PT2 PS0 PT1 PX1 PT0 PX0 10000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xB8
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 99
SFR Definition 8.9. EIE1: Extended Interrupt Enable 1
Bit7: ET3: Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
Bit6: ECP1: Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
Bit5: ECP0: Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
Bit4: EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Bit3: EADC0: Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
Bit2: EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
Bit1: RESERVED. Read = 0. Must Write 0.
Bit0: ESMB0: Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 Reserved ESMB0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xE6
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
100 Rev. 1.8
SFR Definition 8.10. EIP1: Extended Interrupt Priority 1
Bit7: PT3: Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
Bit6: PCP1: Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
Bit5: PCP0: Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
Bit4: PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
Bit3: PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
Bit2: PWADC0: ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
Bit1: RESERVED. Read = 0. Must Write 0.
Bit0: PSMB0: SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
PT3 PCP1 PCP0 PCP0 PADC0 PWADC0 Reserved PSMB0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xF6
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 101
SFR Definition 8.11. IT01CF: INT0/INT1 Configuration
Bit7: IN1PL: /INT1 Polarity
0: /INT1 input is active low.
1: /INT1 input is active high.
Bits6–4: IN1SL2–0: /INT1 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT1. Note that this pin assignment is inde-
pendent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
Bit3: IN0PL: /INT0 Polarity
0: /INT0 interrupt is active low.
1: /INT0 interrupt is active high.
Bits2–0: INT0SL2–0: /INT0 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT0. Note that this pin assignment is inde-
pendent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
IN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 00000001
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xE4
Note: Refer to SFR Definition 17.1 for INT0/1 edge- or level-sensitive interrupt selection.
IN1SL2–0 /INT1 Port Pin
000 P0.0
001 P0.1
010 P0.2
011 P0.3
100 P0.4
101 P0.5
110 P0.6
111 P0.7
IN0SL2–0 /INT0 Port Pin
000 P0.0
001 P0.1
010 P0.2
011 P0.3
100 P0.4
101 P0.5
110 P0.6
111 P0.7
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
102 Rev. 1.8
8.4. Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter-
rupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped
(analog peripherals remain in their selected states; the external oscillator is not effected). Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode consumes the least power. SFR Defini-
tion 8.12 describes the Power Control Register (PCON) used to control the CIP-51's power management
modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital
peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscil-
lators lowers power consumption considerably; however, a reset is required to restart the MCU.
8.4.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “9.6. PCA Watchdog
Timer Reset” on page 108 for more information on the use and configuration of the WDT.
Note: Any instruction that sets the IDLE bit should be immediately followed by an instruction that
has 2 or more opcode bytes. For example:
// in 'C':
PCON |= 0x01; // set IDLE bit
PCON = PCON; // ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h ; set IDLE bit
MOV PCON, PCON; ... followed by a 3-cycle dummy instruction
If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during
the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from IDLE mode when
a future interrupt occurs.
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 103
8.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-
tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripher-
als are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including
the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset
sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µsec.
SFR Definition 8.12. PCON: Power Control
Bits7–2: GF5–GF0: General Purpose Flags 5–0.
These are general purpose flags for use under software control.
Bit1: STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
Bit0: IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
GF5 GF4 GF3 GF2 GF1 GF0 STOP IDLE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x87
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
104 Rev. 1.8
NOTES:
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 105
9. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to Section “12. Oscillators” on page 121 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section “18.3. Watchdog Timer Mode” on page 212 details the use of the Watchdog Timer).
Program execution begins at location 0x0000.
Figure 9.1. Reset Sources
PCA
WDT
Missing
Clock
Detector
(one-
shot) (Software Reset)
System Reset
Reset
Funnel
Px.x
Px.x
EN
SWRSF
System
Clock
CIP-51
Microcontroller
Core
Extended Interrupt
Handler
EN
WDT
Enable
MCD
Enable
Errant
FLASH
Operation
/RST
(wired-OR)
Power On
Reset
'0'
+
-
Comparator 0
C0RSEF
VDD
+
-
Supply
Monitor
Enable
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
106 Rev. 1.8
9.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. An additional delay occurs before the device is released from reset; the delay decreases as the VDD
ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 9.2. plots
the power-on and VDD monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset
delay (TPORDelay) is typically less than 0.3 ms.
Note: The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be released from
reset before VDD reaches the VRST level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The VDD monitor is disabled following a
power-on reset.
Figure 9.2. Power-On and VDD Monitor Reset Timing
9.2. Power-Fail Reset / VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 9.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD
monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by
Power-On
Reset
VDD
Monitor
Reset
/RST
t
volts
1.0
2.0
Logic HIGH
Logic LOW T
PORDelay
VDD
2.70
2.55
V
RST
VDD
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 107
any other reset source. For example, if the VDD monitor is enabled and a software reset is performed, the
VDD monitor will still be enabled after the reset.
Important Note: The VDD monitor must be enabled before it is selected as a reset source. Selecting the
VDD monitor as a reset source before it is enabled and stabilized may cause a system reset. The proce-
dure for configuring the VDD monitor as a reset source is shown below:
Step 1. Enable the VDD monitor (VDMEN bit in VDM0CN = ‘1’).
Step 2. Wait for the VDD monitor to stabilize (see Table 9.1 for the VDD Monitor turn-on time).
Note: This delay should be omitted if software contains routines that erase or write Flash
memory.
Step 3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
See Figure 9.2 for VDD monitor timing; note that the reset delay is not incurred after a VDD monitor reset.
See Table 9.1 for complete electrical characteristics of the VDD monitor.
SFR Definition 9.1. VDM0CN: VDD Monitor Control
9.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 9.1 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
Bit7: VDMEN: VDD Monitor Enable.
This bit is turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system
resets until it is also selected as a reset source in register RSTSRC (Figure 9.2). The VDD
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
VDD monitor as a reset source before it has stabilized may generate a system reset.
See Table 9.1 for the minimum VDD Monitor turn-on time.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
Bit6: VDD STAT: VDD Status.
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above the VDD monitor threshold.
Bits5–0: Reserved. Read = Variable. Write = don’t care.
R/W R R R R R R R Reset Value
VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved Variable
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address: 0xFF
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
108 Rev. 1.8
9.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
9.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Com-
parator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the
reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by this reset.
9.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “18.3. Watchdog Timer Mode” on
page 212; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to ‘1’. The state of the RST pin is unaffected by this reset.
9.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a
MOVX write operation targets an address above address 0x3DFF for C8051F310/1 or 0x1FFF for
C8051F312/3/4/5.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above address 0x3DFF for C8051F310/1 or 0x1FFF for C8051F312/3/4/5.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above 0x3DFF for C8051F310/1 or 0x1FFF for C8051F312/3/4/5.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“10.3. Security Options” on page 113).
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
9.8. Software Reset
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
, . SILIEUN LABS
C8051F310/1/2/3/4/5/6/7
Rev. 1.8 109
SFR Definition 9.2. RSTSRC: Reset Source
Bit7: UNUSED. Read = 0. Write = don’t care.
Bit6: FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
Bit5: C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0. Write: Comparator0 is not a reset
source.
1: Read: Source of last reset was Comparator0. Write: Comparator0 is a reset source
(active-low).
Bit4: SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit. Write: No Effect.
1: Read: Source of last was a write to the SWRSF bit. Write: Forces a system reset.
Bit3: WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
Bit2: MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout. Write: Missing
Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout. Write: Missing Clock
Detector enabled; triggers a reset if a missing clock condition is detected.
Bit1: PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the VDD
monitor as a reset source. Note: writing ‘1’ to this bit before the VDD monitor is enabled
and stabilized may cause a system reset. See register VDM0CN (Figure 9.1)
0: Read: Last reset was not a power-on or VDD monitor reset. Write: VDD monitor is not a
reset source.
1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags indeterminate.
Write: VDD monitor i