TSU101, 102, 104 Datasheet by STMicroelectronics

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September 2015
DocID024317 Rev 3
1/33
This is information on a product in full production.
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TSU101, TSU102, TSU104
Nanopower, rail-to-rail input and output, 5 V CMOS operational
amplifiers
Datasheet - production data
Features
Submicro ampere current consumption:
580 nA typ per channel at 25 °C at
VCC = 1.8 V
Low supply voltage: 1.5 V - 5.5 V
Unity gain stable
Rail-to-rail input and output
Gain bandwidth product: 8 kHz typ
Low input bias current: 5 pA max at 25 °C
High tolerance to ESD: 2 kV HBM
Industrial temperature range:
-40 °C to 85 °C
Benefits
42 years of typical equivalent lifetime
(for TSU101) if supplied by a 220 mAh coin
type Lithium battery
Tolerance to power supply transient drops
Accurate signal conditioning of high
impedance sensors
Application performances guaranteed over
industrial temperature range
Fast desaturation
Applications
Ultra long life battery-powered applications
Power metering
UV and photo sensors
Electrochemical and gas sensors
Pyroelectric passive infrared (PIR) detection
Battery current sensing
Medical instrumentation
RFID readers
Description
The TSU101, TSU102, and TSU104 operational
amplifiers offer an ultra low-power consumption
of 580 nA typical and 750 nA maximum per
channel when supplied by 1.8 V. Combined with
a supply voltage range of 1.5 V to 5.5 V, these
features allow the TSU10x series to be efficiently
supplied by a coin type Lithium battery or a
regulated voltage in low-power applications.
The 8 kHz gain bandwidth of these devices make
them ideal for sensor signal conditioning, battery
supplied, and portable applications.
Contents
2/33
DocID024317 Rev 3
Contents
1 Package pin connections ................................................................ 3
2 Absolute maximum ratings and operating conditions ................. 4
3 Electrical characteristics ................................................................ 5
4 Application information ................................................................ 17
4.1 Operating voltages .......................................................................... 17
4.2 Rail-to-rail input ............................................................................... 17
4.3 Input offset voltage drift over temperature ....................................... 17
4.4 Long term input offset voltage drift .................................................. 18
4.5 Schematic optimization aiming for nanopower ................................ 19
4.6 PCB layout considerations .............................................................. 20
4.7 Using the TSU10x series with sensors ............................................ 20
4.8 Fast desaturation ............................................................................ 22
4.9 Using the TSU10x series in comparator mode ................................ 22
4.10 ESD structure of TSU10x series ..................................................... 22
5 Package information ..................................................................... 23
5.1 SC70-5 (or SOT323-5) package information ................................... 24
5.2 SOT23-5 package information ........................................................ 25
5.3 DFN8 2x2 package information ....................................................... 26
5.4 MiniSO8 package information ......................................................... 27
5.5 QFN16 3x3 package information ..................................................... 28
5.6 TSSOP14 package information ....................................................... 30
6 Ordering information ..................................................................... 31
7 Revision history ............................................................................ 32
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TSU101, TSU102, TSU104
Package pin connections
DocID024317 Rev 3
3/33
1 Package pin connections
Figure 1: Pin connections for each package (top view)
Absolute maximum ratings and operating
conditions
4/33
DocID024317 Rev 3
2 Absolute maximum ratings and operating conditions
Table 1: Absolute maximum ratings (AMR)
Symbol Parameter Value Unit
VCC Supply voltage
(1)
6
V
Vid Differential input voltage
(2)
±VCC
Vin Input voltage
(3)
(VCC-) - 0.2 to (VCC+) + 0.2
Iin Input current (4) 10 mA
Tstg Storage temperature -65 to 150 °C
Tj Maximum junction temperature 150
Rthja Thermal resistance junction to
ambient (5)(6)
SC70-5 205
°C/W
SOT23-5 250
DFN8 2x2 117
MiniSO8 190
QFN16 3x3 45
TSSOP14 100
ESD
HBM: human body model (7) 2000
V
MM: machine model
(8)
200
CDM: charged device model (9)
All other packages
except SC70-5 1000
SC70-5 900
Latch-up immunity (10)
200 mA
Notes:
(1)All voltage values, except the differential voltage are with respect to the network ground terminal.
(2)The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
(3)((VCC+) - Vin) must not exceed 6 V, (Vin - VCC-) must not exceed 6 V.
(4)The input current must be limited by a resistor in series with the inputs.
(5)Rth are typical values.
(6)Short-circuits can cause excessive heating and destructive dissipation.
(7)Related to ESDA/JEDEC JS-001 Apr. 2010
(8)Related to JEDEC JESD22-A115C Nov.2010
(9)Related to JEDEC JESD22-C101-E Dec. 2009
(10)Related to JEDEC JESD78C Sept. 2010
Table 2: Operating conditions
Symbol Parameter Value Unit
VCC Supply voltage 1.5 to 5.5 V
Vicm Common mode input voltage range (VCC-) - 0.1 to (VCC+) + 0.1
Toper Operating free air temperature range -40 to 85 °C
krical characleriskics a: VCC+ =1.B V wilh VCC- = 0 V, Vic C, and RL =1 Mn connected to VCCIZ (unless otherwise
TSU101, TSU102, TSU104
Electrical characteristics
DocID024317 Rev 3
5/33
3 Electrical characteristics
Table 3: Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2,
Tamb = 25 ° C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio Input offset voltage
-3 0.1 3 mV
-40 °C < T< 85 °C -3.4
3.4
ΔVio/ΔT Input offset voltage drift -40 °C < T< 85 °C
5 μV/°C
ΔVio Long-term input offset
voltage drift T = 25 °C (1)
0.18
µV/
√month
Iio Input offset current (2)
1 5
pA
-40 °C < T< 85 °C
30
Iib Input bias current (2)
1 5
-40 °C < T< 85 °C
30
CMR Common mode rejection
ratio 20 log (ΔVicm/ΔVio)
Vicm = 0 to 0.6 V, Vout = VCC/2 65 85
dB
-40 °C < T< 85 °C 65
Vicm = 0 to 1.8 V, Vout = VCC/2 55 74
-40 °C < T< 85 °C 55
Avd Large signal voltage gain
Vout = 0.3 V to ((VCC+) - 0.3 V),
RL = 100 95 115
-40 °C < T< 85 °C 95
VOH High level output voltage,
(drop from VCC+)
RL = 100
40
mV
-40 °C < T< 85 °C
40
VOL Low level output voltage RL = 100
40
-40 °C < T< 85 °C
40
Iout
Output sink current Vout = VCC , VID = -200 mV 4 5
mA
-40 °C < T< 85 °C 4
Output source current Vout = 0 V, VID = 200 mV 4 5
-40 °C < T< 85 °C 4
ICC Supply current,
(per channel)
No load, Vout = VCC/2
580 750 nA
-40 °C < T< 85 °C
800
AC performance
GBP Gain bandwidth product
RL = 1 MΩ, CL = 60 pF
8
kHz
Fu Unity gain frequency
8
ϕm Phase margin
60
Degrees
Gm Gain margin
10
dB
SR Slew rate (10 % to 90 %) RL = 1 MΩ, CL = 60 pF
Vout = 0.3 V to ((VCC+) - 0.3 V)
3
V/ms
en Equivalent input noise
voltage
f = 100 Hz
265
nV/√Hz
f = 1 kHz
265
Electrical characteristics
6/33
DocID024317 Rev 3
Symbol Parameter Conditions Min. Typ. Max. Unit
∫en Low-frequency peak-to-
peak input noise Bandwidth: f = 0.1 to 10 Hz
9
µVpp
in Equivalent input noise
current
f = 100 Hz
0.64
fA/√Hz
f = 1 kHz
4.4
trec Overload recovery time 100 mV from rail in comparator,
RL = 100 kΩ, VID = ±VCC,
-40 °C < T< 85 °C 30 µs
Notes:
(1)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
(2)Guaranteed by design.
krical characleriskics a: VCC+ = 3.3 V wilh VCC- = 0 V, Vicm = VCC/Z C, and RL = 1 Mn connected to VCCIZ (unless otherWIse specifiedp
TSU101, TSU102, TSU104
Electrical characteristics
DocID024317 Rev 3
7/33
Table 4: Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2,
Tamb = 25 ° C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio Input offset voltage
-3 0.1 3 mV
-40 °C < T< 85 °C -3.4
3.4
ΔVio/ΔT Input offset voltage drift -40 °C < T< 85 °C
5 μV/°C
ΔVio Long-term input offset
voltage drift T = 25 °C (1)
0.36
µV/
√month
Iio Input offset current (2)
1 5
pA
-40 °C < T< 85 °C
30
Iib Input bias current (2)
1 5
-40 °C < T< 85 °C
30
CMR Common mode rejection
ratio 20 log (ΔVicm/ΔVio)
Vicm = 0 to 2.1 V, Vout = VCC/2 70 92
dB
-40 °C < T< 85 °C 70
Vicm = 0 to 3.3 V, Vout = VCC/2 60 77
-40 °C < T< 85 °C 60
Avd Large signal voltage gain
Vout = 0.3 V to ((VCC+) - 0.3 V),
RL= 100 105 120
-40 °C < T< 85 °C 105
VOH High level output voltage
(drop from VCC+)
RL = 100
40
mV
-40 °C < T< 85 °C
40
VOL Low level output voltage RL = 100
40
-40 °C < T< 85 °C
40
Iout
Output sink current Vout = VCC , VID = -200 mV 6 9
mA
-40 °C < T< 85 °C 6
Output source current Vout = 0 V, VID = 200 mV 8 11
-40 °C < T< 85 °C 8
ICC Supply current,
(per channel)
No load, Vout = VCC/2
600 800 nA
-40 °C < T< 85 °C
850
AC performance
GBP Gain bandwidth product
RL = 1 MΩ, CL = 60 pF
8
kHz
Fu Unity gain frequency
8
ϕm Phase margin
60
Degrees
Gm Gain margin
11
dB
SR Slew rate (10 % to 90 %) RL = 1 MΩ, CL = 60 pF,
Vout = 0.3 V to ((VCC+) - 0.3 V)
3
V/ms
en Equivalent input noise
voltage
f = 100 Hz
260
nV/√Hz
f = 1 kHz
255
∫en Low-frequency peak-to-
peak input noise Bandwidth: f = 0.1 to 10 Hz
8.6
µVpp
Electrical characteristics
8/33
DocID024317 Rev 3
Symbol Parameter Conditions Min. Typ. Max. Unit
in Equivalent input noise
current
f = 100 Hz
0.55
fA/√Hz
f = 1 kHz
3.8
trec Overload recovery time 100 mV from rail in comparator,
RL = 100 kΩ, VID = ±VCC,
-40 °C < T< 85 °C 30 µs
Notes:
(1)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
(2)Guaranteed by design.
clrical charauerislics al VCC+ = 5 V wflh VCC- = O V, Vicm = VCC/Z, C, and RL =1 Mn connected to VCCIZ (unless otherwise specifiedp
TSU101, TSU102, TSU104
Electrical characteristics
DocID024317 Rev 3
9/33
Table 5: Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2,
Tamb = 25 ° C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio Input offset voltage
-3 0.1 3 mV
-40 °C < T< 85 °C -3.4
3.4
ΔVio/ΔT Input offset voltage drift -40 °C < T< 85 °C
5 μV/°C
ΔVio Long-term input offset
voltage drift T = 25 °C (1)
1.1
µV/
√month
Iio Input offset current (2)
1 5
pA
-40 °C < T< 85 °C
30
Iib Input bias current (2)
1 5
-40 °C < T< 85 °C
30
CMR Common mode rejection
ratio 20 log (ΔVicm/ΔVio)
Vicm = 0 to 3.8 V, Vout = VCC/2 70 90
dB
-40 °C < T< 85 °C 70
Vicm = 0 to 5 V, Vout = VCC/2 65 82
-40 °C < T< 85 °C 65
SVR Supply voltage rejection
ratio
VCC = 1.5 to 5.5 V, Vicm = 0 V 70 90
-40 °C < T< 85 °C 70
Avd Large signal voltage gain
Vout = 0.3 V to ((Vcc+) - 0.3 V),
RL= 100 110 130
-40 °C < T< 85 °C 110
VOH High level output voltage,
(drop from VCC+)
RL = 100
40
mV
-40 °C < T< 85 °C
40
VOL Low level output voltage RL = 100
40
-40 °C < T< 85 °C
40
Iout
Output sink current Vout = VCC , VID = -200 mV 6 9
mA
-40 °C < T< 85 °C 6
Output source current Vout = 0 V, VID = 200 mV 8 11
-40 °C < T< 85 °C 8
ICC Supply current,
(per channel)
No load, Vout = VCC/2
650 850 nA
-40 °C < T< 85 °C
950
AC performance
GBP Gain bandwidth product
RL = 1 MΩ, CL = 60 pF
9
kHz
Fu Unity gain frequency
8.6
ϕm Phase margin
60
Degrees
Gm Gain margin
12
dB
SR Slew rate (10 % to 90 %) RL = 1 MΩ, CL = 60 pF,
Vout = 0.3 V to ((VCC+) - 0.3 V)
3
V/ms
en Equivalent input noise
voltage
f = 100 Hz
240
nV√Hz
f = 1 kHz
225
Electrical characteristics
10/33
DocID024317 Rev 3
Symbol Parameter Conditions Min. Typ. Max. Unit
∫en Low-frequency
peak-to-peak input noise Bandwidth: f = 0.1 to 10 Hz
8.1
µVpp
in Equivalent input noise
current
f = 100 Hz
0.18
fA√Hz
f = 1 kHz
3.5
trec Overload recovery time 100 mV from rail in comparator,
RL = 100 kΩ, VID = ±VCC,
-40 °C < T< 85 °C 30 µs
EMIRR Electromagnetic
interference rejection
ratio (3)
Vin = -10 dBm, f = 400 MHz
73
dB
Vin = -10 dBm, f = 900 MHz
88
Vin = -10 dBm, f = 1.8 GHz
80
Vin = -10 dBm, f = 2.4 GHz
80
Notes:
(1)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
(2)Guaranteed by design.
(3)Based on evaluations performed only in conductive mode.
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TSU101, TSU102, TSU104
Electrical characteristics
DocID024317 Rev 3
11/33
Figure 2: Supply current vs. supply voltage
Figure 3: Supply current vs. input common mode
voltage
Figure 4: Supply current in saturation mode
Figure 5: Input offset voltage distribution
Figure 6: Input offset voltage vs common mode voltage
Figure 7: Input offset voltage vs temperature at 3.3 V
supply voltage
00
2525
5050
7575
100100
125125
150150
175175
31003100
31253125
31503150
31753175
32003200
32253225
32503250
32753275
33003300
0.00.0
0.1
0.20.2
0.3
0.40.4
0.5
0.60.6
0.7
0.80.8
0.9
1.01.0
Vcc=3.3V
Follower configuration
Temperature
85°C/65°C/45°C/25°C/-5°C/-40°C
Input voltage(mV)
Icc (µA)
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Electrical characteristics
12/33
DocID024317 Rev 3
Figure 8: Input offset voltage temperature coefficient
distribution
Figure 9: Input bias current vs. temperature at
mid VICM
Figure 10: Input bias current vs. temperature at
low VICM
Figure 11: Input bias current vs. temperature at
high VICM
Figure 12: Output characteristics at 1.8 V supply voltage
Figure 13: Output characteristics at 3.3 V supply voltage
50 45 Saurce “1 vm- .zv E:35 w “‘30 0121545678910 Output Currant (mA) vam g 3‘ FoHowerconflgurauan‘T1290 5 3 1 Vcc:3 3v, Vm ham 13H m floflmvhnm 13H 1 E Vr\:VraH‘l:1DHz R\:10Mn,cx:1e F 5 012 E 01 m «a 007 n a D2 W o 75 u 51015202530354045505550 Time(ms) Signal Amplilude (V) Gawn:+11‘1UUkfl/1MQ‘V Vpp‘ T:25"C Vcc:3 3V‘ Vwcm=Vr\=1.65V RI=10MQ C\=169F a 1 2 3 4 Time (ms) Signal Amplitude (V) Fonower canfiguramn‘ T:25”C Vcc:3 3v, Vwcm Vr\:1 55v RMDMO, 0:1st n 25 so 75 100 125 150 Time(ms) Slew Rate [V/ms) =SODF 5V \o Vccro 5V SR ca‘cu‘ated lrom 10% lo 90% T:85“C 4.0 15 20 25 30 35 40 45 Vcc (V) 50 55
TSU101, TSU102, TSU104
Electrical characteristics
DocID024317 Rev 3
13/33
Figure 14: Output characteristics at 5 V supply voltage
Figure 15: Output voltage vs. input voltage close to the
rails
Figure 16: Output saturation with a sine wave on input
Figure 17: Desaturation time
Figure 18: Phase reversal free
Figure 19: Slew rate vs. supply voltage
00
2525
5050
7575
100100
125125
150150
175175
31003100
31253125
31503150
31753175
32003200
32253225
32503250
32753275
33003300
00
2525
50
50
75
75
100
100
125125
150
150
175175
3100
3100
3125
3125
3150
3150
3175
3175
32003200
32253225
3250
3250
3275
3275
33003300
Vcc=3.3V
Followerconfiguration
Temperature
85°C/65°C/45°C/25°C/-5°C/-40°C
Output voltage (mV)
Input voltage (mV)
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Electrical characteristics
14/33
DocID024317 Rev 3
Figure 20: Output swing vs. input signal frequency
Figure 21: Triangulation of a sine wave
Figure 22: Large signal response at 3.3 V supply
voltage
Figure 23: Small signal response at 3.3 V supply voltage
Figure 24: Overshoot vs. capacitive load at 3.3 V supply
voltage
Figure 25: Phase margin vs. capacitive load at 3.3 V
supply voltage
za 1 Feedback 1M9 1a v:c:3 3V,V1cm:1.65V,T:ZS°C ‘ Ga 5 RI: 0M9, 0:15pF, Vr\:V:d2 45 an 15 mp 150 12a Vicm (V) a; a 30 5 g n 3;, a a 3 a a an 2 o '5 Feedback min/47w (”,1 reun- Feedback: 100141 790 ‘ ,30 Vcc 1.8V,V1cm=0.9\/ 420 um, CI=EDpF, Vrl=Vcc/2 "5° ,1 m m mu 1000 1am Frequency (Hz) Quinn“ (“1) 1am 1am 150 15a 12a 12a so 917 so so a so 9 E at; r E y E V E 0 § E a I? m , m , o 30 g 0 30 g , so , so go so 55v m Vcc=5v, V1cm=2.5V m G:101(10kfl/1M§2) m G 101(10kQ/1Mfl) 45D R\:10M§L c1:eopF, Vr1:Vcc/z OMQ,C éOpF, Vrl:Vcc/2 Jan Aan mm 1mm 10mm 117 Frequency (ny Frequenny (H1) 10 9 5 \k 7 ’i‘ s 7 if A z 5 5 Vcc=3 3v, ii A. Ga1n101‘ mm a Recummended res1smrm ‘3 A R1=10M01 g mace naweenme ompm u T:25“C 0! me up amp and me 3 Measured 3120115 v 3 av v 155‘, m: 1 mm: 2 FuHuwerconflgurauan 1 0 10“ oo 05 1o 15 20 25 an
TSU101, TSU102, TSU104
Electrical characteristics
DocID024317 Rev 3
15/33
Figure 26: Bode diagram for different feedback values
Figure 27: Bode diagram at 1.8 V supply voltage
Figure 28: Bode diagram at 3.3 V supply voltage
Figure 29: Bode diagram at 5 V supply voltage
Figure 30: Gain bandwidth product vs. input common
mode voltage
Figure 31: In-series resistor (Riso) vs. capacitive load
ompm voltage nulse density(nV/VH1) a a 1000 100 4.: o 100 Vcc=1 av Fauower conflgurauon T:25"C 1000 Frequency (H1) 1 0000 100000 Outputvnltage noise densily [nVNHz] c; o o 1000 100 o o V00:3.3V FaHower conflgurahon 1:250: V1cm=1 65V 100 1000 Frequency (Hz) 1 0000 100000 100 1k 100 Frequency 1ny 0 10 :10 :1: E Vcc:5v 5 FoHower conflgurauon A g T=25"C 3 g 1000 1 .5 V1cm=25V g . = .,. e -— E E 4 ‘ 5 m 100 7 2 Q Vcc=3V‘ Vrcm:1 65V 2 Bandpassmer 011121010112 5 T:25"C E- = o 10 10 100 1000 10000 100000 Frequency (Hz) 140 140 120 forum _ n17 0 7.? 12° 3 73117313 3 e z 100 ‘ 100 g E u -= e a.) .. so .. _ 3 3 3 so 3 60 g ‘0 E 40 2° ° 20 100 1K 10K Frequency [H11
Electrical characteristics
16/33
DocID024317 Rev 3
Figure 32: Noise at 1.8 V supply voltage in follower
configuration
Figure 33: Noise at 3.3 V supply voltage in follower
configuration
Figure 34: Noise at 5 V supply voltage in follower
configuration
Figure 35: Noise amplitude on 0.1 to 10 Hz frequency
range
Figure 36: Channel separation on TSU102
Figure 37: Channel separation on TSU104
TSU101, TSU102, TSU104
Application information
DocID024317 Rev 3
17/33
4 Application information
4.1 Operating voltages
The TSU101, TSU102, and TSU104 series of amplifiers can operate from 1.5 V to 5.5 V.
Their parameters are fully specified at 1.8 V, 3.3 V, and 5 V supply voltages and are very
stable in the full VCC range. Additionally, main specifications are guaranteed on the
industrial temperature range from -40 to 85 ° C.
4.2 Rail-to-rail input
The TSU101, TSU102, and TSU104 series is built with two complementary PMOS and
NMOS input differential pairs. Thus, these devices have a rail-to-rail input, and the input
common mode range is extended from (VCC-) - 0.1 V to (VCC+) + 0.1 V.
The devices have been designed to prevent phase reversal behavior.
4.3 Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset
variation related to the offset value measured at 25 °C. The operational amplifier is one of
the main circuits of the signal conditioning chain, and the amplifier input offset is a major
contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated
during production at application level. The maximum input voltage drift over temperature
enables the system designer to anticipate the effects of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
with T = -40 °C and 85 °C.
The datasheet maximum value is guaranteed by measurements on a representative
sample size ensuring a Cpk (process capability index) greater than 2.
V
io
Tmax V
io
T( ) V
io
25
()
T 25 °C
=°C
Application information
18/33
DocID024317 Rev 3
4.4 Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum
junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2.
Equation 2
Where:
AFV is the voltage acceleration factor
b is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in
Equation 3.
Equation 3
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
k is the Boltzmann constant (8.6173 x 10-5 eVk-1)
TU is the temperature of the die when VU is used (°K)
TS is the temperature of the die under temperature stress (°K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and
the temperature acceleration factor (Equation 4).
Equation 4
AF is calculated using the temperature and voltage defined in the mission profile of the
product. The AF value can then be used in Equation 5 to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
Equation 5
AFVeβV
S
V
U
( )
.
=
A
FT
e
E
a
k
------ 1
T
U
1
T
S
=
.
A
F
A
FT
A
FV
×=
Months A
F
1000 h× 12 months 24 h365.25 days×
()×=/
TSU101, TSU102, TSU104
Application information
DocID024317 Rev 3
19/33
To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined
as a function of the maximum operating voltage and the absolute maximum rating
(as recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at
different measurement conditions (see Equation 6).
Equation 6
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is
obtained using the ratio of the Vio (input offset voltage value) drift over the square root of
the calculated number of months (Equation 7).
Equation 7
where Vio drift is the measured drift value in the specified test conditions after 1000 h stress
duration.
4.5 Schematic optimization aiming for nanopower
To benefit from the full performance of the TSU10 series, the impedances must be
maximized so that current consumption is not lost where it is not required.
For example, an aluminum electrolytic capacitance can have significantly high leakage.
This leakage may be greater than the current consumption of the op-amp. For this reason,
ceramic type capacitors are preferred.
For the same reason, big resistor values should be used in the feedback loop. However,
there are three main limitations to be considered when choosing a resistor.
1. When the TSU10x series is used with a sensor: the resistance connected between the
sensor and the input must remain much higher than the impedance of the sensor
itself.
2. Noise generated: a 100 kΩ resistor generates 40 nV/√Hz, a bigger resistor value
generates even more noise.
3. Leakage on the PCB: leakage can be generated by moisture. This can be improved by
using a specific coating process on the PCB.
VCC maxVop with Vicm VCC 2= = /
V
io
V
io
drift
month s( )
=
Application information
20/33
DocID024317 Rev 3
4.6 PCB layout considerations
For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible
to the power supply pins.
Minimizing the leakage from sensitive high impedance nodes on the inputs of the TSU10x
series can be performed with a guarding technique. The technique consists of surrounding
high impedance tracks by a low impedance track (the ring). The ring is at the same
electrical potential as the high impedance node.
Therefore, even if some parasitic impedance exists between the tracks, no leakage current
can flow through them as they are at the same potential (see Figure 38: "Guarding on the
PCB").
Figure 38: Guarding on the PCB
4.7 Using the TSU10x series with sensors
The TSU10x series has MOS inputs, thus input bias currents can be guaranteed down to
5 pA maximum at ambient temperature. This is an important parameter when the
operational amplifier is used in combination with high impedance sensors.
The TSU101, TSU102, and TSU104 series is perfectly suited for trans-impedance
configuration as shown in Figure 39: "Trans-impedance amplifier schematic". This
configuration allows a current to be converted into a voltage value with a gain set by the
user. It is an ideal choice for portable electrochemical gas sensing or photo/UV sensing
applications. The TSU10x series, using trans-impedance configuration, is able to provide a
voltage value based on the physical parameter sensed by the sensor.
l—‘— Sensor e‘emmchemma‘ nnmomoae/w J. v r27 we“ fix VreH VreVZ
TSU101, TSU102, TSU104
Application information
DocID024317 Rev 3
21/33
Electrochemical gas sensors
The output current of electrochemical gas sensors is generally in the range of tens of nA to
hundreds of µA. As the input bias current of the TSU101, TSU102, and TSU104 is very low
(see Figure 9, Figure 10, and Figure 11) compared to these current values, the TSU10x
series is well adapted for use with the electrochemical sensors of two or three electrodes.
Figure 40: "Potentiostat schematic using the TSU101 (or TSU102)" shows a potentiostat
(electronic hardware required to control a three-electrode cell) schematic using the
TSU101, TSU102, and TSU104. In such a configuration, the devices minimize leakage in
the reference electrode compared to the current being measured on the working electrode.
Figure 39: Trans-impedance amplifier schematic
Figure 40: Potentiostat schematic using the TSU101 (or TSU102)
15mm 6%
Application information
22/33
DocID024317 Rev 3
4.8 Fast desaturation
When the TSU101, TSU102, and TSU104 operational amplifiers go into saturation mode,
they take a short period of time to recover, typically thirty microseconds. When recovering
after saturation, the TSU10x series does not exhibit any voltage peaks that could generate
issues (such as false alarms) in the application (see Figure 17). This is because the
internal gain of the amplifier decreases smoothly when the output signal gets close to the
VCC+ or VCC- supply rails (see Figure 15 and Figure 16).
Thus, to maintain signal integrity, the user should take care that the output signal stays at
100 mV from the supply rails.
With a trans-impedance schematic, a voltage reference can be used to keep the signal
away from the supply rails.
4.9 Using the TSU10x series in comparator mode
The TSU10x series can be used as a comparator. In this case, the output stage of the
device always operates in saturation mode. In addition, Figure 4 shows the current
consumption is not bigger and even decreases smoothly close to the rails. The TSU101,
TSU102, and TSU104 are obviously operational amplifiers and are therefore optimized to
be used in linear mode. We recommend to use the TS88 series of nanopower comparators
if the primary function is to perform a signal comparison only.
4.10 ESD structure of TSU10x series
The TSU101, TSU102, and TSU104 are protected against electrostatic discharge (ESD)
with dedicated diodes (see Figure 41: "ESD structure"). These diodes must be considered
at application level especially when signals applied on the input pins go beyond the power
supply rails (VCC+ or VCC-).
Figure 41: ESD structure
Current through the diodes must be limited to a maximum of 10 mA as stated in Table 1:
"Absolute maximum ratings (AMR)". A serial resistor or a Schottky diode can be used on
the inputs to improve protection but the 10 mA limit of input current must be strictly
observed.
TSU101, TSU102, TSU104
Package information
DocID024317 Rev 3
23/33
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Fa? mm a W b T; w W if < \kv‘="" h="" j="" \.="">
Package information
24/33
DocID024317 Rev 3
5.1 SC70-5 (or SOT323-5) package information
Figure 42: SC70-5 (or SOT323-5) package outline
Table 6: SC70-5 (or SOT323-5) mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.80
1.10 0.315
0.043
A1
0.10
0.004
A2 0.80 0.90 1.00 0.315 0.035 0.039
b 0.15
0.30 0.006
0.012
c 0.10
0.22 0.004
0.009
D 1.80 2.00 2.20 0.071 0.079 0.087
E 1.80 2.10 2.40 0.071 0.083 0.094
E1 1.15 1.25 1.35 0.045 0.049 0.053
e
0.65
0.025
e1
1.30
0.051
L 0.26 0.36 0.46 0.010 0.014 0.018
<
SEATING PLANE
GAUGE PLANE
DIMENSIONS IN MM
SIDE VIEW
TOP VIEW
COPLANAR LEADS
TSU101, TSU102, TSU104
Package information
DocID024317 Rev 3
25/33
5.2 SOT23-5 package information
Figure 43: SOT23-5 package outline
Table 7: SOT23-5 mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.90 1.20 1.45 0.035 0.047 0.057
A1
0.15
0.006
A2 0.90 1.05 1.30 0.035 0.041 0.051
B 0.35 0.40 0.50 0.014 0.016 0.020
C 0.09 0.15 0.20 0.004 0.006 0.008
D 2.80 2.90 3.00 0.110 0.114 0.118
D1
1.90
0.075
e
0.95
0.037
E 2.60 2.80 3.00 0.102 0.110 0.118
F 1.50 1.60 1.75 0.059 0.063 0.069
L 0.10 0.35 0.60 0.004 0.014 0.024
K 0 degrees
10 degrees 0 degrees
10 degrees
pw ‘ wuzxAm a. [mu mm mm? ( j wws 5qu wzw WW F—W 5 La m ‘ “I ., m- j/// W w swam wzw
Package information
26/33
DocID024317 Rev 3
5.3 DFN8 2x2 package information
Figure 44: DFN8 2x2 package outline
Table 8: DFN8 2x2 mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.70 0.75 0.80 0.028 0.030 0.031
A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.15 0.20 0.25 0.006 0.008 0.010
D
2.00
0.079
E
2.00
0.079
e
0.50
0.020
L 0.045 0.55 0.65 0.018 0.022 0.026
N 8
NOLlVDHUNEEH L Md o-l MW QH'H F1 SEATING PLANE m 3mm 3mm
TSU101, TSU102, TSU104
Package information
DocID024317 Rev 3
27/33
5.4 MiniSO8 package information
Figure 45: MiniSO8 package outline
Table 9: MiniSO8 mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A
1.1
0.043
A1 0
0.15 0
0.006
A2 0.75 0.85 0.95 0.030 0.033 0.037
b 0.22
0.40 0.009
0.016
c 0.08
0.23 0.003
0.009
D 2.80 3.00 3.20 0.11 0.118 0.126
E 4.65 4.90 5.15 0.183 0.193 0.203
E1 2.80 3.00 3.10 0.11 0.118 0.122
e
0.65
0.026
L 0.40 0.60 0.80 0.016 0.024 0.031
L1
0.95
0.037
L2
0.25
0.010
k
ccc
0.10
0.004
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Package information
28/33
DocID024317 Rev 3
5.5 QFN16 3x3 package information
Figure 46: QFN16 3x3 mm package outline
The exposed pad is not internally connected and can be set to ground.
TSU101, TSU102, TSU104
Package information
DocID024317 Rev 3
29/33
Table 10: QFN16 3x3 mm mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.80 0.90 1.00 0.031 0.035 0.039
A1 0
0.05 0
0.002
A3
0.20
0.008
b 0.18
0.30 0.007
0.012
D 2.90 3.00 3.10 0.114 0.118 0.122
D2 1.50
1.80 0.059
0.071
E 2.90 3.00 3.10 0.114 0.118 0.122
E2 1.50
1.80 0.059
0.071
e
0.50
0.020
L 0.30
0.50 0.012
0.020
Figure 47: QFN16 3x3 mm recommended footprint
D E \ ‘ A2 , : :A \ i I 2! a7—2 A1 ’5 same PLANE 0.25 mm GAGE PLANE D7 \ PW 1 \DENT‘F‘CAT‘ON L1
Package information
30/33
DocID024317 Rev 3
5.6 TSSOP14 package information
Figure 48: TSSOP14 package outline
Table 11: TSSOP14 mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A
1.20
0.047
A1 0.05
0.15 0.002 0.004 0.006
A2 0.80 1.00 1.05 0.031 0.039 0.041
b 0.19
0.30 0.007
0.012
c 0.09
0.20 0.004
0.0089
D 4.90 5.00 5.10 0.193 0.197 0.201
E 6.20 6.40 6.60 0.244 0.252 0.260
E1 4.30 4.40 4.50 0.169 0.173 0.176
e
0.65
0.0256
L 0.45 0.60 0.75 0.018 0.024 0.030
L1
1.00
0.039
k
aaa
0.10
0.004
TSU101, TSU102, TSU104
Ordering information
DocID024317 Rev 3
31/33
6 Ordering information
Table 12: Order codes
Order code Temperature range Package Packing Marking
TSU101ICT
-40 °C to 85 °C
SC70-5
Tape and reel
K22
TSU101ILT SΟΤ23-5 K160
TSU101RICT SC70-5 K24
TSU101RILT SΟΤ23-5 K169
TSU102IQ2T DFN8 2x2 K24
TSU102IST MiniSO8 K160
TSU104IQ4T QFN16 3x3 K160
TSU104IPT TSSOP14 TSU104I
Revision history
32/33
DocID024317 Rev 3
7 Revision history
Table 13: Document revision history
Date Revision Changes
16-Apr-2013 1 Initial release
02-Jul-2013 2
Added the TSU102 and TSU104 devices and updated
the datasheet accordingly.
Added the silhouettes, pin connections, and package
information for DFN8 2x2, MiniSO8, QFN16 3x3, and
TSSOP14.
Added Figure 36 and Figure 37
04-Sep-2015 3
Updated title of Figure 31
Replaced QFN16 3x3 package information (outline,
mechanical data, and footprint).
TSU101, TSU102, TSU104
DocID024317 Rev 3
33/33
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© 2015 STMicroelectronics All rights reserved

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