MCP2035 Datasheet by Microchip Technology

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2012 Microchip Technology Inc. DS22304A-page 1
MCP2035
Device Features:
Single Analog Input Pin for Signal Detection
High Input Detection Sensitivity (3 mVPP
, typical)
High Modulation Depth Sensitivity (as low as 8%)
Three Output Type Selections:
- Demodulated Data
- Carrier Clock
- Received Signal Strength Indicator (RSSI)
Input Carrier Frequency: 125 kHz, typical
Input Data Rate: 10 Kbps, maximum
8 Internal Configuration Registers
Bidirectional Transponder Communication via the
same input pin (LF talk-back)
Programmable Antenna Tuning Capacitance
(up to 63 pF, 1 pF/step)
Programmable Output Enable Filter
Low Standby Current: 2 µA, typical
Low Operating Current: 10 µA, typical
Serial Peripheral Interface (SPI) with external
devices
Industrial and Extended Temperature Range:
-40°C to +85°C (Industrial)
Typical Applications:
BodyCom Applications
Security Industry Applications
Automotive Industry Applications
Description:
The MCP2035 is a single-channel, stand-alone Analog
Front-End (AFE) device for low-frequency (LF) signal
detection and low-power short range transponder
applications, such as BodyCom communications.
The device can detect an input signal with amplitude as
low as ~1 mVPP
, and can demodulate an amplitude-
modulated input signal with as low as 8% modulation
depth. The device can also transmit data (LF talk-back)
by clamping and unclamping the input LC antenna
voltage.
The device can output demodulated data, carrier clock
or RSSI current, depending on the output-type
selection configuration register bit settings. The
demodulated data and carrier clock outputs are
available on the LFDATA pin, while the RSSI output is
available on the RSSI pin. The RSSI current output is
linearly proportional to the input signal strength.
The device has programmable internal tuning
capacitors for the input channel. The user can program
the input tuning capacitors up to 63 pF, 1 pF per step.
The internal tuning capacitors can be used effectively
for fine-tuning of the external LC resonant circuit.
The device has eight volatile internal configuration
registers for dynamic configurations of the device
operation on-the-fly. All registers are readable and
programmable using the serial SPI commands, except
the read-only STATUS register.
The device is optimized for very low current
consumption and has various battery-saving low-
power modes (Sleep, Standby, Active).
This device is available in a 14-pin TSSOP package.
Package Type:
1
2
3
4
5
6
7
14
13
12
9
11
10
8
NC
LCCOM
LCX
VSS
LFDATA/
VDD
NC
NC
VSS
CS
SCLK/ALERT
RSSI
NC
VDD
CCLK/SDIO
MCP2035
TSSOP
Analog Front-End Device for BodyCom Applications
MCP2035
DS22304A-page 2 2012 Microchip Technology Inc.
NOTES:
cs ALERT E ALERT R
2012 Microchip Technology Inc. DS22304A-page 3
MCP2035
1.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +6.5V
Voltage on all other pins with respect to VSS ................................................................................. -0.3V to (VDD + 0.3V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Maximum LC Input Voltage (LCX) loaded, with device....................................................................................... 10.0 VPP
Maximum LC Input Voltage (LCX) unloaded, without device............................................................................ 700.0 VPP
Maximum Input Current (rms) into device (LCX Input Channel) .............................................................................10 mA
Human Body ESD rating......................................................................................................................2000 (minimum) V
Machine Model ESD rating ....................................................................................................................200 (minimum) V
Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
DC CHARACTERISTICS
Electrical Specifications: Standard Operating Conditions (unless otherwise stated),
Operating temperature: -40C TA +85C, LCX Input Signal: Sinusoidal 300 mVPP, Carrier Frequency = 125 kHz,
LCCOM connected to VSS, Bits <3:1> of Configuration Register 0: LCXEN = 0, LCZEN = LCYEN = 1.
Parameters Sym. Min. Typ.(2)Max. Units Conditions
Supply Voltage VDD 2.0 3.0 3.6 V
VDD Start Voltage to ensure
internal
Power-on Reset signal
VPOR ——1.8V
Modulation Transistor-on
Resistance
RM 50 100 VDD =3.0V
Active Current (detecting signal)
1 LC Input Channel (LCX) is
Receiving Signal
IACT —10µACS=V
DD
Input = Continuous Wave (CW)
Amplitude = 300 mVPP
LCX input channel is enabled.
Standby Current
(wait to detect signal)
ISTDBY —2 5µACS=V
DD; ALERT =V
DD
LCX input channel is enabled.
Sleep Current ISLEEP —0.2 1 µACS=V
DD; ALERT =V
DD
Analog Input Leakage
Current on LCX and LCCOM
pins
IAIL ——AV
DD =3.6V, V
SS VIN 1V with
respect to ground. Internal
tuning capacitors are switched
off, tested in Sleep mode
Digital Input Low Voltage VIL VSS —0.3V
DD V SCLK, SDI, CS
Digital Input High Voltage VIH 0.8 VDD —V
DD V SCLK, SDI, CS
Note 1: These parameters are characterized but not tested.
2: Data in “Typ.” column is at 3.0V, +25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
3: Negative current is defined as current sourced by the pin.
ALERT ALERT
MCP2035
DS22304A-page 4 2012 Microchip Technology Inc.
Digital Input Leakage Current
SDI, SCLK, CS (Note 3)
IIL ——AV
DD = 3.6V
VSS VPIN VDD
VPIN VDD
Digital Output Low Voltage
ALERT, LFDATA/SDIO
VOL ——V
SS +0.4 V Analog Front-End section
IOL = 1.0 mA, VDD = 2.0V
Digital Output High Voltage
ALERT, LFDATA/SDIO
VOH VDD - 0.5 V IOH = -400 A, VDD = 2.0V
Digital Input Pull-Up Resistor
CS, SCLK
RPU 50 200 350 kVDD =3.6V
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Standard Operating Conditions (unless otherwise stated),
Operating temperature: -40C TA +85C, LCX Input Signal: Sinusoidal 300 mVPP, Carrier Frequency = 125 kHz,
LCCOM connected to VSS, Bits <3:1> of Configuration Register 0: LCXEN = 0, LCZEN = LCYEN = 1.
Parameters Sym. Min. Typ.(2)Max. Units Conditions
Note 1: These parameters are characterized but not tested.
2: Data in “Typ.” column is at 3.0V, +25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
3: Negative current is defined as current sourced by the pin.
2012 Microchip Technology Inc. DS22304A-page 5
MCP2035
AC CHARACTERISTICS
Electrical Specifications: Standard Operating Conditions (unless otherwise stated), Supply Voltage: 2.0V VDD 3.6V, Operating temperature: -40°C TA +85°C,
LCCOM connected to VSS, LCX Input Signal: Sinusoidal 300 mVPP
, Carrier Frequency = 125 kHz, Bits <3:1> of Configuration Register 0: LCXEN = 0, LCZEN =
LCYEN = 1.
Parameters Sym. Min. Typ(2)Max. Units Conditions
Input Sensitivity VSENSE 13.0 6mV
PP VDD = 3.0V
Output enable filter disabled
AGCSIG = 0;
MODMIN = 00
(33% modulation depth setting)
Input = Continuous Wave (CW)
Output = Logic level transition from low-to-high at
sensitivity level for CW input.
Coil de-Q’ing Voltage - RF Limiter (RFLM)
must be active
VDE_Q 3— 5 VV
DD = 3.0V, Force IIN = 5 A
(worst case)
RF Limiter Turn-on Resistance at LCX pin RFLM — 300 700 VDD = 2.0V, VIN = 8 VDC
Sensitivity Reduction SADJ —0 —dBV
DD = 3.0V
No sensitivity reduction selected
Maximum reduction selected
Monotonic increment in attenuation value from setting
= 0000 to 1111 by design
—-30 — dB
Minimum Modulation Depth
60% setting VIN_MOD 60 84 % VDD = 3.0V
See Section 5.20 “Minimum Modulation Depth
Requirement for Input Signal”.
See Modulation Depth Definition in Figure 5-5.
33% setting 33 49 %
14% setting 14 26 %
8% 8 %
Carrier frequency FCARRIER — 125 kHz
Input modulation frequency FMOD 10 kHz Input data rate with NRZ data format.
VDD = 3.0V
Minimum modulation depth setting = 33%
Input conditions:
Amplitude = 300 mVPP
Modulation depth = 100%
Note 1: Parameter is characterized but not tested.
2: Data in “Typ.” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
3: Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF).
4: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
TAGC . TPAGC
MCP2035
DS22304A-page 6 2012 Microchip Technology Inc.
LCX Tuning Capacitor CTUNX —0 —pFV
DD = 3.0V,
Config. Reg. 1,
bits <6:1> Setting = 000000
44 59 82 pF 63 pF ±30%
Config. Reg. 1, bits <6:1> Setting = 111111
63 steps, approx. 1 pF/step
Monotonic increment in capacitor value from setting =
000000 to 111111 by design
Q of Internal Input Tuning
Capacitors
Q_C 50(1)——
Demodulator Charge Time
(delay time of demodulated
output to rise)
TDR —50 — µsV
DD = 3.0V
Minimum modulation depth setting = 33%
Input conditions:
Amplitude = 300 mVPP
Modulation depth = 100%
Demodulator Discharge Time (delay time of
demodulated
output to fall)
TDF —50 — µsV
DD = 3.0V
MOD depth setting = 33%
Input conditions:
Amplitude = 300 mVPP
Modulation depth = 100%
Rise time of LFDATA TRLFDATA —0.5 — µsV
DD 3.0V. Time is measured from 10% to 90% of
amplitude
Fall time of LFDATA TFLFDATA —0.5 — µsV
DD 3.0V
Time is measured from 10% to 90% of amplitude
Automatic Gain Control (AGC) stabilization
time (TAGC + TPAGC)
TSTAB 4— —ms
AGC initialization time TAGC —3.5 — ms
High time after AGC initialization time TPAGC —62.5 — µs
AC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Standard Operating Conditions (unless otherwise stated), Supply Voltage: 2.0V VDD 3.6V, Operating temperature: -40°C TA +85°C,
LCCOM connected to VSS, LCX Input Signal: Sinusoidal 300 mVPP
, Carrier Frequency = 125 kHz, Bits <3:1> of Configuration Register 0: LCXEN = 0, LCZEN =
LCYEN = 1.
Parameters Sym. Min. Typ(2)Max. Units Conditions
Note 1: Parameter is characterized but not tested.
2: Data in “Typ.” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
3: Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF).
4: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
FCARR‘ER
2012 Microchip Technology Inc. DS22304A-page 7
MCP2035
Gap time after AGC stabilization time TGAP 200 — µs
Time element of pulse TE100 µs Minimum pulse width
Time from exiting Sleep or POR to being
ready to receive signal
TRDY ——50
(1)ms
Minimum time AGC level must be held after
receiving AGC Preserve command
TPRES 5(1) ms AGC level must not change more than 10% during
TPRES
Internal RC oscillator frequency FOSC 27 32 35.5 kHz Internal clock trimmed at 32 kHz during test
Inactivity Timer time-out TINACT 13.5 16 17.75 ms 512 cycles of RC oscillator @ FOSC
Alarm Timer time-out TALARM 27 32 35.5 ms 1024 cycles of RC oscillator @ FOSC
Input Resistance (LCX) RIN —800
(1)—kLCCOM grounded, VDD = 3V, FCARRIER = 125 kHz
Input Parasitic Capacitance (LCX) CIN —24
(1) pF LCCOM grounded, VDD = 3V, FCARRIER = 125 kHz
Minimum output enable filter high time
OEH (Bits Config0<8:7>)
01 = 1 ms TOEH 32 (~1 ms) — —
clock
count
RC oscillator = FOSC
(see FOSC specification
for variations).
Viewed from the pin input:
(Note 3)
10 = 2 ms 64 (~2 ms) — —
11 = 4 ms 128 (~4 ms) — —
00 = Filter Disabled — —
Minimum output enable filter low time
OEL (Bits Config0<6:5>)
00 = 1 ms TOEL 32 (~1 ms)
clock
count
RC oscillator = FOSC
Viewed from the pin input:
(Note 4)
01 = 1 ms 32 (~1 ms)
10 = 2 ms 64 (~2 ms)
11 = 4 ms 128 (~4 ms)
AC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Standard Operating Conditions (unless otherwise stated), Supply Voltage: 2.0V VDD 3.6V, Operating temperature: -40°C TA +85°C,
LCCOM connected to VSS, LCX Input Signal: Sinusoidal 300 mVPP
, Carrier Frequency = 125 kHz, Bits <3:1> of Configuration Register 0: LCXEN = 0, LCZEN =
LCYEN = 1.
Parameters Sym. Min. Typ(2)Max. Units Conditions
Note 1: Parameter is characterized but not tested.
2: Data in “Typ.” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
3: Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF).
4: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
MCP2035
DS22304A-page 8 2012 Microchip Technology Inc.
Maximum output enable filter period
OEH OEL TOEH TOEL
01 00 = 1 ms 1 ms (Filter 1) TOET 96 (~3 ms)
clock
count
RC oscillator = FOSC
01 01 = 1 ms 1 ms (Filter 1) 96 (~3 ms)
01 10 = 1 ms 2 ms (Filter 2) 128 (~4 ms)
01 11 = 1 ms 4 ms (Filter 3 192 (~6 ms)
10 00 = 2 ms 1 ms (Filter 4) 128 (~4 ms)
10 01 = 2 ms 1 ms (Filter 4) 128 (~4 ms)
10 10 = 2 ms 2 ms (Filter 5) 160 (~5 ms)
10 11 = 2 ms 4 ms (Filter 6) 250 (~8 ms)
11 00 = 4 ms 1 ms (Filter 7) 192 (~6 ms)
11 01 = 4 ms 1 ms (Filter 7) 192 (~6 ms)
11 10 = 4 ms 2 ms (Filter 8) 256 (~8 ms)
11 11 = 4 ms 4 ms (Filter 9) 320 (~10 ms)
00 XX = Filter Disabled — — LFDATA output appears as long as input signal level is
greater than VSENSE.
RSSI current output IRSSI —0.65 2 µAV
IN = 37 mVPP
6 12 20.3 µA VIN = 370 mVPP
100 µA VDD = 3.0V, VIN = 0 to 4 VPP
Linearly increases with input signal amplitude.
Tested at VIN = 37 mVPP
, 100 mVPP
, and 370 mVPP
at +25ºC.
RSSI current linearity ILRRSSI -15 15 % Tested at room temperature only (see Equation 5-1
and Figure 5-7 for test method).
AC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Standard Operating Conditions (unless otherwise stated), Supply Voltage: 2.0V VDD 3.6V, Operating temperature: -40°C TA +85°C,
LCCOM connected to VSS, LCX Input Signal: Sinusoidal 300 mVPP
, Carrier Frequency = 125 kHz, Bits <3:1> of Configuration Register 0: LCXEN = 0, LCZEN =
LCYEN = 1.
Parameters Sym. Min. Typ(2)Max. Units Conditions
Note 1: Parameter is characterized but not tested.
2: Data in “Typ.” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
3: Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF).
4: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).
2012 Microchip Technology Inc. DS22304A-page 9
MCP2035
SPI TIMING
Electrical Specifications: Standard Operating Conditions (unless otherwise stated),
Supply Voltage: 2.0V VDD 3.6V, Operating temperature: -40°C TA +85°C,
LCX Input Signal: Sinusoidal 300 mVPP
, Carrier Frequency: 125 kHz, LCCOM connected to VSS
Parameters Sym Min Typ(1)Max Units Conditions
SCLK Frequency FSCLK —— 3MHz
CS fall to first SCLK edge
setup time
TCSSC 100 — ns
SDI setup time TSU 30 — ns
SDI hold time THD 50 — ns
SCLK high time THI 150 — ns
SCLK low time TLO 150 — ns
SDO setup time TDO ——150ns
SCLK last edge to CS rise
setup time
TSCCS 100 — ns
CS high time TCSH 500 — ns
CS rise to SCLK edge setup time TCS1 50 — ns
SCLK edge to CS fall setup time TCS0 50 ns SCLK edge when CS is high
Rise time of SPI data
(SPI Read command)
TRSPI —10nsV
DD 3.0V; time is measured
from 10% to 90% of amplitude
Fall time of SPI data
(SPI Read command)
TFSPI —10nsV
DD 3.0V; time is measured
from 90% to 10% of amplitude
Note 1: Data in “Typ.” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 2.0V to 3.6V, VSS = GND.
Parameters Symbol Min Typical Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 +85 °C
Operating Temperature Range TA-40 +125 °C
Storage Temperature Range TA-65 +150 °C
Thermal Package Resistances
Thermal Resistance, 14L-TSSOP JA —100°C/W
MCP2035
DS22304A-page 10 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. DS22304A-page 11
MCP2035
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VDD = 3V, Carrier Frequency = 125 kHz, LCCOM = connected to VSS, TA = +25°C.
FIGURE 2-1: Typical Standby Current.
FIGURE 2-2: Typical Active Current.
FIGURE 2-3: Oscillator Frequency vs.
Temperature, VDD = 3.6V and 2.0V.
FIGURE 2-4: Oscillator Frequency
Histograms vs. Temperature, VDD = 2V.
FIGURE 2-5: Oscillator Frequency
Histograms vs. Temperature at VDD = 3V.
FIGURE 2-6: De-Q’ed Voltage vs.
Unloaded Coil Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
0.5
1
1.5
2
2.5
2 V
3 V
Current Draw (µA)
V
DD
(V)
Standby Current (LCX Channel Enabled)
+85
o
C
+25oC
-40oC
0
1
2
3
4
5
6
7
8
9
2 V
3 V
Current Draw (µA)
V
DD
(V)
Active Current (LCX Channel Enabled)
+85oC
+25oC
-40oC
29
30
31
32
33
34
35
-50 -25 0 25 50 75 100
125
Oscillator Frequency (kHz)
Temperature (°C)
Osc. Freq. @ VDD = 3.6V
Osc. Freq. @ VDD = 2.0V
0.0%
5.0%
10.0%
15.0%
20.0%
25.0%
30.0%
35.0%
40.0%
45.0%
50.0%
27
28
29
30
31
32
33
34
35
Percentage of Occurences (%)
Oscillator Frequency (kHz)
-40C
25C
85C
VDD = 2.0V
0.0%
5.0%
10.0%
15.0%
20.0%
25.0%
30.0%
35.0%
40.0%
45.0%
50.0%
27
28
29
30
31
32
33
34
35
Percentage of Occurences (%)
Oscillator Frequency (kHz)
-40C
25C
85C
VDD = 3.6V
0
2
4
6
8
10
12
0 200 400 600
800
De-Q'ed (Loaded) Coil Voltage
(VPP)
Unloaded Coil Voltage (VPP)
MCP2035
DS22304A-page 12 2012 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = 3V, Carrier Frequency = 125 kHz, LCCOM = connected to VSS.
FIGURE 2-7: Modulation Transistor-on
Resistance (+25°C).
FIGURE 2-8: Input Channel Sensitivity vs.
Bandwidth.
FIGURE 2-9: Typical RSSI Output Current
vs. Input Signal Strength.
FIGURE 2-10: Typical Tuned Capacitance
Value vs. Configuration Register Bit Setting
(VDD = 3V, Temperature = +25°C).
FIGURE 2-11: Typical Tuned Capacitance
Value vs. Configuration Register Bit Setting
(VDD = 3V, Temperature = -40°C).
FIGURE 2-12: Typical Tuned Capacitance
Value vs. Configuration Register Bit Setting
(VDD = 3V, Temperature = +85°C).
0
10
20
30
40
50
60
70
80
024
6
Ohms
V
DD
(V)
0
5
10
15
20
25
0 50 100 150 200 250 300 350 400
450
Sensitivity (mVPP)
Frequency (kHz)
0
20
40
60
80
100
120
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
RSSI (µA)
Input Voltage (V)
-40 C
+85 C
+25 C
0
10
20
30
40
50
60
70
0 204060
80
Capacitance (pF)
Bit Setting (Steps)
0
10
20
30
40
50
60
70
0204060
80
Capacitance (pF)
Bit Setting (steps)
0
10
20
30
40
50
60
70
0 204060
80
Capacitance (pF)
Bit Setting (Steps)
WWW
2012 Microchip Technology Inc. DS22304A-page 13
MCP2035
Note: Unless otherwise indicated, VDD = 3V, Carrier Frequency = 125 kHz, LCCOM = connected to VSS.
FIGURE 2-13: Examples of RSSI Output
Current Variations Between Device to Device at
Room Temperature.
FIGURE 2-14: Example of Typical TDR
Changes over Temperature.
Input Signal Condition: Amplitude = 300 mVPP
,
Modulation Depth = 100 %.
FIGURE 2-15: Example of Typical TDF
Changes over Temperature.
Input Signal Condition: Amplitude = 300 mVPP
,
Modulation Depth = 100 %.
0
10
20
30
40
50
60
70
80
024
6
RSSI Current (mA)
Input Voltage (V)
Device A
Device B
Device C
Device D
Note: Equal amplitude is applied to each
device.
0
10
20
30
40
50
60
70
80
90
100
85°C
25°C
-20°C
-40°C
T
DR
(µs)
Temperature (°C)
8%
14%
33%
60%
0
10
20
30
40
50
60
85°C
25°C
-20°C
-40°C
T
DF
(µs)
Temperature (°C)
8%
14%
33%
60%
A'1.06mV Chl 2.00v , M2.00ms ch41 soouv 500w A' 3.0!)!le .1.4va Ch] 2.00 V , M2.00mS Ch-I J' SOOHV 1.00mv
MCP2035
DS22304A-page 14 2012 Microchip Technology Inc.
2.1 Performance Plots
FIGURE 2-16: Input Sensitivity Example.
(a) Sensitivity = 1.06 mVPP
(b) Sensitivity = 3 mVPP
Demodulated output
Input signal
Demodulated output
Input signal
LOOmV MLOOmS C12 I L-IZmV g sep 2005 14:07:14
2012 Microchip Technology Inc. DS22304A-page 15
MCP2035
FIGURE 2-17: Typical AGC Initialization Time at Room Temperature (VDD = 3V).
Note: Ch2 is the input and Ch1 is the output (demodulated data appears after AGC Initialization time (TAGC)).
Output Enable Filter is disabled.
3| 1.0x Vert 0.01X Horz A: 2.0ms . @z —2.1ms Elm 2.00v 2.00v MS.00I11SCI11./' 1.84v C13 50.0mV ; ALERT ALERT
MCP2035
DS22304A-page 16 2012 Microchip Technology Inc.
FIGURE 2-18: ALERT Output Example: With No Parity Error and no 32 ms Alarm Timer Time-out.
Note: Ch3 is the input with correct Output Enable Filter timing.
Ch1 is the demodulated LFDATA output.
Ch2 is the ALERT pin output. It shows that the ALERT output pin maintains logic high if the input signal
meets the programmed filter timing requirement.
:I'IZ Zoom: 1.0X Vert 0.01X HOfZ A' 32.0ms , I 37.7!118 2.00v 2.00v MS.00ms|ChZ./' 1.76V 50.0an g I
2012 Microchip Technology Inc. DS22304A-page 17
MCP2035
FIGURE 2-19: ALERT Output Example: With 32 ms Alarm Timer Timed Out.
Note: The 32 ms Alarm Timer is enabled only if the Output Enable Filter is enabled.
Ch3 is the input signal with incorrect Output Enable Filter timing.
Ch1 is the demodulated LFDATA output. No output since the input filter is not matched.
Ch2 is the ALERT output.
The output shows that the logic level changes after 32 ms from the AGC initialization time (TAGC) if the input signal
does not meet the programmed filter timing requirement.
2.00V C12 1.00mV .00m5 C12 . 2mV 959p 2005 14:11:28
MCP2035
DS22304A-page 18 2012 Microchip Technology Inc.
FIGURE 2-20: Examples of Soft Inactivity Timer Time Out: This output is available only if the Output
Enable Filter is disabled.
Note: Ch2 is the input without modulation (i.e., noise).
Ch1 is the output at the LFDATA pin due to the 16 ms Soft Inactivity Timer time out. Note the 3.5 ms AGC initialization
time after the Soft Reset.
The cases shown above apply when the Output Filter is disabled.
(a) Output (Ch1):
Device repeats Soft
Reset after 16 ms,
Inactivity Timer has
timed out
(b) Input (Ch2):
Input has no
modulation
2012 Microchip Technology Inc. DS22304A-page 19
MCP2035
FIGURE 2-21: Examples of Clamp-On and Clamp-Off Commands and Changes in Coil Voltage.
Coil Voltage
Clock Pulses
Clamp On
Coil Voltage
Clock Pulses
Clamp Off
Command
Command
LCX
SCLK
SDI
LCX
SCLK
SDI
(Sh-3 Zoom: 1.0x Vert 0.02N Horz A' 13mV Ch1 2.00V , lesoms Ch-If SOmV 50.0mv CI1-| Zoom: 1.0x Vert 0.02X HOI‘Z Ch1 2.00V A M2.Snms Ch-IJ' snmv 50.0mv
MCP2035
DS22304A-page 20 2012 Microchip Technology Inc.
FIGURE 2-22: Example of Minimum Modulation Depth Setting: Modulation Depth of Input
Signal = 77%, Minimum Modulation Depth (MODMIN) Setting = 60%.
FIGURE 2-23: Example of Minimum Modulation Depth Setting: Modulation Depth of Input
Signal = 56%, Minimum Modulation Depth (MODMIN) Setting = 60%.
Demodulated output
Input signal with 77%
modulation depth
Demodulated output
Input signal with 56%
modulation depth
Note: There is no demodulated output since the modulation depth of the input signal is lower than the minimum
modulation depth setting. The device will have demodulated output if the Minimum Modulation Depth
option is set to 8%, 14%, or 33%.
Ch-l Zoom: 1.0x Vel't 0.02X HOI'Z A' 41mV Ch] 2.00V - N12.50n1s CIHJ' SOmV 50.0an Ch-U Zoom: 1.0x Vert 0.02N HOI‘Z A 7SmV , 36mV ChI 2.00V , MZSOms CI‘HJ' 25mv 50.0mV
2012 Microchip Technology Inc. DS22304A-page 21
MCP2035
FIGURE 2-24: Example of Minimum Modulation Depth Setting: Modulation Depth of Input
Signal = 42%, Minimum Modulation Depth (MODMIN) Setting = 33%.
FIGURE 2-25: Example of Minimum Modulation Depth Setting: Modulation Depth of Input
Signal = 14%, Minimum Modulation Depth (MODMIN) Setting = 14%.
Demodulated output
Input signal with 42%
modulation depth
Demodulated output
Input signal with 14%
modulation depth
‘ , x - mzvooms CIHJ‘ l7mV 50.0mv M2.00ms Ch-I J' 17mV 2.00m: Cl'I-I .r 1 run" fin 0"qu
MCP2035
DS22304A-page 22 2012 Microchip Technology Inc.
FIGURE 2-26: Examples of Output Enable Filters 1 through 3 (Wake-up Filters) and Demodulated
Outputs.
Filter 1
Output Enable
Filter Timing of
Input Signal
Configuration
Bit Settings
OEH OEL
TOEH = 1 ms
TOEL = 1 ms
TOET = 3 ms
01
or
01
00
01
Filter 2
Output Enable
Filter Timing of
Input Signal
Configuration Bit
Settings
OEH OEL
TOEH = 1 ms
TOEL = 2 ms
TOET = 4 ms
01 10
Filter 3
Output Enable
Filter Timing of
Input Signal
Configuration Bit
Settings
OEH OEL
TOEH = 1 ms
TOEL = 4 ms
TOET = 6 ms
01 11
I IM2.00ms 014 .r 17mv I A 4.12ms Izm: 2.00v | I I Mlooms 014 .r 17mv I 0.0mVV 6.08ms |2.2-lm: I I 2.00 v I , Ch-I .r 17mV (3'14 fi0.0ll‘lV
2012 Microchip Technology Inc. DS22304A-page 23
MCP2035
FIGURE 2-27: Examples of Output Enable Filters 4 through 6 (Wake-up Filters) and Demodulated
Outputs.
Filter 4
Output Enable
Filter Timing of
Input Signal
Configuration Bit
Settings
OEH OEL
TOEH = 2 ms
TOEL = 1 ms
TOET = 4 ms
10
or
10
00
01
Filter 5
Output Enable
Filter Timing of
Input Signal
Configuration Bit
Settings
OEH OEL
TOEH = 2 ms
TOEL = 2 ms
TOET = 5 ms
10 10
Filter 6
Output Enable
Filter Timing of
Input Signal
Configuration
Bit Settings
OEH OEL
TOEH = 2 ms
TOEL = 4 ms
TOET = 8 ms
10 11
Ch] 2.00v 2.00v I , Ch—l 510. omv I , CI'I-I 3‘0.omv 3,.oomv .o-uns 1.15m: M2.0Ims Ch-l J’ 17mv A' 6.08ms 12.2mm N12.00m Ch-I .r 17mv S.0-Ims 14.2mm
MCP2035
DS22304A-page 24 2012 Microchip Technology Inc.
FIGURE 2-28: Examples of Output Enable Filters 7 through 9 (Wake-up Filters) and Demodulated
Outputs.
Filter 7
Output Enable
Filter Timing of
Input Signal
Configuration Bit
Settings
OEH OEL
TOEH = 4 ms
TOEL = 1 ms
TOET = 6 ms
11
or
11
00
01
Filter 8
Output Enable
Filter Timing of
Input Signal
Configuration
Bit Settings
OEH OEL
TOEH = 4 ms
TOEL = 2 ms
TOET = 8 ms
11 10
Filter 9
Output Enable
Filter Timing of
Input Signal
Configuration Bit
Settings
OEH OEL
TOEH = 4 ms
TOEL = 4 ms
TOET = 10 ms
11 11
Ch-I Zoom: 5.00V 2.0x Vert Loomv' 0.0m Horz A' 2.70mV t .3-ImV M 2,00ms Cl‘I-I f 114an CIH Zoom: 5.00V 2.0x Vel't LOOmVV 0.01X HOI'Z A 2.70nIV ml‘llnq M 2.00ms CH4 1' 1.2-ImV
2012 Microchip Technology Inc. DS22304A-page 25
MCP2035
FIGURE 2-29: Input Signal and Demodulated Output When the Output Enable Filter is Disabled.
FIGURE 2-30: Input Signal and Demodulator Output When Output Enable Filter is Enabled and Input
Meets Filter Timing Requirements.
Input Signal
LFDATA
Note: Demodulated output is available immediately after AGC initialization.
Output
Input Signal
LFDATA
Note: Demodulated output is available only if the incoming signal meets the enable filter timing criteria that is
defined in the Configuration Register 0 (Register 5-1). If the criteria is met, the output is available after the
low timing (TOEL) of the Enable Filter.
Output
Ch-t Zoom: 2.0x Vert 0.01X Horz M2.00ms CH4 J' 1.oomv'
MCP2035
DS22304A-page 26 2012 Microchip Technology Inc.
FIGURE 2-31: No Demodulator Output When Output Enable Filter is Enabled But Input Does Not
Meet Filter Timing Requirements.
Input Signal
No LFDATA
Output
Chl ‘ | MSyoops 011 J‘ szomv mm 011 200 Va» 7 . CHI J' SZOmV
2012 Microchip Technology Inc. DS22304A-page 27
MCP2035
FIGURE 2-32: Carrier Clock Output Examples.
(a) Carrier Clock Output with Carrier/1 Option
Carrier Clock Output
Carrier Input
(b) Carrier Clock Output with Carrier/4 Option
Carrier Input
Carrier Clock Output
MCP2035
DS22304A-page 28 2012 Microchip Technology Inc.
NOTES:
U“ m ALERT
2012 Microchip Technology Inc. DS22304A-page 29
MCP2035
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
3.1 Supply Voltage (VDD, VSS)
The VDD pin is the power supply pin for the analog and
digital circuitry within the MCP2035. This pin requires
an appropriate bypass capacitor of 0.1 µF. The voltage
on this pin should be maintained in the 2.0V-3.6V range
for specified operation.
The VSS pin is the ground pin and the current return
path for both analog and digital circuitry of the
MCP2035. If an analog ground plane is available, it is
recommended that this device be tied to the analog
ground plane of the PCB.
3.2 Chip Select (CS)
The CS pin needs to stay high when the device is
receiving input signals. Leaving the CS pin low will
place the device in the SPI Programming mode.
The CS pin is an open collector output. This pin has an
internal pull-up resistor to ensure that no spurious SPI
communication occurs between power-up and pin
configuration of the MCU.
3.3 SPI Clock Input (SCLK/ALERT)
This pin becomes the SPI clock input (SCLK) when CS
is low, and becomes the ALERT output when CS is
high.
The ALERT pin is an open collector output. This pin has
an internal pull-up resistor to ensure that no spurious
SPI communication occurs between power-up and pin
configuration of the MCU.
3.4 Received Signal Strength
Indicator (RSSI)
This pin becomes the Received Signal Strength Indicator
(RSSI) output current sink when the RSSI output option
is selected.
TABLE 3-1: PIN FUNCTION TABLES
MCP2035
TSSOP Symbol I/O/P Function
1V
SS P Ground Pin
2CS IChip Select Digital Input Pin
3 SCLK/ALERT I/O Clock input for the modified 3-wire SPI interface.
ALERT output: This pin goes low if there is a parity error in the
Configuration register or the 32 ms Alarm Timer is timed out.
4 RSSI O Received Signal Strength Indicator (RSSI) current output
5 NC N/A No Connect
6 LFDATA/CCLK/SDIO I/O Demodulated data output
Carrier clock output
Serial input or output data for the modified 3-wire SPI interface
7V
DD P Positive Supply Voltage Pin
8V
DD P Positive Supply Voltage Pin
9 NC N/A No Connect (Note 1)
10 NC N/A No Connect (Note 1)
11 LCX I Input pin for external LC antenna
12 NC N/A No Connect
13 LCCOM I Common reference input for the external LC antenna
14 VSS P Ground Pin
Type Identification: I = Input; O = Output; P = Power
Note 1: This pin is bonded out to ground internally.
MCP2035
DS22304A-page 30 2012 Microchip Technology Inc.
3.5 Demodulated Data Output (LFDATA)
Carrier Clock Output (CCLK)
SPI Data I/O (SDIO)
When the CS pin is high, this pin is an output pin for
demodulated data or carrier clock, depending on out-
put-type selection. When carrier clock output (CCLK) is
selected, the LFDATA output is a square pulse of the
input carrier clock and is available as soon as the AGC
stabilization time (TSTAB) is completed.
When the CS pin is low, this pin becomes the SPI data
input and output (SDIO).
3.6 LCX Input
This is the input pin of the LCX channel. An external LC
resonance antenna circuit can be connected between
the LCX and LCCOM pins.
3.7 LC Common Reference (LCCOM)
This pin is the common reference input pin for the
external LC resonant circuit.
2012 Microchip Technology Inc. DS22304A-page 31
MCP2035
4.0 APPLICATION INFORMATION
Microchip’s MCP2030 and MCP2035 are stand-alone
analog-front devices for low frequency (LF) signal
detection and low-power/short range transponder
applications. The MCP2035 is a single-channel
device, while the MCP2030 is a three-channel device
for more advanced applications.
The device’s high input sensitivity (1 mVPP) and
ability to detect very weakly modulated input signals
(as low as 8%), makes the device suitable for
various intelligent short range transponder
applications, such as Microchip’s BodyCom
applications.
4.1 MCP2035 BodyCom Application
Example
Figure 4-1 shows an example of a BodyCom system
that is utilizing the human body as a signal transmis-
sion medium. The system has two units: (a) Base Sta-
tion Unit and (b) Mobile Unit. An example of the
BodyCom communication sequence is as follows:
When the human interfaces with the Base Station,
it is initialized by an event of either touch or prox-
imity, and the Base Station transmits a modulated
128 kHz command signal.
This signal is then capacitively coupled to the
human body, propagates and is detected by the
Mobile Unit’s high sensitivity MCP2035 front-end
device.
The Mobile Unit processes the Base Station’s
command information, and responds back using a
high frequency (HF, 8 MHz) carrier.
This respond signal is then received by the HF
receiver in the Base Station, and demodulated
and fed to another MCP2035 in the Base Station
unit for digital waveforms. This return signal is
then processed by the MCU in the Base Station.
Figure 4-2 shows an example of the Mobile Unit
schematics. This BodyCom solution can be used in
various applications such as secure access control and
passive keyless entry for automobiles.
FIGURE 4-1: BodyCom System Example Utilizing the Human Body as a Signal Transmission
Medium.
Note: See Microchip’s Application Note AN1391
for more details of the BodyCom
applications solutions.
HF
Transmitter
LF
Driver
MCU
(PIC16LF1827)
MCP2035
(Single-Channel Stand-alone
Analog Front-End)
(8 MHz)
Mixer
HF
Receiver
Base Station Unit Mobile Unit
(128 kHz)
(8 MHz)
(128 kHz)
MCP2035
Human Interface
/Touch Pad
Capacitive
Coupling
Capacitive
Coupling
DSM
PIC16LF1829
Microcontroller
3} n%u%flflfl ALERT % e
MCP2035
DS22304A-page 32 2012 Microchip Technology Inc.
FIGURE 4-2: Example of BodyCom Mobile Unit Implementation.
NC
LCCOM
LCX
VSS
LFDATA/CCLK/SDIO
VDD
NC
NC
VSS
CS
SCLK/ALERT
RSSI
NC
VDD
PIC16LF1827 To A D C
+3V
MCP2035
+3V
RF Circuitry
(HF TX)
CL
(128 kHz)
Receiving Signal
(8 MHz)
Transmitting Signal
Data Signal Mod
(fC = 8 MHz)
2012 Microchip Technology Inc. DS22304A-page 33
MCP2035
5.0 FUNCTIONAL DESCRIPTION
AND THEORY OF DEVICE
OPERATION
The MCP2035 contains an analog input channel for
signal detection and LF talk-back. This section
provides the functional description of the device.
The input channel has internal tuning capacitors,
sensitivity control circuits, an input signal strength
limiter and an LF talk-back modulation transistor. An
AGC loop is used for input channel gains. The output of
the input channel is fed into a demodulator. The digital
output is passed to the LFDATA pin. Figure 5-1 shows
the block diagram of the device and Figure 5-2 shows
the input signal path.
There are a total of eight Configuration registers. Six of
them are used for device operation options, one for
column parity bits and one for status indication of
device operation. Each register has nine bits including
one row parity bit. These registers are readable and
writable by SPI commands, except for the STATUS
register, which is read-only.
The device’s features are dynamically controllable by
programming the Configuration registers.
5.1 RF Limiter
The RF Limiter limits LC pin input voltage by de-Q’ing
the external LC resonant antenna circuit. The limiter
begins de-Q’ing the external LC antenna when the
input voltage exceeds VDE_Q, progressively de-Q’ing
harder to reduce the antenna input voltage.
5.2 Modulation Circuit
for LF Talk-Back
The LF talk-back is achieved by turning on and off the
modulation transistor. The modulation circuit consists
of a modulation transistor (FET), internal tuning
capacitors and external LC antenna components. The
modulation transistor and the internal tuning capacitors
are connected between the LCX input pin and LCCOM
pin. Each LC input has its own modulation transistor.
When the modulation transistor turns on, its low
Turn-on Resistance (RM) clamps the induced LC
antenna voltage. The coil voltage is minimized when
the modulation transistor turns on, and maximized
when the modulation transistor turns off. The
modulation transistor’s low turn-on resistance (RM)
results in a high modulation depth.
The modulation data comes from the external micro-
controller section via the digital SPI as “Clamp On”,
“Clamp Off” commands. A basic block diagram of the
modulation circuit is shown in Figure 5-1 and
Figure 5-2.
The modulation FET is also shorted momentarily after
Soft Reset and Inactivity Timer time-out.
5.3 Tuning Capacitor
The input tuning capacitor values are programmed by
the Configuration registers up to 63 pF, 1 pF per step.
5.4 Variable Attenuator
The variable attenuator is used to attenuate, via AGC
control, the input signal voltage to avoid saturating the
amplifiers and demodulators.
5.5 Sensitivity Control
The sensitivity of the input channel can be reduced by
the Configuration register sensitivity setting. This is
used to desensitize the channel from optimum.
5.6 AGC Control
The AGC controls the variable attenuator to limit the
internal signal voltage to avoid saturation of internal
amplifiers and demodulators (Refer to Section 5.4
“Variable Attenuator”).
5.7 Fixed Gain Amplifiers 1 and 2
FGA1 and FGA2 provide a maximum two-stage gain
of 40 dB.
Note: The LF-Talk back is only used when it
needs to communicate back to the Base
Station using the same Base Station’s low
frequency (128 kHz) carrier frequency. A
typically LF-Talk back range is up to a few
inches. For the BodyCom applications, it
uses HF (~8 MHz) for the return signal.
Note: The user can control the tuning
capacitor by programming the
Configuration registers. See Register 5-2
for details.
Note: The variable attenuator function is
accomplished by the device itself. The
user cannot control its function.
Note: The user can desensitize the channel
sensitivity by programming the
Configuration registers. See Register 5-5
for details.
Note: The AGC control function is accomplished
by the device itself. The user cannot
control its function.
Note: The user cannot control the gain of these
two amplifiers.
ALERT ALERT ALERT
MCP2035
DS22304A-page 34 2012 Microchip Technology Inc.
5.8 Carrier Clock Detector
The Carrier Clock Detector senses the input carrier
cycles. The output of the detector switches digitally at
the signal carrier frequency. Carrier clock output is
available when the output is selected by the DATOUT
bit in Configuration Register 1 (Register 5-2).
5.9 Demodulator
The Demodulator consists of a full-wave rectifier, low-
pass filter, peak detector and Data Slicer that detects
the envelope of the input signal.
5.10 Data Slicer
The Data Slicer consists of a reference generator and
comparator. The Data Slicer compares the input with
the reference voltage. The reference voltage comes
from the minimum modulation depth requirement
setting and input peak voltage.
5.11 Output Enable Filter
The Output Enable Filter enables the LFDATA output
once the incoming signal meets the wake-up sequence
requirements (see Section 5.14 “Configurable
Output Enable Filter”).
5.12 Received Signal Strength
Indicator (RSSI)
The RSSI provides a current which is proportional to
the input signal amplitude (see Section 5.29.3
“Received Signal Strength Indicator (RSSI)
Output”).
5.13 Analog Front-End Timers
The device has an internal 32 kHz RC oscillator. The
oscillator is used in several timers:
Inactivity Timer
•Alarm Timer
Pulse Width Timer
Period Timer
AGC Settling Timer
5.13.1 RC OSCILLATOR
The RC oscillator generates a 32 kHz internal clock.
5.13.2 INACTIVITY TIMER
The Inactivity Timer is used to automatically return the
device to Standby mode, if there is no input signal. The
time-out period is approximately 16 ms (TINACT), based
on the 32 kHz internal clock.
The purpose of the Inactivity Timer is to minimize
current draw by automatically returning to the lower
current Standby mode, if there is no input signal for
approximately 16 ms.
The timer is reset when:
An amplitude change in the LF input signal, either
high-to-low or low-to-high
CS
pin is low (any SPI command)
Timer-related Soft Reset
The timer starts after AGC initialization time (TAGC).
The timer causes a Soft Reset when:
A previously received input signal does not
change either high-to-low or low-to-high for
TINACT
The Soft Reset returns the device to Standby mode
where most of the analog circuits, such as the AGC,
demodulator and RC oscillator, are powered down. This
returns the device to the lower Standby Current mode.
5.13.3 ALARM TIMER
The Alarm Timer is used to notify the external MCU that
the device is receiving an input signal that does not pass
the output enable filter requirement. The time-out period
is approximately 32 ms (TALARM) in the presence of
continuing noise.
The Alarm Timer time-out occurs if there is an input
signal for longer than 32 ms that does not meet the
output enable filter requirements. The Alarm Timer
time-out causes:
a) The ALERT pin to go low.
b) The ALARM bit to set in the Status
STATUS Register 7 (Register 5-8).
The external MCU is informed of the Alarm Timer time-
out by monitoring the ALERT pin. If the Alarm Timer
time-out occurs, the external MCU can take
appropriate actions, such as lowering channel
sensitivity or disabling the input channel. If the noise
source is ignored, the device can return to a lower
standby current draw state.
The timer is reset when the:
CS
pin is low (any SPI command).
Output enable filter is disabled.
LFDATA pin is enabled (signal passed output
enable filter).
The timer starts after the AGC initialization time.
The timer causes a low output on the ALERT pin when:
Output enable filter is enabled and modulated
input signal is present for TALARM, but does not
pass the output enable filter requirement.
Note: The Alarm Timer is disabled if the output
enable filter is disabled.
af a} Hi ml
2012 Microchip Technology Inc. DS22304A-page 35
MCP2035
5.13.4 PULSE WIDTH TIMER
The Pulse Width Timer is used to verify that the
received output enable sequence meets both the
minimum TOEH and minimum TOEL requirements.
5.13.5 PERIOD TIMER
The Period Timer is used to verify that the received
output enable sequence meets the maximum TOET
requirement.
5.13.6 AGC INITIALIZATION TIMER (TAGC)
This timer is used to keep the output enable filter in
Reset while the AGC settles on the input signal. The
time-out period is approximately 3.5 ms. At the end of
this time (TAGC), the input should remain high (TPAGC),
otherwise the counting is aborted and a Soft Reset is
issued. See Figure 5-4 for details.
FIGURE 5-1: Functional Block Diagram.
Note 1: The device needs a continuous and
uninterrupted high input signal during
AGC initialization time (TAGC). Any
absence of signal during this time may
reset the timer and a new input signal is
needed for AGC settling time, or may
result in an improper AGC gain setting,
which will produce invalid output.
2: The rest of the device section wakes
up if the input channel receives a sig-
nal with the AGC settling time cor-
rectly. STATUS Register 7 bit <2>
(Register 5-8) indicates the status if the
input channel wakes up.
Configuration
To Tuning Cap X
To Modulation
VSST
LCX
Transistors
Registers
VDDT
To Sensitivity X
AGC Preserve
Detector
CS LFDATA/
SCLK/ALERT
External MCU
Command Decoder/Controller
Mod
Tune X
Output Enable
RF
Lim
32 kHZ
Oscillator
B
A
AGC
Sensitivity
Control X
Filter
AGC
Timer
RSSI CCLK/SDIO
÷ 64
Watchdog
WAKEX
LCCOM
Modulation Depth
LCY (Note 1)
LCZ
(Note 1)
Note 1: LCY and LCZ pads are internally grounded.
MCP2035
DS22304A-page 36 2012 Microchip Technology Inc.
FIGURE 5-2: Input Signal Path.
A
A
RF
Limiter
MOD
FET
Capacitor
Tuning
Var.
Atten.
FGA1 FGA2
Full-Wave
LFDATA
X
Y
Z
LCX
LCCOM
Carrier
>4V
PP
CLKDIV
DATOUT
AGC
Feedback
Peak
REF GEN
0.1V
X
Y
ZB
AGCACT
AGCSIG
Demodulator
AGC
Registers
Configuration
Sens.
Control
Legend:
FGA = Fixed Gain Amplifier
FWR = Full-wave Rectifier
LPF = Low-pass Filter
PD = Peak Detector
00
Detector
+
+
+
Data Slicer
MOD Depth Control
Output Enable
Filter
10
Amplifier
Rectifier
Low-Pass
Filter Detector
Auto-Channel
Selector
32 kHz
Clock/AGC
/1 OR /4
C
CHX ACT
AUTOCHSEL
LFDATA
01
10
11
RSSI GEN
C
Timer
÷ 64
RSSI
DETX
WAKEX
WAKEY
WAKEZ
DETY
DETZ
0.4V
Note 1: LCY and LCZ pads are
internally grounded.
LCY, LCZ
(Note 1)
Decode
‘ fl «MW \ W M MW m MMMMW 4Hfl~ W M M; ”Mu H ‘ ‘—, HH 3w.» _—,
2012 Microchip Technology Inc. DS22304A-page 37
MCP2035
5.14 Configurable Output Enable Filter
The purpose of this filter is to enable the LFDATA
output and wake the external microcontroller only after
receiving a specific sequence of pulses on the LC input
pin. Therefore, it prevents waking up the external
microcontroller due to noise or unwanted input signals.
The circuit compares the timing of the demodulated
header waveform with a pre-defined value, and
enables the demodulated LFDATA output when a
match occurs.
The output enable filter consists of a high (TOEH) and
low duration (TOEL) of a pulse immediately after the
AGC settling gap time. The selection of high and low
times further implies a max period time. The output
enable high and low times are determined by SPI
programming. Figure 5-3 and Figure 5-4 show the
output enable filter waveforms.
There should be no missing cycles during TOEH.
Missing cycles may result in failing the output enable
condition.
FIGURE 5-3: Output Enable Filter Timing.
FIGURE 5-4: Output Enable Filter Timing Example (Detailed).
Data Packet
t TOEH t TOEL
Required Output Enable Sequence
LFDATA output is enabled
on this rising edge
t TOET
Demodulator
Output
TGAP
Device Wake-up
Start bit
AGC
(TAGC + TPAGC)
TSTAB
and AGC Stabilization Gap Pulse
LF Coil Input
Demodulated LFDATA Output
Low
Standby
Mode
Current
Filter is passed and
LFDATA is enabled
Gap
TPAGC
3.5 ms
Filter
starts
TGAP
Start bit for data
(need
TSTAB
t TOEH
t TOEL
t TOET
t 2T
E
(AFE Stabilization)
“high”) Pulse
TAGC
(AGC initialization time)
Legend:
TAGC = AGC initialization time TGAP = AGC stabilization gap
TPAGC = High time after TAGC TOEH = Minimum output enable filter high time
TSTAB = AGC stabilization time (TAGC + TPAGC)T
OEL = Minimum output enable filter low time
TE= Time element of pulse (minimum pulse width) TOET = Maximum output enable filter period
MCP2035
DS22304A-page 38 2012 Microchip Technology Inc.
TOEH is measured from the rising edge of the
demodulator output to the first falling edge. The pulse
width must fall within TOEH t TOET
.
TOEL is measured from the falling edge of the
demodulator output to the rising edge of the next pulse.
The pulse width must fall within TOEL t TOET.
TOET is measured from rising edge to the next rising
edge (i.e., the sum of TOEH and TOEL). The sum of TOEH
and TOEL must be t T
OET
. If the Configuration
Register 0 (Register 5-1), OEH<8:7> is set to ‘00’, then
the filter is disabled. See Figure 2-30 for this case.
The filter will reset, requiring a complete new successive
high and low period to enable LFDATA, under the
following conditions.
The received high is not greater than the
configured minimum TOEH value.
During TOEH, a loss of signal for longer than 56 s
causes a filter Reset.
The received low is not greater than the
configured minimum TOEL value.
The received sequence exceeds the maximum
TOET value:
-T
OEH + TOEL > TOET
-or T
OEH > TOET
-or T
OEL > TOET
A Soft Reset SPI command is received.
If the filter resets due to a long high-time (TOEH > TOET),
the high-pulse timer will not begin timing again until
after a gap of TE and another low-to-high transition
occurs on the demodulator output.
Disabling the output enable filter disables the TOEH and
TOEL requirement and the device passes all detected
data. See Figures 2-30,2-31 and 2-32 for examples.
When viewed from an application perspective, from the
pin input, the actual output enable filter timing must
factor in the analog delays in the input path (such as
demodulator charge and discharge times).
•T
OEH - TDR + TDF
•T
OEL + TDR - TDF
The output enable filter starts immediately after TGAP
,
the gap after AGC stabilization period.
5.15 Input Sensitivity Control
The device has typical input sensitivity of 3 mVPP
. This
means any input signal with amplitude greater than
3mV
PP can be detected. The internal AGC loop
regulates the detecting signal amplitude when the input
level is greater than approximately 20 mVPP
. This
signal amplitude is called “AGC-active level”. The AGC
loop regulates the input voltage so that the input signal
amplitude range will be kept within the linear range of
the detection circuits without saturation. The AGC
Active Status bit (AGCACT<5>) in STATUS Register 7
(Register 5-8) is set if the AGC loop regulates the input
voltage.
Tabl e 5 -2 shows the input sensitivity comparison when
the AGCSIG option is used. When AGCSIG option bit is
set, the demodulated output is available only when the
AGC loop is active (see Table 5-1). The channel input
sensitivity can be reduced by setting the appropriate
Configuration registers. Configuration Register 3
(Register 5-4), Configuration Register 4 (Register 5-5)
and Configuration Register 5 (Register 5-6) have the
option to reduce each channel gain from 0 dB to
approximately -30 dB.
TABLE 5-1: OUTPUT ENABLE FILTER
TIMING
OEH
<1:0> OEL
<1:0> TOEH
(ms) TOEL
(ms) TOET
(ms)
01 00 113
01 01 113
01 10 124
01 11 146
10 00 214
10 01 214
10 10 225
10 11 248
11 00 416
11 01 416
11 10 428
11 11 4410
00 XX Filter Disabled
Note 1: The timing values of TOEH and TOEL are
minimum and TOET is maximum at room
temperature and VDD = 3.0V, 32 kHz
oscillator.
TABLE 5-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>)
AGCSIG<7>
(Config. Register 5) Description Input Sensitivity
(Typical)
0Option Disabled – Detect any input signal level (demodulated data and carrier clock) 3.0 mVPP
1Option Enabled – No output until AGC Status = 1 (i.e., VPEAK 20 mVPP)
(demodulated data and carrier clock)
Provides the best signal to noise ratio
20 mVPP
2012 Microchip Technology Inc. DS22304A-page 39
MCP2035
5.16 Enable or Disable of Input
Channel
The Input channel can be enabled or disabled by
programming the LCXEN bit in Configuration
Register 0 (Register 5-1). When the input channel is
enabled, it detects the input signal and provides output.
When the channel is disabled, the device shuts down
the input channel and provides no output, while saving
current draws. The exact circuits disabled when an
input is disabled are amplifiers, detector, full-wave
rectifier, data slicer, and modulation FET. However, the
RF input limiter remains active to protect the silicon
from excessive antenna input voltages.
5.17 AGC Amplifier
The circuit automatically amplifies input signal voltage
levels to an acceptable level for the data slicer. Fast
attacking and slow releasing by nature, the AGC tracks
the carrier signal level and not the modulated data bits.
The AGC requires an AGC initialization time (TAGC).
The AGC will attempt to regulate the input channel’s
peak signal voltage into the data slicer to a desired
regulated AGC voltage – reducing the input path’s gain
as the signal level attempts to increase above
regulated AGC voltage, and allowing full amplification
on signal levels below the regulated AGC voltage.
The AGC has two modes of operation:
During the AGC initialization time (TAGC), the
AGC time constant is fast, allowing a reasonably
short acquisition time of the continuous input
signal.
After TAGC, the AGC switches to a slower time
constant for data slicing.
Also, the AGC is frozen when the input signal envelope
is low. The AGC tracks only high envelope levels.
5.18 AGC Preserve
The AGC preserve feature is used to preserve the AGC
value during the AGC initialization time (TAGC) and
apply the value to the data slicing circuit for the follow-
ing data streams instead of using a new tracking value.
This feature is useful to demodulate the input signal
correctly when the input has random amplitude varia-
tions at a given time period. This feature is enabled
when the device receives an AGC Preserve On com-
mand and disabled if it receives an AGC Preserve Off
command. Once the AGC Preserve On command is
received, the device acquires a new AGC value during
each AGC initialization time and preserves the value
until a Soft Reset or an AGC Preserve Off command is
issued. Therefore, it does not need to issue another
AGC Preserve On command. An AGC Preserve Off
command is needed to disable the AGC preserve
feature (see Section 5.30.2.5 “AGC Preserve On
Command” and Section 5.30.2.6 “AGC Preserve Off
Command” for AGC Preserve commands).
5.19 Soft Reset
The Soft Reset is issued in the following events:
a) After Power-on Reset (POR)
b) After Inactivity Timer time-out
c) If an “Abort” occurs
d) After receiving SPI Soft Reset command
The “Abort” occurs if there is no positive signal
detected at the end of the AGC initialization period
(TAGC). The Soft Reset initializes internal circuits and
brings the device into a low current Standby mode
operation. The internal circuits that are initialized by the
Soft Reset include:
Output Enable Filter
•AGC circuits
• Demodulator
32 kHz Internal Oscillator
The Soft Reset has no effect on the Configuration register
setup, except for some of the AFE STATUS Register 7
bits. (Register 5-8).
The circuit initialization takes one internal clock cycle
(1/32 kHz = 31.25 µs). During the initialization, the
modulation transistors between each input and
LCCOM pins are turned-on to discharge any internal/
external parasitic charges. The modulation transistors
are turned-off immediately after the initialization time.
The Soft Reset is executed in Active mode only. It is not
valid in Standby mode.
5.20 Minimum Modulation Depth
Requirement for Input Signal
The device demodulates the modulated input signal if
the modulation depth of the input signal is greater than
the minimum requirement that is programmed in
Configuration Register 5 (Register 5-6). Figure 5-5
shows the definition of the modulation depth and
examples. MODMIN<6:5> of the Configuration
Register 5 offer four options. They are 60%, 33%, 14%
and 6%. The default setting is 33%.
The purpose of this feature is to enhance the
demodulation integrity of the input signal. The 6%
setting is the best choice for the input signal with weak
modulation depth, which is typically observed near the
high-voltage Base Station antenna and also at far-
distance from the Base Station antenna. It gives the
best demodulation sensitivity, but is very susceptible to
noise spikes that can result in a bit detection error. The
60% setting can reduce the bit errors caused by noise,
but gives the least demodulation sensitivity. See
Table 5-3 for minimum modulation depth requirement
settings.
MCP2035
DS22304A-page 40 2012 Microchip Technology Inc.
FIGURE 5-5: Modulation Depth Examples.
TABLE 5-3: SETTING FOR MINIMUM
MODULATION DEPTH
REQUIREMENT
MODMIN Bits
(Config. Register 5) Modulation Depth
Bit 6 Bit 5
00 33% (default)
01 60%
10 14%
11 8%
(a) Modulation Depth Definition
(b) Input signal vs. minimum modulation depth setting vs. LFDATA output
BA
A - B
A + B X 100%
Modulation Depth (%) = 10 - 7
10 + 7 X 100% = 17.64%
Amplitude
10 mVPP
7 mVPP
Amplitude
Modulation Depth (%) =
t
t
Demodulated LFDATA Output when MODMIN Setting = 14%
Demodulated LFDATA Output if MODMIN Setting = 33%
Input signal with modulation depth = 17.64%
Coil Input Strength
Amplitude
0
(LFDATA output = not toggled)
t
t
(LFDATA output = toggled)
Input Signal
Input Signal
ALERT ALERT ALERT
2012 Microchip Technology Inc. DS22304A-page 41
MCP2035
5.21 Low-Current Sleep Mode
The device can stay at an ultra low-current mode
(Sleep mode) when it receives a Sleep command via
the Serial Peripheral Interface (SPI). All circuits includ-
ing the RF Limiter, except the minimum circuitry
required to retain register memory and SPI capability,
will be powered down to minimize the current draw.
Power-on Reset or any SPI command, other than the
Sleep command, is required to wake the device from
Sleep.
5.22 Low-Current Standby Mode
The device is in Standby mode when no input signal is
present on the input pin, but is powered and ready to
receive any incoming signals.
5.23 Low-Current Active Mode
The device is in Low-Current Active mode when an
input signal is present on any input pin and internal
circuitry is switching with the received data.
5.24 Error Detection of Configuration
Register Data
The Configuration registers are volatile memory.
Therefore, the contents of the registers can be cor-
rupted or cleared by any electrical incidence, such as
battery disconnect. To ensure data integrity, the device
has an error detection mechanism using row and col-
umn parity bits of the Configuration register memory
map. The bit 0 of each register is a row parity bit which
is calculated over the eight Configuration bits (from bit
1 to bit 8). The Column Parity Register (Configuration
Register 6) holds column parity bits; each bit is calcu-
lated over the respective columns (Configuration regis-
ters 0 to 5) of the Configuration bits. The STATUS
register is not included for the column parity bit calcula-
tion. Parity is to be odd. The parity bit, set or cleared,
makes an odd number of set bits. The user needs to
calculate the row and column parity bits using the
contents of the registers and program them. During
operation, the device continuously calculates the row
and column parity bits of the configuration memory
map. If a parity error occurs, the device lowers the
SCLK/ALERT pin (interrupting the microcontroller
section) indicating the configuration memory has been
corrupted or unloaded and needs to be reprogrammed.
At an initial condition after a Power-on Reset, the
values of the registers are all clear (default condition).
Therefore, the device will issue the parity bit error by
lowering the SCLK/ALERT pin. If the user reprograms
the registers with the correct parity bits, the SCLK/
ALERT pin will be toggled to logic high level
immediately.
The parity bit errors do not change or affect any
functional operation.
Table 5-4 shows an example of the register values and
corresponding parity bits.
TABLE 5-4: CONFIGURATION REGISTER PARITY BIT EXAMPLE
Register Name Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(Row Parity)
Configuration Register 0 10101000 0
Configuration Register 1 00000000 1
Configuration Register 2 00000000 1
Configuration Register 3 00000000 1
Configuration Register 4 00000000 1
Configuration Register 5 10000000 0
Configuration Register 6
(Column Parity Register)
1 1 0 1 0 1 1 1 1
MCP2035
DS22304A-page 42 2012 Microchip Technology Inc.
5.25 Factory Calibration
The device is calibrated during probe test to reduce the
device-to-device variation in standby current, internal
timing and sensitivity, as well as channel-to-channel
sensitivity variation.
5.26 De-Q’ing of Antenna Circuit
When the transponder is close to the Base Station, the
transponder coil may develop coil voltage higher than
VDE_Q. This condition is called “near field”. The device
detects the strong near field signal through the AGC
control, and de-Q’ing the antenna circuit to reduce the
input signal amplitude.
5.27 Demodulator
The demodulator recovers the modulation data from
the received signal, containing carrier plus data, by
appropriate envelope detection. The demodulator has
a fast rise (charge) time (TDR) and a fall time (TDF)
appropriate to an envelope of input signal (see
Section 1.0 “Electrical Specifications” for TDR and
TDF specifications). The demodulator contains the
full-wave rectifier, low-pass filter, peak detector and
data slicer.
FIGURE 5-6: Demodulator Charge and Discharge.
5.28 Power-On Reset
This circuit remains in a Reset state until a sufficient
supply voltage is applied. The Reset releases when the
supply is sufficient for correct device operation,
nominally VPOR.
The Configuration registers are all cleared on a
Power-on Reset. As the Configuration registers are
protected by odd row and column parity, the ALERT pin
will be pulled down – indicating to the external micro-
controller section that the configuration memory is
cleared and requires new programming.
5.29 LFDATA Output Selection
The device output is available only when the input
channel is enabled (LCXEN = Enabled in
Configuration Register 0).
The LFDATA output can be configured to pass the
Demodulator output, Received Signal Strength Indi-
cator (RSSI) output, or Carrier Clock (CCLK). See
Configuration Register 1 (Register 5-2) for more
details.
5.29.1 DEMODULATOR OUTPUT
The demodulator output is the default configuration of
the output selection. This is the output of an envelope
detection circuit. See Figure 5-6 for the demodulator
output.
When the demodulated output is selected, the output is
available in two different conditions depending on how
the options of Configuration Register 0 (Register 5-1)
are set: Output Enable Filter is disabled or enabled.
See Section 2.0 “Typical Performance Curves” for
various demodulated data output.
Related Configuration register bits:
Configuration Register 1 (Register 5-2),
DATOUT <8:7>:
bit 8 bit 7
00: Demodulator Output
01: Carrier Clock Output
10: RSSI Output
01: RSSI Output
Configuration Register 0 (Register 5-1): all bits
Full-wave Rectifier output
Input at LC input pin
Demodulated LFDATA output
TDR TDF
a- on a- \.
2012 Microchip Technology Inc. DS22304A-page 43
MCP2035
5.29.2 CARRIER CLOCK OUTPUT
When the carrier clock output is selected, the LFDATA
output is a square pulse of the input carrier clock and
available as soon as the AGC stabilization time (TAGC)
is completed. There are two Configuration register
options for the carrier clock output: (a) clock divide-by
one or (b) clock divide-by four, depending on bit
DATOUT<7> of Configuration Register 2
(Register 5-3). The carrier clock output is available
immediately after the AGC settling time. The Output
Enable Filter, AGCSIG, and MODMIN options are appli-
cable for the carrier clock output in the same way as the
demodulated output. See Figure 2-32 for carrier clock
output examples.
Related Configuration register bits:
Configuration Register 1 (Register 5-2),
DATOUT <8:7>:
bit 8 bit 7
00: Demodulator Output
01: Carrier Clock Output
10: RSSI Output
11: RSSI Output
Configuration Register 2 (Register 5-3),
CLKDIV<7>:
0: Carrier Clock/1
1: Carrier Clock/4
Configuration Register 0 (Register 5-1): all bits
are affected
Configuration Register 5 (Register 5-6)
5.29.3 RECEIVED SIGNAL STRENGTH
INDICATOR (RSSI) OUTPUT
An analog current output is available at the RSSI pin
when the Received Signal Strength Indicator (RSSI)
output is selected by the Configuration register. The
analog current is linearly proportional to the input signal
strength.
All timers in the circuit, such as the Inactivity Timer,
Alarm Timer, and AGC initialization time, are disabled
during the RSSI mode. Therefore, the RSSI output is
not affected by the AGC stabilization time, and
available immediately when the RSSI option is
selected. The device enters Active mode immediately
when the RSSI output is selected.
When the device receives an SPI command during the
RSSI output, the RSSI mode is temporarily disabled
until the SPI communication is completed. It returns to
the RSSI mode again after the SPI communication is
completed. The RSSI mode is held until another
output type is selected (CS low turns off the RSSI
signal).
The RSSI output current is linearly proportional to the
input signal strength. There are variations between
device to device. See Figure 2-13 for examples. The
linearity (ILRRSSI) of the RSSI output current is tested
by sampling the outputs for three input points:
37 mVPP
, 100 mVPP
, and 370 mVPP
. The RSSI output
current for 100 mVPP of input signal is compared with
the expected output current obtained from the line that
is connecting the two endpoints (37 mVPP and
370 mVPP). Equation 5-1 and Figure 5-7 show the
details for the RSSI linearity specification.
EQUATION 5-1: RSSI LINEARITY
SPECIFICATION
FIGURE 5-7: RSSI Linearity Test
Example.
ILRRSSI(%) =
Deviation at 100 mVPP of Input Signal
IRSSI for 370 mVPP of Input Signal
Where:
Deviation at 100 mVPP of Input Signal =
[IRSSI measured - IRSSI expected] at 100 mVPP
of input signal.
•I
RSSI expected = RSSI current obtained from
the line that is connecting two endpoints (RSSI
output currents for 37 mVPP and 370 mVPP of
input).
x 100%
RSSI Output Current [A]
y
x
37 mVPP 100 mVPP 370 mVPP
y = a+bx
=Measured
= Expected
d
d = Deviation
Input Signal Amplitude
9' m 9' \. E /ALERT
MCP2035
DS22304A-page 44 2012 Microchip Technology Inc.
Related Configuration register bits:
Configuration Register 1 (Register 5-2),
DATOUT<8:7>:
bit 8 bit 7
00: Demodulated Output
01: Carrier Clock Output
10: RSSI Output
11: RSSI Output
Configuration Register 2 (Register 5-3),
RSSIFET<8>:
0: Pull-Down MOSFET off
1: Pull-Down MOSFET on.
Configuration Register 0 (Register 5-1): all bits
are affected.
FIGURE 5-8: RSSI Output Path.
5.29.3.1 ANALOG-TO-DIGITAL DATA
CONVERSION OF RSSI SIGNAL
The RSSI output is an analog current. It needs an
external Analog-to-Digital (ADC) data conversion
device for digitized output. The ADC data conversion
can be accomplished by using a stand-alone external
ADC device, an external MCU that has internal ADC
features, or an external MCU that has no ADC features
but instead uses firmware. The RSSIFET is used to
discharge any external charge on the LFDATA pin in
the RSSI Output mode. The MOSFET can be turned on
or off with bit RSSIFET<8> of Configuration Register 2
(Register 5-3). When it is turned on, the internal
MOSFET provides a discharge path for the external
capacitor that is connected at the LFDATA pin. This
MOSFET option is valid only if RSSI output is selected
and not controllable by users for demodulated or carrier
clock output options.
See separate application notes for various external ADC
implementation methods for this device.
See Figure 5-8 for RSSI output path.
5.30 Configuration Registers
5.30.1 SPI COMMUNICATION
The SPI communication is used to read from or write to
the Configuration registers and to send command-only
messages. Three pins are used for SPI
communication: CS, SCLK/ALERT, and LFDATA/RSSI/
CCLK/SDIO. Figure 5-9, Figure 5-10 and Figure 5-11
show examples of the SPI communication sequences.
When these pins are connected to the external MCU
I/O pins, the following are needed:
CS
Pin is permanently an input with an internal pull-up.
SCLK/ALERT
Pin is an open collector output when CS is high.
An internal pull-up resistor exists to ensure no
spurious SPI communication between powering
and the MCU configuring its pins. This pin
becomes the SPI clock input when CS is low.
LFDATA/CCLK/SDIO
Pin is a digital output (LFDATA) so long as CS is
high. During SPI communication, the pin is the
SPI data input (SDI) unless performing a register
Read, where it will be the SPI data output (SDO).
Note: The pull-down MOSFET option is valid
only when the RSSI output is selected.
The MOSFET is not controllable by users
when demodulated or carrier clock output
option is selected.
RSSI Output Current
Generator
VDD
MOSFET (controlled
RSSI Pull-down
Current Output
LFDATA/CCLK Pin
RSSIFET(1)
Off
if RSSI active
RSSI Pin
Note 1: The RSSIFET is used to discharge any
external capacitor that is connected at
the LFDATA pin.
by Config. 2, bit 8)
2012 Microchip Technology Inc. DS22304A-page 45
MCP2035
FIGURE 5-9: Power-Up Sequence.
FIGURE 5-10: SPI Write Sequence.
CS
SCLK/ALERT
LFDATA/CCLK/SDIO
ALERT
LFDATA
(output)
(open collector
CS pulled high by
internal pull-up
MCU pin is input.
MCU pin is input. MCU pin is input.
MCU pin output
Driving CS high
output)
SCLK pulled high
by internal pull-up
CS
SCLK/ALERT
LFDATA/CCLK/SDIO
TSU THD
TCSSC TSCCS
THI TLO
1/FSCLK
TCS1
TCSH
TCS0
ALERT
LFDATA SDI
(output) (input)
(output)
SCLK
(input) ALERT
(output)
Driven low by MCU
Driven low by MCU
LFDATA
(output)
MCU pin to Input
MCU pin to Input
Driven low by MCU
16 Clocks for Write Command, Address and Data
MCU pin to Output
MCU pin still Input
1
2
3
4
5
6
7
MCU SPI Write Details:
1. Drive the open collector ALERT output low
To ensure no false clocks occur when CS drops
2. Drop CS
• SCLK/ALERT becomes SCLK input
LFDATA/CCLK/SDIO becomes SDI input
3. Change LFDATA/CCLK/SDIO connected pin to output
Driving SPI data
4. Clock in 16-bit SPI Write sequence – command, address, data and parity bit
Command, address, data and parity bit
5. Change LFDATA/CCLK/SDIO connected pin to input
6. Raise CS to complete the SPI Write
7. Change SCLK/ALERT back to input
LSbMSb
7 O 070 O O O O m ‘ L : m, 4% m+ 0‘ 01.. ‘ 1 ? 1 \J ‘ 3 ‘ x x: x q- x q- a0 O a 4r 4' ALERT § § ALERT E § LK/ALERT E ALERT
MCP2035
DS22304A-page 46 2012 Microchip Technology Inc.
FIGURE 5-11: SPI Read Sequence.
CS
LFDATA/RSSI/
CCLK/SDIO
Driven low by MCU
TSU THD
TSCCS
THI TLO
1/FSCLK
TCS1
TCSH
TCS0
SDI
(input)
SCLK
(input) ALERT
(output)
LFDATA
(output)
MCU pin to Input
MCU pin to Input
Driven low by MCU
MCU pin to Output
16 Clocks for Read Command, TCSSC TCSSC TCS1
TCSH
TCS0
SDO
SCLK
(input)
ALERT
(output)
LFDATA
(output)
MCU pin to Input
Driven low by MCU
16 Clocks for Read Result
(output)
SCLK/ALERT
ALERT
LFDATA
(output)
(output)
Driven low by MCU
MCU pin still Input
1
2
3
4
5
67
8
9
10
TDO
MSb LSb
TCSSC Address and Dummy Data
MCU SPI Read Details:
1. Drive the open collector ALERT output low
To ensure no false clocks occur when CS drops
2. Drop CS
• SCLK/ALERT becomes SCLK input
LFDATA/CCLK/SDIO becomes SDI input
3. Change LFDATA/CCLK/SDIO connected pin to output
Driving SPI data
4. Clock in 16-bit SPI Read sequence
Command, address and dummy data
5. Change LFDATA/CCLK/SDIO connected pin to input
6. Raise CS to complete the SPI Read entry of command and address
7. Drop CS
AFE SCLK/ALERT becomes SCLK input
LFDATA/CCLK/SDIO becomes SDO output
8. Clock out 16-bit SPI Read result
First seven bits clocked-out are dummy bits
Next eight bits are the Configuration register data
The last bit is the Configuration register row parity bit
9. Raise CS to complete the SPI Read
10. Change SCLK/ALERT back to input
Note: The TCSH is considered as one clock. Therefore, the Configuration register data appears at
6th clock after TCSH.
2012 Microchip Technology Inc. DS22304A-page 47
MCP2035
5.30.2 COMMAND DECODER/
CONTROLLER
The circuit executes eight SPI commands from the
external MCU. The command structure is:
Command (3 bits) + Configuration Address (4 bits) +
Data Byte and Row Parity Bit with the Most Significant
bit first. Table 5-5 shows the available SPI commands.
The device operates in SPI mode 0,0. In mode 0,0 the
clock idles in the low state (Figure 5-12). SDI data is
loaded into the device on the rising edge of SCLK and
SDO data is clocked out on the falling edge of SCLK.
There must be multiples of 16 clocks (SCLK) while CS
is low or commands will abort.
TABLE 5-5: SPI COMMANDS
Command Address Data Row
Parity Description
Command only – Address and Data are “Don’t Care”, but need to be clocked in regardless.
000 XXXX XXXX XXXX X Clamp on – enable modulation circuit
001 XXXX XXXX XXXX X Clamp off – disable modulation circuit
010 XXXX XXXX XXXX X Enter Sleep mode (any other command wakes the AFE)
011 XXXX XXXX XXXX X AGC Preserve On – to temporarily preserve the current AGC
level
100 XXXX XXXX XXXX X AGC Preserve Off – AGC again tracks strongest input signal
101 XXXX XXXX XXXX X Soft Reset – resets various circuit blocks
Read Command – Data will be read from the specified register address.
110 0000 Config Byte 0 P General – options that may change during normal operation
0001 Config Byte 1 P Input channel (LCX) antenna tuning and LFDATA output format
0010 Config Byte 2 P RSSIFET Condition and CLKDIV settings
0011 Config Byte 3 P Not used
0100 Config Byte 4 P Input channel (LCX) sensitivity reduction
0101 Config Byte 5 P Modulation depth and AGC loop
0110 Column Parity P Column parity byte for Config Byte 0 -> Config Byte 5
0111 Status X The device's internal operation status and parity error
indication bits
Write Command – Data will be written to the specified register address.
111 0000 Config Byte 0 P Output enable filter, channel enable/disable, etc.
0001 Config Byte 1 P Input channel (LCX) antenna tuning and LFDATA output type
0010 Config Byte 2 P RSSIFET, CLKDIV
0011 Config Byte 3 P Write all bits to “0s”
0100 Config Byte 4 P Input channel (LCX) sensitivity reduction
0101 Config Byte 5 P AGCSIG, MODMIN
0110 Column Parity P Column parity byte (odd parity) for Configuration Bytes 0 to 5
0111 Not Used X Register is readable, but not writable
Note: ‘P’ denotes the row parity bit (odd parity) for the respective data byte.
MCP2035
DS22304A-page 48 2012 Microchip Technology Inc.
FIGURE 5-12: Detailed SPI Timing (AFE).
5.30.2.1 Clamp On Command
This command results in activating (turning on) the
modulation transistor of the input channel.
5.30.2.2 Clamp Off Command
This command results in deactivating (turning off) the
modulation transistor of input channel.
5.30.2.3 Sleep Command
This command places the device in Sleep mode
minimizing current draw by disabling all but the
essential circuitry. Any other command wakes the
device from Sleep (e.g., Clamp Off command).
5.30.2.4 Soft Reset Command
The device issues a Soft Reset when it receives an
external Soft Reset command. The external Soft Reset
command is typically used to end a SPI communication
sequence or to initialize the device for the next signal
detection sequence, etc. See Section 5.19 “Soft
Reset” for more details on Soft Reset.
If a Soft Reset command is sent during a “Clamp-on”
condition, the device still keeps the “Clamp-on” condi-
tion after the Soft Reset execution. The Soft Reset is
executed in Active mode only, not in Standby mode.
The SPI Soft Reset command is ignored if the device is
not in Active mode.
5.30.2.5 AGC Preserve On Command
This command results in preserving the AGC level
during each AGC initialization time and applies the
value to the data slicing circuit for the following data
stream. The preserved AGC value is reset by a Soft
Reset, and a new AGC value is acquired and pre-
served when it starts a new AGC initialization time. This
feature is disabled by an AGC Preserve Off command
(see Section 5.18 “AGC Preserve”).
5.30.2.6 AGC Preserve Off Command
This command disables the AGC preserve feature and
returns to the normal AGC tracking mode, fast tracking
during AGC settling time and slow tracking after that
(see Section 5.18 “AGC Preserve”).
5.30.3 READ/WRITE COMMANDS FOR
CONFIGURATION REGISTERS
The device includes eight Configuration registers,
including a Column Parity register and STATUS regis-
ter. All registers are readable and writable via SPI com-
mands, except the STATUS register, which is read-
only. Bit 0 of each register is a row parity bit (except for
STATUS Register 7) that makes the register contents
an odd number (“1”) including the parity bit itself.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
bit 2
CS
SCLK
SDIO
Command Data Byte
bit 0
bit 8
bit 1
Address Row
Parity Bit
bit 0
bit 3
MSb LSb
bit 0
Note: If the odd parity bits for the row and
column are incorrectly programmed, the
Parity Error Indicator (PEI) bit in the Status
Register 7 is set (“1”) and the ALERT
output pin will pull low, which causes extra
current draws.
2012 Microchip Technology Inc. DS22304A-page 49
MCP2035
5.30.3.1 STATUS Register
The status register indicates the operation condition of
the MCP2035 device after various SPI commands and
Power-on Reset. See Tabl e 5 -7 for more details.
TABLE 5-6: CONFIGURATION REGISTERS SUMMARY
Register Name Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Configuration Register 0 OEH OEL ALRTIND 1
(Note 1) 1
(Note 1) LCXEN R0PAR
Configuration Register 1 DATOUT Input Channel (LCX) Tuning Capacitor R1PAR
Configuration Register 2 RSSIFET CLKDIV Write to all 0’s (Note 1) R2PAR
Configuration Register 3 Unimplemented Write to all 0’s (Note 1) R3PAR
Configuration Register 4 Input Channel (LCX) Sensitivity Control Write to all 0’s (Note 1) R4PAR
Configuration Register 5 0
(Note 1)
AGCSIG MODMIN MODMIN Write to all 0’s (Note 1) R5PAR
Column Parity Bit
Register 6
Column Parity Bits R6PAR
STATUS Register 7 Active Channel Indicators AGCACT Wake-up Channel Indicators ALARM PEI
Note 1: The values in the colored area are strongly recommended for the best result.
2: The user must compute the odd row parity bit (bit 0 of each row) and odd column parity bits in the Column
Parity Bit Register 6, and program them the same as other configuration registers.
3: STATUS Register is read only register.
ALERT
MCP2035
DS22304A-page 50 2012 Microchip Technology Inc.
REGISTER 5-1: CONFIGURATION REGISTER 0 (ADDRESS: 0000)
R/W-0
OEH1
bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OEH0 OEL1 OEL0 ALRTIND 11 LCXEN R0PAR
bit7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 8-7 OEH<1:0>: Output Enable Filter High Time (TOEH) bit
00 = Output Enable Filter disabled (no wake-up sequence required, passes all signals to LFDATA)
01 = 1 ms
10 = 2 ms
11 = 4 ms
bit 6-5 OEL<1:0>: Output Enable Filter Low Time (TOEL) bit
00 = 1 ms
01 = 1 ms
10 = 2 ms
11 = 4 ms
bit 4 ALRTIND: ALERT bit, output triggered by:
1 = Parity error and/or expired Alarm Timer (receiving noise, see Section 5.13.3 “Alarm Timer”)
0 = Parity error
bit 3-2 Write these two bits to all “1”. (Note 1)
bit 1 LCXEN: Input Channel (LCX) Enable bit
1 =Disabled
0 = Enabled
bit 0 R0PAR: Register 0 Parity bit – set or cleared (1 or 0) so the 9-bit register contains odd parity – an odd
number of set bits. An incorrect parity bit may draw unnecessary extra current.
Note 1: Writing these bits to1” ensures disabling of internally grounded unused channels (LCY and LCZ), which
guarantees minimizing any current draw through the unused internal channels.
2012 Microchip Technology Inc. DS22304A-page 51
MCP2035
REGISTER 5-2: CONFIGURATION REGISTER 1 (ADDRESS: 0001)
R/W-0
DATOUT1
bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATOUT0 LCXTUN5 LCXTUN4 LCXTUN3 LCXTUN2 LCXTUN1 LCXTUN0 R1PAR
bit7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 8-7 DATOUT<1:0>: LFDATA Output type bit
00 = Demodulated output
01 = Carrier clock output
10 = RSSI output
11 = RSSI output
bit 6-1 LCXTUN<5:0>: LCX Tuning Capacitance bit
000000 = +0 pF (Default)
111111 = +63 pF
bit 0 R1PAR: Register 1 Parity Bit – set or cleared (1 or 0) so the 9-bit register contains odd parity – an odd
number of set bits. An incorrect parity bit may draw unnecessary extra current.
REGISTER 5-3: CONFIGURATION REGISTER 2 (ADDRESS: 0010)
R/W-0
RSSIFET
bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CLKDIV 0 0 0 0 0 0R2PAR
bit7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 8 RSSIFET: Pull-down MOSFET on LFDATA pad bit (controllable by user in the RSSI mode only)
1 = Pull-down RSSI MOSFET on
0 = Pull-down RSSI MOSFET off
bit 7 CLKDIV: Carrier Clock Divide-by bit
1 = Carrier clock/4
0 = Carrier clock/1
bit 6-1 Recommended to all 0’s. (Note 1)
bit 0 R2PAR: Register 2 Parity bit – set or cleared (1 or 0) so the 9-bit register contains odd parity – an odd
number of set bits. An incorrect parity bit may draw unnecessary extra current.
Note 1: These bits are associated to the internally grounded LCY tuning capacitors, and have no effect in the MCP2035.
MCP2035
DS22304A-page 52 2012 Microchip Technology Inc.
REGISTER 5-4: CONFIGURATION REGISTER 3 (ADDRESS: 0011)
U-0
bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
0 0 0 0 0 0R3PAR
bit7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 8-7 Unimplemented: Read as0
bit 6-1 Recommended to all 0’s. (Note 1)
bit 0 R3PAR: Register 3 Parity Bit – set or cleared (1 or 0) so the 9-bit register contains odd parity – an odd
number of set bits. An incorrect parity bit may draw unnecessary extra current.
Note 1: These bits are associated to the internally grounded LCZ tuning capacitors, and have no effect in the
MCP2035.
2012 Microchip Technology Inc. DS22304A-page 53
MCP2035
REGISTER 5-5: CONFIGURATION REGISTER 4 (ADDRESS: 0100)
R/W-0
LCXSEN3
bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LCXSEN2 LCXSEN1 LCXSEN0 0 0 0 0R4PAR
bit7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 8-5 LCXSEN<3:0>: Typical Input Channel (LCX) Sensitivity Reduction bit. (Note 1)
0000 = -0 dB (Default)
0001 = -2 dB
0010 = -4 dB
0011 = -6 dB
0100 = -8 dB
0101 = -10 dB
0110 = -12 dB
0111 = -14 dB
1000 = -16 dB
1001 = -18 dB
1010 = -20 dB
1011 = -22 dB
1100 = -24 dB
1101 = -26 dB
1110 = -28 dB
1111 = -30 dB
bit 4-1 Recommended to all 0’s. (Note 2)
bit 0 R4PAR: Register 4 Parity bit – set or cleared (1 or 0) so the 9-bit register contains odd parity – an odd
number of set bits. An incorrect parity bit may draw unnecessary extra current.
Note 1: Assured monotonic increment (or decrement) by design.
2: These bits are associated to the internally grounded LCY sensitivity control, and have no effect in the
MCP2035.
L
MCP2035
DS22304A-page 54 2012 Microchip Technology Inc.
REGISTER 5-6: CONFIGURATION REGISTER 5 (ADDRESS: 0101)
R/W-0
0
bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AGCSIG MODMIN1 MODMIN0 0 0 0 0R5PAR
bit7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 8 Recommended to write 0’: This bit has no effect in the MCP2035.
bit 7 AGCSIG: Demodulator Output Enable bit, after the AGC loop is active
1 = Enabled – No output until AGC is regulating at around 20 mVPP at input pin. The AGC Active Sta-
tus bit is set when the AGC begins regulating.
0 = Disabled – The device passes signal of any level it is capable of detecting
bit 6-5 MODMIN<1:0>: Minimum Modulation Depth bit
00 = 33%
01 = 60%
10 = 14%
11 = 8%
bit 4-1 Recommended to all 0’s. (Note 1)
bit 0 R5PAR: Register 5 Parity bit – set or cleared (1 or 0) so the 9-bit register contains odd parity – an odd
number of set bits. An incorrect parity bit may draw unnecessary extra current.
Note 1: These bits are associated to the internally grounded LCZ sensitivity control.
2012 Microchip Technology Inc. DS22304A-page 55
MCP2035
REGISTER 5-7: COLUMN PARITY REGISTER 6 (ADDRESS: 0110)
R/W-0
COLPAR7
bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
COLPAR6 COLPAR5 COLPAR4 COLPAR3 COLPAR2 COLPAR1 COLPAR0 R6PAR
bit7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 8 COLPAR7: Set or Cleared (1 or 0) so that this 8th parity bit (COLPAR7) + the sum of the Config. reg-
ister row parity bits contain an odd number of set (“1”) bits.
bit 7 COLPAR6: Set or Cleared (1 or 0) such that this 7th parity bit (COLPAR6) + the sum of the 7th bits in
Config. registers 0 through 5 contain an odd number of set (“1”) bits.
bit 6 COLPAR5: Set or Cleared (1 or 0) such that this 6th parity bit (COLPAR5) + the sum of the 6th bits in
Config. registers 0 through 5 contain an odd number of set (“1” ) bits.
bit 5 COLPAR4: Set or Cleared (1 or 0) such that this 5th parity bit (COLPAR4) + the sum of the 5th bits in
Config. registers 0 through 5 contain an odd number of set (“1”) bits.
bit 4 COLPAR3: Set or Cleared (1 or 0) such that this 4th parity bit (COLPAR3) + the sum of the 4th bits in
Config. registers 0 through 5 contain an odd number of set (“1”) bits.
bit 3 COLPAR2: Set or Cleared (1 or 0) such that this 3rd parity bit (COLPAR2) + the sum of the 3rd bits in
Config. registers 0 through 5 contain an odd number of set (“1”) bits.
bit 2 COLPAR1: Set or Cleared (1 or 0) such that this 2nd parity bit (COLPAR1) + the sum of the 2nd bits
in Config. registers 0 through 5 contain an odd number of set (“1”) bits.
bit 1 COLPAR0: Set or Cleared (1 or 0) such that this 1st parity bit (COLPAR0) + the sum of the 1st bits in
Config. registers 0 through 5 contain an odd number of set (“1”) bits.
bit 0 R6PAR: Register 6 Parity bit – Set or Cleared (1 or 0) so the 9-bit register contains odd (“1”) parity –
an odd number of set (“1”) bits
Note 1: The parity bits are calculated from the configuration registers from 0 to 6 and programmed by the user. An
incorrect parity bit can cause unnecessary extra current draws although the device may function correctly.
ALERT ALERT
MCP2035
DS22304A-page 56 2012 Microchip Technology Inc.
REGISTER 5-8: STATUS REGISTER 7 (ADDRESS: 0111)
R-0
CHZACT
bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHYACT CHXACT AGCACT WAKEZ WAKEY WAKEX ALARM PEI
bit7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 8 CHZACT: This bit has no meaning in the MCP2035. Therefore, ignore this bit. This bit can be cleared
via Soft Reset.
bit 7 CHYACT: This bit has no meaning in the MCP2035. Therefore, ignore this bit. This bit can be cleared
via Soft Reset
bit 6 CHXACT: Input Channel (LCX) Active bit (cleared via Soft Reset). (Note 1)
1 = Input Channel (LCX) is passing data after TAGC
0 = Input Channel (LCX) is not passing data after TAGC
bit 5 AGCACT: AGC Active Status bit (real time, cleared via Soft Reset)
1 = AGC is active (Input signal is strong). AGC is active when input signal level is approximately
>20mV
PP range.
0 = AGC is inactive (Input signal is weak)
bit 4-3 This bit has no meaning, and can be cleared via Soft Reset.
bit 2 WAKEX: Wake-up Channel X Indicator Status bit (cleared via Soft Reset)
1 = Input Channel (LCX) caused a device wake-up (passed 64 clock counter)
0 = Input Channel (LCX) did not cause a device wake-up
bit 1 ALARM: Indicates whether an Alarm Timer time-out has occurred (cleared via read “STATUS Register
command”)
1 = The Alarm Timer time-out has occurred. It may cause the ALERT output to go low depending on
the state of bit 4 of the Configuration register 0
0 = The Alarm Timer is not timed out
bit 0 PEI: Parity Error Indicator bit – indicates whether a Configuration register parity error has occurred
(real time)
1 = A parity error has occurred and caused the ALERT output to go low
0 = A parity error has not occurred
Note 1: Bit is high whenever channel is passing data. Bit is low in Standby mode.
2012 Microchip Technology Inc. DS22304A-page 57
MCP2035
TABLE 5-7: STATUS REGISTER BIT CONDITION
(AFTER POWER-ON RESET AND VARIOUS SPI COMMANDS)
Condition
Bit 8
(Note 2) Bit 7
(Note 2) Bit 6 Bit 5 Bit 4
(Note 2) Bit 3
(Note 2) Bit 2 Bit 1 Bit 0
CHZACT CHYACT Input
(CHX)
ACT AGCACT WAKEZ WAKEY WAKEX ALARM PEI
POR 000000001
Read Command
(STATUS Register only)
uuuuuuu0u
Sleep Command uuuuuuuuu
Soft Reset Executed
(Note 1) 0000000uu
Legend: u = unchanged
Note 1: See Section 5.19 “Soft Reset” and Section 5.30.2.4 “Soft Reset Command” for the condition of Soft
Reset execution.
2: These bits have no meaning and are ignored in the MCP2035.
TABLE 5-8: EXAMPLE OF SELECTING CONFIGURATION REGISTER BIT VALUES AND PARITY
BITS
Register
Name Bit
8Bit
7Bit
6Bit
5Bit
4Bit
3Bit
2 Bit
1
Bit 0
(Calculate
d Row
Parity Bit)
Condition
Config. Reg. 0 1 0 1 0 1 1 100OEH = OEL = 2 ms, ALRTIND = 1,
Input Channel (LCX) = Enabled
Config Reg. 1 0 0 0 0 0 0 0 1 0Output Data Type = Demodulated Output,
Input Tuning Capacitor Value = 1 pF
Config Reg. 2 0 0 0 0 0 0 0 0 1RSSI Pull-Down MOSFET = Off,
CLKDIV = 0
Config Reg. 3 0 0 0 0 0 0 0 0 1Recommended
Config Reg. 4 0 0 0 0 0 0 0 0 1Input Channel Sensitivity Reduction = None
Config Reg. 5 01 0 0 0 0 0 0 0AGCSIG = 1, Min Modulation Depth = 33%
Calculated
Column Parity
Register 6
00010000 0 Calculated Column Odd Parity Bits
Note 1: The values in the colored area are strongly recommended for the best result.
2: See the calculated row and column parity bits. These bits must be programmed by the user. See Note in
Section 5.30.3 “Read/Write Commands for Configuration Registers” for the parity bits.
MCP2035
DS22304A-page 58 2012 Microchip Technology Inc.
NOTES:
HHHHHHH HHHHHHH Q ‘9 O O HHHHHHH HHHHHHH
2012 Microchip Technology Inc. DS22304A-page 59
MCP2035
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
14-Lead TSSOP Example
YYWW
NNN
XXXXXXXX
2035I
1217
256
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body USSOP] 'HIIHi, N M J L ”L TOP VIEW SEATING PLANE """ 14X b—— .---a SIDE VIEW MIcrochIp Technology Drawmg comoevc SheeI 1 of 2
MCP2035
DS22304A-page 60 2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14-Lead Plastic Thin Shrink Small Outline (ST) -4.4 mm Body [TSSOP] Unils MlLLIMETERS Dimenslon Limils MIN | NOM | MAX Number oi Plns N 14 Pllch e o 65 BSC Overall Helght A , , 1 20 Molded Package Tmckness A2 0 80 1 co 1 05 Slandofl A1 0 05 , o 15 Overall wlaln E 6 40 BSC Molded Package Width E1 4 30 4 4o 4 50 Molded Package Lenglh D 4 90 5 00 510 Paal Lengm L o 45 a so a 75 Foolprinl (L1) 1.00 REF Fool Angle «1 a” . 5° Leaa Thlckness c a 09 . a 20 Lead Widlh a 019 . a an Notes 1. Pin 1 visual index lealure may vary bul musl be localea w1ln1n lne hatched area. 2. Dimensmns D and E1 do nal lnclude mold flash or pralmsians Mold llasn or prolruslons snall not exceed U15mm per Slde 3 Dimenslonlng and tolerancing per ASME v14 5M BSC Basic Dimenslorl. Thearellcally exacl value shown wlthoul mlerances. REF Relerence Dlmension‘ usually without tolerance, for inlormalion purposes only. Microchlp Technalogy Drawlng No. co4rosvc Sheet 2 012
2012 Microchip Technology Inc. DS22304A-page 61
MCP2035
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] 0‘ C1 ‘ E E: LE E7 l:| EJ Jg g—i \ ,l a L SILK SCREEN RECOMMENDED LAND PATTERN Units MlLLIMETERS Dimension Limits MIN | NOM | MAX Contact Pitch E o 65 380 Contact Pad Spacing c1 5 90 Contact Pad Wldlh (x14) x1 0 45 Contact Pad Length (x14) w 1 45 Distance Belween Pads G o 20 Notes: ‘l. Dimensioning and Iolerancmg per ASME Y14.5M ESC' Basic Dlmension Theoretically Exact Value shown wilhoul tolerances Microchip Tachnulugy Drawing No 004-2087A
MCP2035
DS22304A-page 62 2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012 Microchip Technology Inc. DS22304A-page 63
MCP2035
APPENDIX A: REVISION HISTORY
Revision A (May 2012)
Original Release of this Document.
MCP2035
DS22304A-page 64 2012 Microchip Technology Inc.
NOTES:
PART NO. X /XX
2012 Microchip Technology Inc. DS20000A-page 65
MCP2035
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device: MCP2035: Single-Channel Stand-Alone Analog
Front-end (AFE)
Temperature Range: I= -40C to +85C (Industrial)
Package: ST = Plastic Shrink Small outline (4.4 mm) -
(TSSOP)
Examples:
a) MCP2035-I/ST: Industrial Temperature,
14LD TSSOP Package
b) MCP2035T-I/ST: Tape and Reel,
Industrial Temperature,
14LD TSSOP Package
MCP2035
DS20000A-page 66 2012 Microchip Technology Inc.
NOTES:
YSTEM <2>
2012 Microchip Technology Inc. DS22304A-page 67
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-2-684
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
6‘ ‘MICRDCHIP
DS22304A-page 68 2012 Microchip Technology Inc.
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China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Osaka
Tel: 81-66-152-7160
Fax: 81-66-152-9310
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Worldwide Sales and Service
11/29/11

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