MUN5314DW1, NSBC114YPDxx Datasheet by ON Semiconductor

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This series of digital lra "stors is designed to replace a device and its external re or b' network. The Bias Re Transistor (BRT) ctmmim single liansisior with u monolithic bias network consisting of twt) resistors; a cries base resistor and a basereminer resistor. The BRT eliminates these individual components by imegmling them into a single device. The use otu BRT can reduce both system cost and board space. Fealu res - Simplifies Circuit Design - Reduces Board Space - Reduces Component Count - s and NSV Prefix for Automotive and Other Applicaiitms Requiring Unique site and Control Change Requirements: AECrQlUl Qualified and PPAP Capable' - These Devices are PbrFree, Halogen Free/BFR Free and are RUHS Compliant MAXIMUM RATINGS ('rA : 25°C ooth polarities or (PNP| a 02 (NPNj, unless dtherwrse noted) Ratlng Symbol Max Unlt ColleciotrBase Voltage V050 50 Vde ColleciotrEmlfler Voltage V050 50 Vde Collector Current — Continuous lc too mAdc Input Forward Voltage VWM, 40 Vde Input Reverse Voltage VWEV, s Vde Stresses exceedlng those listed in the Maxlmum Ratings table may damage the devrce, It any ot these time are exceeded deviee tunetlonalrty should not he assumed damage may occur and rellahility may he attested, ORDERING INFORMATION Devlce Package Shippingl MUNSSMDWITlGr so‘r—asa 3,qu / Tape 3. Reel SMUNSBMDWlTlG" NSVMUN5314DW1TSG' so‘r—asa 10,000/Tape & Reel Nssetl AYPDXVGTI e, so‘r—ssa 4,000 /Tape 3. Reel NSVECl t 4VPDXV6T1G“ Nssetl AYPDXVGTSG so‘r—ssa 5,000 /Tape 3. Reel Nssetl AYPDPSTSG so‘r—esa 5,000 /Tape 3. Reel ler lntormatrdn on tape and reel speertrcations, lncludtng part dnentation and tape sizes, please reter to our Tape and Reel Packaglrlg Speelheations Brochure, BRDsml/D, o Semlcunduclurcampunenu luausuras LLC zuls 1 June, 2017 — Rev. 6 0N Semiconductor® Pu
© Semiconductor Components Industries, LLC, 2016
June, 2017 Rev. 6
1Publication Order Number:
DTC114YP/D
MUN5314DW1,
NSBC114YPDXV6,
NSBC114YPDP6
Complementary Bias
Resistor Transistors
R1 = 10 kW, R2 = 47 kW
NPN and PNP Transistors with Monolithic
Bias Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base-emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable*
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
(TA = 25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted)
Rating Symbol Max Unit
Collector-Base Voltage VCBO 50 Vdc
Collector-Emitter Voltage VCEO 50 Vdc
Collector Current Continuous IC100 mAdc
Input Forward Voltage VIN(fwd) 40 Vdc
Input Reverse Voltage VIN(rev) 6 Vdc
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
Device Package Shipping
MUN5314DW1T1G,
SMUN5314DW1T1G*
SOT363 3,000 / Tape & Reel
NSVMUN5314DW1T3G* SOT363 10,000 / Tape & Reel
NSBC114YPDXV6T1G,
NSVBC114YPDXV6T1G*
SOT563 4,000 / Tape & Reel
NSBC114YPDXV6T5G SOT563 8,000 / Tape & Reel
NSBC114YPDP6T5G SOT963 8,000 / Tape & Reel
For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
www.onsemi.com
MARKING DIAGRAMS
PIN CONNECTIONS
14 M G
1
14/Q = Specific Device Code
M = Date Code*
G= Pb-Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending up-
on manufacturing location.
SOT363
CASE 419B
SOT563
CASE 463A
Q1
Q2
(1)(2)(3)
(6)(5)(4)
R1
R2
R2
R1
SOT963
CASE 527AD
M
1
Q
14 MG
G
1
6
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MUN5314DW1, NSBC114YPDXV6, NSBC114YPDP6
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2
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
MUN5314DW1 (SOT363) ONE JUNCTION HEATED
Total Device Dissipation
TA = 25°C (Note 1)
(Note 2)
Derate above 25°C (Note 1)
(Note 2)
PD187
256
1.5
2.0
mW
mW/°C
Thermal Resistance, (Note 1)
Junction to Ambient (Note 2)
RqJA 670
490
°C/W
MUN5314DW1 (SOT363) BOTH JUNCTION HEATED (Note 3)
Total Device Dissipation
TA = 25°C (Note 1)
(Note 2)
Derate above 25°C (Note 1)
(Note 2)
PD250
385
2.0
3.0
mW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 1)
(Note 2)
RqJA 493
325
°C/W
Thermal Resistance,
Junction to Lead (Note 1)
(Note 2)
RqJL 188
208
°C/W
Junction and Storage Temperature Range TJ, Tstg 55 to +150 °C
NSBC114YPDXV6 (SOT563) ONE JUNCTION HEATED
Total Device Dissipation
TA = 25°C (Note 1)
Derate above 25°C (Note 1)
PD357
2.9
mW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 1)
RqJA 350
°C/W
NSBC114YPDXV6 (SOT563) BOTH JUNCTION HEATED (Note 3)
Total Device Dissipation
TA = 25°C (Note 1)
Derate above 25°C (Note 1)
PD500
4.0
mW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 1)
RqJA 250
°C/W
Junction and Storage Temperature Range TJ, Tstg 55 to +150 °C
NSBC114YPDP6 (SOT963) ONE JUNCTION HEATED
Total Device Dissipation
TA = 25°C (Note 4)
(Note 5)
Derate above 25°C (Note 4)
(Note 5)
PD231
269
1.9
2.2
MW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 4)
(Note 5)
RqJA 540
464
°C/W
NSBC114YPDP6 (SOT963) BOTH JUNCTION HEATED (Note 3)
Total Device Dissipation
TA = 25°C (Note 4)
(Note 5)
Derate above 25°C (Note 4)
(Note 5)
PD339
408
2.7
3.3
MW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 4)
(Note 5)
RqJA 369
306
°C/W
Junction and Storage Temperature Range TJ, Tstg 55 to +150 °C
1. FR4 @ Minimum Pad.
2. FR4 @ 1.0 ×1.0 Inch Pad.
3. Both junction heated values assume total power is sum of two equally powered channels.
4. FR4 @ 100 mm2, 1 oz. copper traces, still air.
5. FR4 @ 500 mm2, 1 oz. copper traces, still air.
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MUN5314DW1, NSBC114YPDXV6, NSBC114YPDP6
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3
ELECTRICAL CHARACTERISTICS (TA=25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector-Base Cutoff Current
(VCB =50V, I
E=0)
ICBO
100
nAdc
Collector-Emitter Cutoff Current
(VCE =50V, I
B=0)
ICEO
500
nAdc
Emitter-Base Cutoff Current
(VEB = 6.0 V, IC=0)
IEBO
0.2
mAdc
Collector-Base Breakdown Voltage
(IC=10mA, IE=0)
V(BR)CBO 50 − −
Vdc
Collector-Emitter Breakdown Voltage (Note 6)
(IC= 2.0 mA, IB=0)
V(BR)CEO 50 − −
Vdc
ON CHARACTERISTICS
DC Current Gain (Note 6)
(IC= 5.0 mA, VCE =10V)
hFE 80 140
Collector-Emitter Saturation Voltage (Note 6)
(IC= 10 mA, IB= 0.3 mA)
VCE(sat)
0.25
V
Input Voltage (Off)
(VCE = 5.0 V, IC= 100 mA) (NPN)
(VCE = 5.0 V, IC= 100 mA) (PNP)
Vi(off)
0.7
0.7
0.3
0.3
Vdc
Input Voltage (On)
(VCE = 0.2 V, IC= 1.0 mA) (NPN)
(VCE = 0.2 V, IC= 1.0 mA) (PNP)
Vi(on) 1.4
1.4
0.8
0.9
Vdc
Output Voltage (On)
(VCC = 5.0 V, VB= 2.5 V, RL= 1.0 kW)
VOL
0.2
Vdc
Output Voltage (Off)
(VCC = 5.0 V, VB= 0.5 V, RL= 1.0 kW)
VOH 4.9 − −
Vdc
Input Resistor R1 7.0 10 13 kW
Resistor Ratio R1/R20.17 0.21 0.25
6. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle 2%.
Figure 1. Derating Curve
AMBIENT TEMPERATURE (°C)
12510075502502550
0
50
100
150
200
250
300
PD, POWER DISSIPATION (mW)
150
(1) (2)
(1) SOT363; 1.0 ×1.0 Inch Pad
(2) SOT563; Minimum Pad
(3) SOT963; 100 mm2, 1 oz. Copper Trace
350
400
(3)
MUN5314DW1, NSBC114YPDXV6, NSBC114YPDP6
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4
TYPICAL CHARACTERISTICS NPN TRANSISTOR
MUN5314DW1, NSBC114YPDXV6
1000
100
10
1
Figure 2. VCE(sat) vs. IC
1002030
IC, COLLECTOR CURRENT (mA)
40 50
Figure 3. DC Current Gain
Figure 4. Output Capacitance
01020 50
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 5. Output Current vs. Input Voltage
100
10
1
0.1
0.01
0.001 01234
Vin, INPUT VOLTAGE (V)
56 78 910
Figure 6. Input Voltage vs. Output Current
VR, REVERSE VOLTAGE (V)
VCE(sat), COLLECTOREMITTER VOLTAGE (V)
IC/IB = 10
55°C
150°C
25°C
hFE, DC CURRENT GAIN
f = 10 kHz
IE = 0 A
TA = 25°C
Cob, OUTPUT CAPACITANCE (pF)
VO = 5 V
150°C
55°C
25°C
IC, COLLECTOR CURRENT (mA)
VO = 0.2 V
Vin, INPUT VOLTAGE (V)
25°C
1
0.1
0.01
4030 0.1 1 10010
VCE = 10 V
25°C150°C
55°C
3.6
3.2
2.8
2.4
2
1.6
1.2
0.8
0.4
0
010 20304050
100
10
1
0.1
150°C
55°C
MUN5314DW1, NSBC114YPDXV6, NSBC114YPDP6
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5
TYPICAL CHARACTERISTICS PNP TRANSISTOR
MUN5314DW1, NSBC114YPDXV6
1000
100
10
1
Figure 7. VCE(sat) vs. IC
1002030
IC, COLLECTOR CURRENT (mA)
40 50
Figure 8. DC Current Gain
Figure 9. Output Capacitance
01020 50
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 10. Output Current vs. Input Voltage
100
10
1
0.1
0.01
0.001 01234
Vin, INPUT VOLTAGE (V)
56 7
Figure 11. Input Voltage vs. Output Current
VR, REVERSE VOLTAGE (V)
VCE(sat), COLLECTOREMITTER VOLTAGE (V)
IC/IB = 10
55°C
150°C
25°C
hFE, DC CURRENT GAIN
f = 10 kHz
IE = 0 A
TA = 25°C
Cob, OUTPUT CAPACITANCE (pF)
VO = 5 V
150°C
55°C
25°C
IC, COLLECTOR CURRENT (mA)
VO = 0.2 V
Vin, INPUT VOLTAGE (V)
25°C
1
0.1
0.01
4030 0.1 1 10010
VCE = 10 V
25°C150°C
55°C
10
010 20304050
100
10
1
0.1
150°C
55°C
9
8
7
6
5
4
3
2
1
0
MUN5314DW1, NSBC114YPDXV6, NSBC114YPDP6
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6
TYPICAL CHARACTERISTICS NPN TRANSISTOR
NSBC114YPDP6
1000
100
10
1
Figure 12. VCE(sat) vs. IC
1002030
IC, COLLECTOR CURRENT (mA)
40 50
Figure 13. DC Current Gain
Figure 14. Output Capacitance
01020 50
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 15. Output Current vs. Input Voltage
100
10
1
0.1
0.01
0.001 01234
Vin, INPUT VOLTAGE (V)
56 7
Figure 16. Input Voltage vs. Output Current
VR, REVERSE VOLTAGE (V)
VCE(sat), COLLECTOREMITTER VOLTAGE (V)
IC/IB = 10
55°C
150°C
25°C
hFE, DC CURRENT GAIN
f = 10 kHz
IE = 0 A
TA = 25°C
Cob, OUTPUT CAPACITANCE (pF)
VO = 5 V
150°C
55°C
25°C
IC, COLLECTOR CURRENT (mA)
VO = 0.2 V
Vin, INPUT VOLTAGE (V)
25°C
1
0.1
0.01
4030 0.1 1 10010
VCE = 10 V
25°C150°C
55°C
2.4
010 20304050
100
10
1
0.1
150°C
55°C
2
1.6
1.2
0.8
0.4
0
MUN5314DW1, NSBC114YPDXV6, NSBC114YPDP6
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7
TYPICAL CHARACTERISTICS PNP TRANSISTOR
NSBC114YPDP6
1000
100
10
1
Figure 17. VCE(sat) vs. IC
1002030
IC, COLLECTOR CURRENT (mA)
40 50
Figure 18. DC Current Gain
Figure 19. Output Capacitance
01020 50
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 20. Output Current vs. Input Voltage
100
10
1
0.1
0.01
0.001 01 2 3 4
Vin, INPUT VOLTAGE (V)
567
Figure 21. Input Voltage vs. Output Current
VR, REVERSE VOLTAGE (V)
VCE(sat), COLLECTOREMITTER VOLTAGE (V)
IC/IB = 10
55°C
150°C
25°C
hFE, DC CURRENT GAIN
f = 10 kHz
IE = 0 A
TA = 25°C
Cob, OUTPUT CAPACITANCE (pF)
VO = 5 V
150°C
55°C
25°C
IC, COLLECTOR CURRENT (mA)
VO = 0.2 V
Vin, INPUT VOLTAGE (V)
25°C
1
0.1
0.01
4030 0.1 1 10010
VCE = 10 V
25°C150°C
55°C
7
010 20304050
100
10
1
0.1
150°C
55°C
6
5
4
3
2
1
011101112
E 0N Semiwndudw" TEs DIMENsIoNING AND ToLEHANcINs PER coNTRoLLINe DIMENSION MILLIMETE DIMENsIoNs D AND E Do NoT INCLu PnomusIoNs. 0R GATE EURRS Mo SIGNS. 0R GATE EURRS SHALL NoT DIMENsIoNs D AND E AT THE DDT THE PLASHC DDDv AND DATDM H DATuMs A AND E ARE DETERMINED AT DATUM DIMENsIoNs I: AND c APPLV To THE ELAT SEC LEAD BETWEEN a DD AND D 15 FROM THE HP DIMENSION e DoEs Not INcLuDE DAMBAR PHoTRusIoN ALLOWAELE DAMBAR PRoTHusIoN sHALL HE D DE ToTAL IN EXCESS or DIMENSION :7 AT MAXIMUM MATERIAL CONDIE TIoN THE DAMEAR cANNoT BE LOCATED oN THE LOWER RADIUS 0: THE FOOT mi 23x nes EH Le L e . s mu. m Mom MAX '3 "b" A , , Tm TOPVIEW m M ”a m" ”a” a me Dec L125 nuns Dana c nus m5 L122 mm: anus am“ e ‘80 2m: 220 Dam Inna 7A 2m am 220 we unsz 7 \ e ms Tee I35 was we me ~ 9 n as 350 a D26 55!: / L age I use I me am Imm Iame f I 7 7 \ J / E m] émm \1 c f m am we SIDE VIEW END VIEW GENERIC MARKING DIAGRAM‘ RECOMMENDED SH H H SOLDERING FOOTPRINT‘ m 5x xxxm- o 65 44 Ie PITCH DIMENSIoNs MILUMEIERS ‘FoI admIIonaI mIormeIIon on our Ph-FIee sIraIegy and soldenng aeIaIIs, please aowmcea Ihe ON SemIconducmr Soldenng and MounIIng Techniques neIeIence Manuala SOLDERRM/D STYLES ON PAGE 2 O IUUU xxx : Specmc Device Code M : Date Code” . : Ph-Free Package (NcIe. MicmaoL may be in eIIher locahom 'DaIe Code DTientaIIon and/or posmon may vaIy dependmg upon manuIacIunng IccaIion ON SemIcunduclm and are hademavks cI SemIcanduclur eempcnems lndusllles. LLC dba ON Semlcanduclar Dr Ils suhsIdlarIes In Ine Dnuee sxaxes andJm mhev cmm‘nes ON SemIcunduclar vesewes me "gm Ic make changes wIlhmA Imne. ncnee In any prawns thEIn oN Semenduc‘nv makes ne wananIy. represenlalmn m guarantee regarding Ine smIaInILIy eI W5 manual: Ier any pamcuIay purpase nnv dues ON Semumnduclm assume any ILaInILIy snsmg euIeI Ine applIcshan m use no any pmdudm clrcufl and specmcany mseIaIms any and an Iaenny Inc‘udmg wIlth Immaucn spemaI censeeuenIIaI m InmcenIaI damages ON Sermmnduclar dues nnl eenyey any hcense under Is paIenI “QM: Ivar Ine ngnIs DI nlhers
SC88/SC706/SOT363
CASE 419B02
ISSUE Y
DATE 11 DEC 2012
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
Cddd M
123
A1
A
c
654
E
b
6X
XXXMG
G
XXX = Specific Device Code
M = Date Code*
G= PbFree Package
GENERIC
MARKING DIAGRAM*
1
6
STYLES ON PAGE 2
1
DIM MIN NOM MAX
MILLIMETERS
A−−− −−− 1.10
A1 0.00 −−− 0.10
ddd
b0.15 0.20 0.25
C0.08 0.15 0.22
D1.80 2.00 2.20
−−− −−− 0.043
0.000 −−− 0.004
0.006 0.008 0.010
0.003 0.006 0.009
0.070 0.078 0.086
MIN NOM MAX
INCHES
0.10 0.004
E1 1.15 1.25 1.35
e0.65 BSC
L0.26 0.36 0.46
2.00 2.10 2.20
0.045 0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.078 0.082 0.086
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.65
0.66
6X
DIMENSIONS: MILLIMETERS
0.30
PITCH
2.50
6X
RECOMMENDED
TOP VIEW
SIDE VIEW END VIEW
bbb H
B
SEATING
PLANE
DETAIL A E
A2 0.70 0.90 1.00 0.027 0.035 0.039
L2 0.15 BSC 0.006 BSC
aaa 0.15 0.006
bbb 0.30 0.012
ccc 0.10 0.004
A-B D
aaa C
2X 3 TIPS
D
E1
D
e
A
2X
aaa H D
2X
D
L
PLANE
DETAIL A
H
GAGE
L2
C
ccc C
A2
6X
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
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DOCUMENT NUMBER:
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SC88/SC706/SOT363
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STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 3:
CANCELLED
STYLE 2:
CANCELLED
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 8:
CANCELLED
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
SC88/SC706/SOT363
CASE 419B02
ISSUE Y
DATE 11 DEC 2012
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42985B
DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SC88/SC706/SOT363
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" m NDTES: 1. DIMENSIDNING AND TEILERANCING PER ASME Y14.5M. 2009. 2. CDNTREILLING DIMENSIDN: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS DF EASE MATERIAL. kDAE A f—sx L PIN DNE 6 5 4 + INDICATEIR b 1 2 3 LJLJ e» EULEM b *H: TDP VIEW SIDE VIEW 1.30 6X 0.30 MILLIMETERS :[GX 045 DIM MIN. NDM. MAX. D E Di A 0.50 0.55 0.60 k1 0.17 0.22 0.27 c 0.08 0.13 0.18 1.80 D 1.50 1.60 1.70 E 1.10 1.20 1.30 D e 0.50 BSC L 0.10 0.20 0.30 0.50 PITCH H: 1.50 1.60 1.70 RECEIMMENDED MDUNTING FDDTPRINTIIE :- For mamanm lnfornnflan on our Phirrep s‘ro‘tegy and somermq demfls, please download the UN seniconuucmr Soldering and Mowmng Technlquas RBFBrsnca Mnnum, smugnkwn ON Semmunduclm and J are Mademavks a1 Semcanduclur Campunenls lnduslnes Lu: 0173 ON Semmanduclar Dr 115 aaaaaanaa 1n the unnaa Slates andJnv mhev commas ON Semmunduclar vesewes me th| In make changes wurmm mnna. nanaa In any prnduns nanan ON Semwnduc‘nv makes m7 wavvamy represenlalmn m guarantee regardmg the sumammy a1 1L; manuals 1m any pamcu‘av purpase nnv dues ON Semmnnduclm assume any Mammy ansmg 01AM me apphcahan m use a1 any pmdudnv c1rcu1| and saaanaauy mscIam‘s any and au Mammy mcmdmg w1|hw|hmma|mn spasm cansequenha‘ m madenla‘ damages ON Sermmnduclar dues nnl aanyay any hcense under 115 pa|em thls nar xna ngma av n|hers
SOT563, 6 LEAD
CASE 463A
ISSUE H
DATE 26 JAN 2021
SCALE 4:1
1
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON11126D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOT563, 6 LEAD
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
LE 11 LE 21 LE 3. PIN l. EMITTER 1 PIN l. EMITTER 1 PIN l. CATHDDE l a. EASE 1 2. EMITTER 2 2. CATHDDE 1 3. CEILLECTEIR 2 3. EASE 2 3. ANDDE/ANEIDE E 4. EMITTER 2 4. EDLLECTDR 2 4. CATHDDE 2 5. EASE 2 5. BASE 1 5 CATHDDE 2 s. CEILLECTEIR 1 s. CEILLECTEIR 1 s. ANDDE/ANDDE 1 ,1 ,1 ,1 511112 41 STYLE 51 STYLE 51 ‘L U U FIN 1. CEILLECTDR FIN 1 CATHDDE PIN 1 CATHDDE 2. CEILLECTEIR 2. CATHDDE 2. ANDDE 3. EASE 3. ANDDE 3 CATHDDE 4. EMITTER 4. ANDDE 4. CATHDDE 5. CEILLECTEIR 5. CATHDDE 5. CATHDDE S. CEILLECTEIR S. CATHDDE S. CATHDDE $11112 7. STYLE 9. STYLE 9. PIN 1. CATHDDE FIN 1. 1mm FIN 1. SEIURCE 1 2. ANEIDE E. DRAIN E. GATE 1 3. CATHDDE :. GATE 3. DRAIN 2 4. CATHDDE 4. SEIURCE 4 SEIURCE 2 5. ANDDE 5. 1mm 5. GATE 2 s. CATHDDE 5. 1mm 5 DRAIN 1 STYLE 1m STYLE 11 PIN 1. CATHDDE 1 PIN 1. EMITTER 2 2. WC 2. EASE a 3. CATHDDE 2 3. CEILLECTEIR 1 4. ANDDE 2 4. EMITTER 1 5. N/C 5. EASE 1 s. ANDDE 1 e. CEILLECTEIR 2 ON Semcunduclm and J ana hademavks ac Semcanduclur Cnmpunenls lnduslnes. 11c aaa ON Semcanduclar an 115 suhs1d1ar1es1n 1na Umled Slates andJnl mhev commas ON Semcunduclar naaaayaa me mm In make changes wuhwl Yunnan nanaa In any panama nanan 0N Semwnduc‘m makes na walvamy. represenlalmn an guarantee nagamnna the aanaanny a! a; manuals a. any pamcu‘av aunaaaa nan dues ON Semmnnduclm aaaama any Mammy ansmg mun! 1na apphcshan m use a4 any pmdudnv c1rcu1| and aaaanaany manna any and an Mammy Mcmdmg mmam hmmahun aaaaa aanaaaaanna m .naaanua damages ON Sermmnduclar dues na1aanyay any hcense under .15 pa|eml1ghls nan 1na nama av n|hers
SOT563, 6 LEAD
CASE 463A
ISSUE H
DATE 26 JAN 2021
XX = Specific Device Code
M = Month Code
G= PbFree Package
XX MG
GENERIC
MARKING DIAGRAM*
1
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON11126D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOT563, 6 LEAD
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SWLEA ENA EMATTEEA EASE A CGLLEcToE 2 EMATTEE2 EASE 2 CGLLEcToE A SWLE4 ENA CDLLEcToE CDLLEcToE 3 EASE 4 EMATTEE 5 CDLLEcToE CDLLEcToE SWLE7 ENA CATNGDE 2 ANDDE 3 CATNGDE 4 CATNGDE 5 ANDDE a CATNGDE SWLEAD ENA CATNGDEA 2 N10 3 CATNGDE2 4 ANDDE2 5 N10 5 ANDDEA nl‘nr—I 6‘54 7+7 E 1‘23; |_I|+II_I PVIEW STVLE 2 EN A EMATTEE A 2 EMATTEE2 a EASE2 4 CDLLEcToE2 5 EASEA CDLLEcToEA STVLES ENA CATHODE CATHODE a ANDDE 4 ANDDE 5 CATHODE CATHODE STVLEB ENA DEAN 2 DEAN a GATE 4 SOURCE 5 DEAN 5 DEAN ‘ [17 4 cafle SIDE VIEW STVLE 3 PIN A a 4 5 cAnADDE A cAnADDE A ANODEAANoDE 2 cAnADDE 2 cAnADDE 2 ANODEAANoDE A STVLE 5 PIN A a 4 5 cAnADDE ANoDE cAnADDE cAnADDE cAnADDE cAnADDE STVLE 9 PIN A 2 a 4 5 5 SOURCE A GATE A DEAN 2 SGchE 2 GATE 2 DEAN A I)" Semiwndudw" NGTES A DAMENSAGNNG AND TOLEEANCNG PER ASME W4 5M Ass» 2 CONTEOLLNG DAMENSAGN MALLAMETEES 3 MAXIMUM LEAD THACKNESS NcLuDES LEAD ENASN IHICKNESS MNAMUM LEAD THACKNESS AS IHE MNAMDM IHICKNESS GE EASE MATEEAAL o DAMENSAGNS D AND E Do NDT ANCLuDE MOLD FLASH‘ EEGTEuSAoNS oE GATE EuEES MILLIMEYERS DIM MIN MOM MAX A 034 037 um I: DID nAs Am: C 007 0A2 0A7 D 095 Ann Ans E D75 nan 055 e DESESc ME 095‘ ADM Ans EE A A GENERIC MARKING DIAGRAM‘ XM o A u X : Specmc Device Code M : Month Code Erma InIormaIion As gananc. Please relel to device aaAa sheeA Am acAuaA pan markmg. Ph-Free indAcamn “Q“ m rnAcmaoA “ may or may noA be present. ON SamAaanauamA and J ave Irademavks DI Sanaanaaamr magma Anaasmas. LLC aaa ON amaanauaar a .a saaaaana; n ma Dnaa Slates anaAmAEaA manna ON SemAcunduchr vesewes AEa "gm to make changes quauA lunher nanaa to any praduns Eanan GN SamAwnaaaAaA makes m7 wananAy. represenlalmn av guarantee regardmg AEe auAAaEAAAAy DI AIS mama Am any panAauAaA purpase nay does ON Semumnduclm assume any AAaEAAAAy snsmg unIaI me appIAcsImn ar use aA any pmdudm clrcull ana spaaAncaAAy dlscIaAms any and an AAaEAAAAy AnaAaaAng WAmaaA AAnAAAaAAan spemak aanaaaaanAAaA ar AncAaanAaA damages oN SanAAmnauaAar dues naI away any hcense under AIS paAenA nghls Ivar ma
SOT963
CASE 527AD01
ISSUE E
DATE 09 FEB 2010
SCALE 4:1
GENERIC
MARKING DIAGRAM*
X = Specific Device Code
M = Month Code
*This information is generic. Please refer
to device data sheet for actual part
marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
DIM MIN NOM MAX
MILLIMETERS
A0.34 0.37 0.40
b0.10 0.15 0.20
C0.07 0.12 0.17
D0.95 1.00 1.05
E0.75 0.80 0.85
e0.35 BSC
0.95 1.00 1.05
HE
E
D
C
A
HE
123
456
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
XM
1
STYLE 1:
PIN 1. EMITTER 1
2. BASE 1
3. COLLECTOR 2
4. EMITTER 2
5. BASE 2
6. COLLECTOR 1
STYLE 2:
PIN 1. EMITTER 1
2. EMITTER2
3. BASE 2
4. COLLECTOR 2
5. BASE 1
6. COLLECTOR 1
STYLE 3:
PIN 1. CATHODE 1
2. CATHODE 1
3. ANODE/ANODE 2
4. CATHODE 2
5. CATHODE 2
6. ANODE/ANODE 1
STYLE 4:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 6:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 5:
PIN 1. CATHODE
2. CATHODE
3. ANODE
4. ANODE
5. CATHODE
6. CATHODE
STYLE 7:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. ANODE
6. CATHODE
STYLE 8:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 9:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 10:
PIN 1. CATHODE 1
2. N/C
3. CATHODE 2
4. ANODE 2
5. N/C
6. ANODE 1
X
Y
TOP VIEW
SIDE VIEW
e
b
X0.08
6X
Y
BOTTOM VIEW
6X
0.35
PITCH
1.20
0.20
DIMENSIONS: MILLIMETERS
RECOMMENDED
PACKAGE
OUTLINE
MOUNTING FOOTPRINT
L0.19 REF
L2 0.05 0.10 0.15
L
6X
L2
6X
6X
0.35
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON26456D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SOT963, 1X1, 0.35P
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a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
www.onsemi.com
1
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ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
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