TPS2543~ Datasheet by Texas Instruments

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I TEXAS INSTRUMENTS mm LO
OUT
GND
FAULT
ILIM_LO
EN
RILIM_LO
RSTATUS
(10 kW)
Power Switch EN
4.5V 5.5V
TPS2543
0.1 uF
CUSB
Fault Signal
DM_IN
DP_IN
VBUS
D-
D+
GND
USB
Connector
To Portable Device à
Power Bus
CTL1
CTL2
CTL3
ILIM_SEL
ILIM Select
DM_OUT
DP_OUT To Host Controller à
Mode Select I/O
IN
STATUS
STATUS Signal RILIM_HI
ILIM_HI
RFAULT
(10 kW)
1
2
3
4
5 6 7 8
9
10
11
12
13141516
Thermal Pad
IN
DM_OUT
DP_OUT
ILIM_SEL
EN
CLT1
CLT2
CLT3
OUT
DM_IN
DP_IN
STATUS
ILIM_HI
ILIM_LO
GND
FAULT
TPS2543
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USB Charging Port Controller and Power Switch with Load Detection
Check for Samples: TPS2543
1FEATURES DESCRIPTION
The TPS2543 is a USB charging port controller and
D+/D– CDP/DCP Modes per USB Battery power switch with an integrated USB 2.0 high-speed
Charging Specification 1.2 data line (D+/D–) switch. The TPS2543 provides the
D+/D– Shorted Mode per Chinese electrical signatures on D+/D– to support the
Telecommunication Industry Standard YD/T following charging schemes:
1591-2009 USB Battery Charging Specification 1.2;
D+/D– Divider Modes 2.0V/2.7V and 2.7/2.0V Chinese Telecom Standard YD/T 1591-2009;
Compliant with 1A and 2A Apple Mobile Digital Divider Mode, Compliant with Apple iPod, iPhone
Devices (1A), and iPad (2A) Mobile Digital Devices.(1)
Automatic Selection of D+/D– Mode for an The TPS2543 can be configured to automatically
Attached Device select the D+/D– mode needed to charge an attached
Supports Sleep-Mode Charging and device. The TPS2543 provides load detection via the
Mouse/Keyboard (Low-Speed Only) Wake Up STATUS pin that allows for both power supply control
in S4/S5 charging and the ability to manage port
Load Detection for Both Power Supply Control power in a multi-port application. Additionally, system
in S4/S5 Charging and Port Power wake up (from S3) with a mouse/keyboard (low
Management in all Charge Modes speed only) is fully supported in the TPS2343.
Compatible with USB 2.0 and 3.0 Power Switch The TPS2543 73-mpower-distribution switch is
Requirements intended for applications where heavy capacitive
• 73-mΩ(typ) High-Side MOSFET loads and short-circuits are likely to be encountered.
Adjustable Current-Limit up to 3.0 A (typ) Two programmable current thresholds provide
flexibility for setting current limits and load detect
Operating Range: 4.5 V to 5.5 V thresholds.
Drop-In Compatible with TPS2540/40A
Available in 16-Pin QFN (3x3) Package
UL Listed and CB File No. E169910
APPLICATIONS
USB Ports (Host and Hubs)
Notebook Desktop PCs (1) Apple, iPod, iPhone, and iPad are trademarks of Apple Inc.,
Universal Wall Charging Adapters registered in the U.S. and other countries.
TPS2543 RTE PACKAGE AND TYPICAL APPLICATION DIAGRAM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
l TEXAS INSTRUMENTS
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TAPACKAGE DEVICE TOP-SIDE MARKING
–40°C to 125°C QFN16 TPS2543 2543
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range, voltages are referenced to GND (unless otherwise noted)
LIMIT UNIT
Voltage range IN, EN, ILIM_LO, ILIM_HI, FAULT, STATUS, ILIM_SEL, –0.3 to 7 V
CTL1, CTL2, CTL3, OUT
IN to OUT –7 to 7
DP_IN, DM_IN, DP_OUT, DM_OUT –0.3 to (IN + 0.3) or 5.7
Input clamp current DP_IN, DM_IN, DP_OUT, DM_OUT ±20 mA
Continuous current in SDP or CDP DP_IN to DP_OUT or DM_IN to DM_OUT ±100 mA
mode
Continuous current in BC1.2 DCP DP_IN to DM_IN ±50 mA
mode
Continuous output current OUT Internally limited
Continuous output sink current FAULT, STATUS 25 mA
Continuous output source current ILIM_LO, ILIM_HI Internally limited mA
ESD rating HBM 2 kV
HBM wrt GND and each other, DP_IN, DM_IN 8
CDM 500 V
Operating junction temperature, TJ–40 to Internally limited °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS2543
THERMAL METRIC(1) UNITS
RTE (16 PIN)
θJA Junction-to-ambient thermal resistance 53.4
θJCtop Junction-to-case (top) thermal resistance 51.4
θJB Junction-to-board thermal resistance 17.2 °C/W
ψJT Junction-to-top characterization parameter 3.7
ψJB Junction-to-board characterization parameter 20.7
θJCbot Junction-to-case (bottom) thermal resistance 3.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
voltages are referenced to GND (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage, IN 4.5 5.5 V
Input voltage, logic-level inputs, EN, CTL1, CTL2, CTL3, ILIM_SEL 0 5.5 V
Input voltage, data line inputs, DP_IN, DM_IN, DP_OUT, DM_OUT 0 VIN V
VIH High-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL 1.8 V
VIL Low-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL 0.8 V
Continuous current, data line inputs, SDP or CDP mode, DP_IN to DP_OUT, DM_IN to ±30 mA
DM_OUT
Continuous current, data line inputs, BC1.2 DCP mode, DP_IN to DM_IN ±15 mA
IOUT Continuous output current, OUT 0 2.5 A
Continuous output sink current, FAULT, STATUS 0 10 mA
RILIM_XX Current-limit set resistors 16.9 750 kΩ
TJOperating virtual junction temperature –40 125 °C
ELECTRICAL CHARACTERISTICS
Unless otherwise noted: –40 TJ125°C, 4.5 V VIN 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. RFAULT =
RSTATUS = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages
are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SWITCH
TJ= 25°C, IOUT = 2 A 73 84
RDS(on) On resistance(1) –40°C TJ85°C, IOUT = 2 A 73 105 mΩ
–40°C TJ125°C, IOUT = 2 A 73 120
trOUT voltage rise time 0.7 1.0 1.60
VIN = 5 V, CL= 1 µF, RL= 100 Ω(see Figure 23 and ms
Figure 24)
tfOUT voltage fall time 0.2 0.35 0.5
ton OUT voltage turn-on time 2.7 4
VIN = 5V, CL= 1 µF, RL= 100 Ω(see Figure 23 and ms
Figure 25)
toff OUT voltage turn-off time 1.7 3
VOUT = 5.5 V, VIN = VEN = 0 V, –40 TJ85°C,
IREV Reverse leakage current 2 µA
Measure IOUT
DISCHARGE
RDCHG OUT discharge resistance VOUT = 4 V, VEN = 0 V 400 500 630 Ω
tDCHG OUT discharge hold time Time VOUT < 0.7 V (see Figure 26) 205 310 450 ms
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account
separately.
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted: –40 TJ125°C, 4.5 V VIN 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. RFAULT =
RSTATUS = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages
are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EN, ILIMSEL, CTL1, CTL2, CTL3 INPUTS
Input pin rising logic threshold 1 1.35 1.70 V
voltage
Input pin falling logic threshold 0.85 1.15 1.45
voltage
Hysteresis(2) 200 mV
Input current Pin voltage = 0 V or 5.5 V –0.5 0.5 µA
ILIMSEL CURRENT LIMIT
VILIM_SEL = 0 V, RILIM_LO = 210 kΩ205 240 275
VILIM_SEL = 0 V, RILIM_LO = 80.6 kΩ575 625 680
IOS OUT short circuit current limit(3) VILIM_SEL = 0 V, RILIM_LO = 22.1 kΩ2120 2275 2430 mA
VILIM_SEL = VIN, RILIM_HI = 20 kΩ2340 2510 2685
VILIM_SEL = VIN, RILIM_HI = 16.9 kΩ2770 2970 3170
Response time to OUT short- VIN = 5.0 V, R = 0.1Ω, lead length = 2 inches (see
tIOS 1.5 µs
circuit(2) Figure 27)
SUPPLY CURRENT
IIN_OFF Disabled IN supply current VEN = 0 V, VOUT = 0 V, –40 TJ85°C 2 µA
VCTL1 = VCTL2 = VIN, VCTL3 = 0 V or VIN, VILIM_SEL = 0 V 155 210
VCTL1 = VCTL2 = VIN, VCTL3 = 0V, VILIM_SEL = VIN 175 230
IIN_ON Enabled IN supply current µA
VCTL1 = VCTL2 = VIN, VCTL3 = VIN, VILIM_SEL = VIN 185 240
VCTL1 = 0V, VCTL2 = VCTL3 = VIN 205 260
UNDERVOLTAGE LOCKOUT
VUVLO IN rising UVLO threshold voltage 3.9 4.1 4.3 V
Hysteresis(2) 100 mV
FAULT
Output low voltage IFAULT = 1 mA 100 mV
Off-state leakage VFAULT = 6.5 V 1 µA
Over current FAULT rising and 5 8.2 12 ms
falling deglitch
STATUS
Output low voltage ISTATUS = 1 mA 100 mV
Off-state leakage VSTATUS = 6.5 V 1 µA
THERMAL SHUTDOWN
Thermal shutdown threshold 155
Thermal shutdown threshold in 135 °C
current-limit
Hysteresis(2) 20
(2) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
(3) Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account
separately.
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ELECTRICAL CHARACTERISTICS, HIGH-BANDWIDTH SWITCH
Unless otherwise noted: –40 TJ125°C, 4.5 V VIN 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. RFAULT =
RSTATUS = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ, Positive currents are into pins. Typical values are at 25°C. All voltages
are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HIGH-BANDWIDTH ANALOG SWITCH
VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA 2 4
DP/DM switch on resistance Ω
VDP/DM_OUT = 2.4 V, IDP/DM_IN = –15 mA 3 6
VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA 0.05 0.15
Switch resistance mismatch between Ω
DP / DM channels VDP/DM_OUT = 2.4 V, IDP/DM_IN = –15 mA 0.05 0.15
VEN = 0 V, VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk-pk,
DP/DM switch off-state capacitance(1) 3 3.6 pF
f = 1 MHz
DP/DM switch on-state capacitance(2) VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk-pk, f = 1 MHz 5.4 6.2 pF
OIRR Off-state isolation(3) VEN = 0 V, f = 250 MHz 33 dB
XTALK On-state cross channel isolation(3) f = 250 MHz 52 dB
VEN = 0 V, VDP/DM_IN = 3.6 V, VDP/DM_OUT = 0 V,
Off state leakage current 0.1 1.5 µA
measure IDP/DM_OUT
BW Bandwidth (–3dB)(3) RL= 50 Ω2.6 GHz
tpd Propagation delay(3) 0.25 ns
Skew between opposite transitions of the
tSK 0.1 0.2 ns
same port (tPHL – tPLH)
(1) The resistance in series with the parasitic capacitance to GND is typically 250 Ω.
(2) The resistance in series with the parasitic capacitance to GND is typically 150 Ω
(3) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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ELECTRICAL CHARACTERISTICS, CHARGING CONTROLLER
Unless otherwise noted: –40 TJ125°C, 4.5 V VIN 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = 0 V, VCTL2 = VCTL3 = VIN.
RFAULT = RSTATUS = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ, Positive currents are into pins. Typical values are at 25°C. All
voltages are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SHORTED MODE VCTL1 = VIN, VCTL2 = VCTL3 = 0V
DP_IN / DM_IN shorting resistance 125 200 Ω
DIVIDER1 MODE
DP_IN Divider1 output voltage 1.9 2.0 2.1 V
DM_IN Divider1 output voltage 2.57 2.7 2.84 V
DP_IN output impedance 8 10.5 12.5 kΩ
DM_IN output impedance 8 10.5 12.5 kΩ
DIVIDER2 MODE IOUT = 1A
DP_IN Divider2 output voltage 2.57 2.7 2.84 V
DM_IN Divider2 output voltage 1.9 2.0 2.1 V
DP_IN output impedance 8 10.5 12.5 kΩ
DM_IN output impedance 8 10.5 12.5 kΩ
CHARGING DOWNSTREAM PORT VCTL1 = VCTL2 = VCTL3 = VIN
VDP_IN = 0.6 V,
VDM_SRC DM_IN CDP output voltage 0.5 0.6 0.7 V
–250 µA < IDM_IN < 0 µA
DP_IN rising lower window thresholdfor
VDAT_REF 0.25 0.4 V
VDM_SRC activation
Hysteresis(1) 50 mV
DP_IN rising upper window thresholdfor
VLGC_SRC 0.8 1 V
VDM_SRC de-activation
hysteresis(1) 100 mV
IDP_SINK DP_IN sink current VDP_IN = 0.6 V 40 70 100 µA
LOAD DETECT – NON POWER WAKE VCTL1 = VCTL2 = VCTL3 = VIN
ILD IOUT rising load detect current threshold 635 700 765 mA
hysteresis(1) 50 mA
tLD_SET Load detect set time 140 200 275 ms
Load detect reset time 1.9 3 4.2 s
LOAD DETECT – POWER WAKE VCTL1 = VCTL2 = 0V, VCTL3 = VIN
IOS_PW Power wake short circuit current limit 32 55 78 mA
IOUT falling power wake reset current 23 45 67 mA
detection threshold
Reset current hysteresis(1) 5 mA
Power wake reset time 10.7 15 20.6 s
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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l TEXAS INSTRUMENTS / /// /// 4/
50
60
70
80
90
100
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
On Resistance (m)
G001
0
0.05
0.1
0.15
0.2
0.25
0.3
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Reverse Leakage Current (µA)
G002
460
480
500
520
540
560
580
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
OUT Discharge Resistance ()
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
G003
0
500
1000
1500
2000
2500
3000
3500
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
OUT Short Circuit Current Limit (mA)
RILIM_LO = 210 k
RILIM_LO = 80.6 k
RILIM_HI = 20 k
RILIM_HI = 16.9 k
G004
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TYPICAL CHARACTERISTICS
POWER SWITCH ON RESISTANCE REVERSE LEAKAGE CURRENT
vs vs
TEMPERATURE TEMPERATURE
Figure 1. Figure 2.
OUT DISCHARGE RESISTANCE OUT SHORT CIRCUIT CURRENT LIMIT
vs vs
TEMPERATURE TEMPERATURE
Figure 3. Figure 4.
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0
0.2
0.4
0.6
0.8
1
1.2
−40 −20 0 20 40 60 80 100
Junction Temperature (°C)
Disabled IN Supply Current (µA)
VIN = 5.5 V
G005
130
140
150
160
170
180
190
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Enabled IN Supply Current (µA)
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
Device configured for SDP
VILIMSEL = 0 V
G006
160
170
180
190
200
210
220
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Enabled IN Supply Current (µA)
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
Device configured for CDP
G007
180
190
200
210
220
230
240
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Enabled IN Supply Current (µA)
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
Device configured for DCP AUTO
G008
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TYPICAL CHARACTERISTICS (continued)
DISABLED IN SUPPLY CURRENT ENABLED IN SUPPLY CURRENT - SDP
vs vs
TEMPERATURE TEMPERATURE
Figure 5. Figure 6.
ENABLED IN SUPPLY CURRENT - CDP ENABLED IN SUPPLY CURRENT - DCP AUTO
vs vs
TEMPERATURE TEMPERATURE
Figure 7. Figure 8.
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0
100
200
300
400
500
600
700
0 1 2 3 4 5 6 7 8 9 10
Sinking Current (mA)
Output Low Voltage (mV)
TJ = −40°C
TJ = 25°C
TJ = 125°C
VIN = 4.5 V
G009
-20
0
Transmission Gain - dB
-20
-10
-15
-5
0.01 1
Frequency - GHz
0.1 10
0
60
XTALK - ON State Cross-Channel Isolation - dB
10
40
20
50
0.01 1
Frequency - GHz
0.1 10
30
80
70
0
60
OIRR - Off State Isolation - dB
10
40
20
50
0.01 1
Frequency - GHz
0.1 10
30
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TYPICAL CHARACTERISTICS (continued)
STATUS AND FAULT OUTPUT LOW VOLTAGE DATA TRANSMISSION CHARACTERISTICS
vs vs
SINKING CURRENT FREQUENCY
Figure 9. Figure 10.
OFF STATE DATA SWITCH ISOLATION ON STATE CROSS-CHANNEL ISOLATION
vs vs
FREQUENCY FREQUENCY
Figure 11. Figure 12.
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l TEXAS INSTRUMENTS Tune (ns) can Time (n5) Gm, \\ \\ \ \ \ \ \\‘ \ \\\ \\
G013
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (ns)
Differential Signal (V)
G014
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (ns)
Differential Signal (V)
600
620
640
660
680
700
720
740
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Current (mA)
IOS - OUT Short Circuit Current Limit
ILD - IOUT Rising Load Detect Threshold
RILIM_LO = 80.6 k
G015
200
205
210
215
220
225
230
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Load Detect Set Time (ms)
G016
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TYPICAL CHARACTERISTICS (continued)
EYE DIAGRAM USING USB COMPLIANCE TEST PATTERN EYE DIAGRAM USING USB COMPLIANCE TEST PATTERN
(with no switch) (with data switch)
Figure 13. Figure 14.
IOUT RISING LOAD DETECT THRESHOLD
AND OUT SHORT CIRCUIT CURRENT LIMIT LOAD DETECT SET TIME
vs vs
TEMPERATURE TEMPERATURE
Figure 15. Figure 16.
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l TEXAS INSTRUMENTS t-nme -1 ms/dw om t- Twme - 1 ms/dlv 5:22 1- Tvne - 2 msldlv m
I
500 mA/div
IN
V
5 V/div
EN
V
2 V/div
OUT
t - Time - 1 ms/div
RLOAD = 5
C = 150 F
Ω
µ
LOAD
G021
52
53
54
55
56
57
58
59
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Power Wake Current Limit (mA)
G017
I
500 mA/div
IN
V
5 V/div
EN
V
5 V/div
/FAULT
t - Time - 2 ms/div
RILM_LO = 80.6 kΩ
G023
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TYPICAL CHARACTERISTICS (continued)
POWER WAKE CURRENT LIMIT
vs
TEMPERATURE TURN-ON RESPONSE
Figure 17. Figure 18.
TURN-OFF RESPONSE DEVICE ENABLED INTO SHORT CIRCUIT
Figure 19. Figure 20.
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l TEXAS INSTRUMENTS "WV/Ly.“ 1 , , WWW WW t- Twme - 5 ms/dw m t- Twme - z ms/dw m
I
1 A/div
IN
V
5 V/div
EN
V
5 V/div
/FAULT
t - Time - 5 ms/div
RILM_HI = 20 kΩ
G024
I
2 A/div
IN
V
2 V/div
OUT
V
5 V/div
/FAULT
t - Time - 2 ms/div
RILIM_HI
LOAD
LOAD
= 20 k
R = 5
C = 150 F
Ω
Ω
µ
G025
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TYPICAL CHARACTERISTICS (continued)
DEVICE ENABLED INTO SHORT CIRCUIT - THERMAL
CYCLING SHORT CIRCUIT to FULL LOAD RECOVERY
Figure 21. Figure 22.
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10%
90%
VOUT
trtf
OUT
RLCL
5 V
VOUT
0 V
tDCHG
VEN
VOUT
ton
50 % 50 %
toff
90 %
10 %
tIOS
IOUT
IOS
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PARAMETER MEASUREMENT DESCRIPTION
Figure 23. OUT Rise/Fall Test Load Figure 24. Power-On and Off Timing
Figure 25. Enable Timing, Active High Enable Figure 26. OUT Discharge During Mode Change
Figure 27. Output Short Circuit Parameters
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1
2
3
4
5 6 7 8
9
10
11
12
13141516
Thermal Pad
IN
DM_OUT
DP_OUT
ILIM_SEL
EN
CLT1
CLT2
CLT3
OUT
DM_IN
DP_IN
STATUS
ILIM_HI
ILIM_LO
GND
FAULT
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DEVICE INFORMATION
TPS2543 RTE PACKAGE
(Top View)
PIN FUNCTIONS
NO. NAME TYPE(1) DESCRIPTION
1 IN P Input voltage and supply voltage; connect 0.1 μF or greater ceramic capacitor from IN to GND as close
to the device as possible
2 DM_OUT I/O D– data line to USB host controller
3 DP_OUT I/O D+ data line to USB host controller
4 ILIM_SEL I Logic-level input signal used to control the charging mode, current limit threshold, and load detection;
see the control truth table
5 EN I Logic-level input for turning the power switch and the signal switches on/off; logic low turns off the signal
and power switches and holds OUT in discharge.
6 CTL1 I
7 CTL2 I Logic-level inputs used to control the charging mode and the signal switches; see the control truth table
8 CTL3 I
9 STATUS O Active-low open-drain output, asserted in load detection conditions
10 DP_IN I/O D+ data line to downstream connector
11 DM_IN I/O D– data line to downstream connector
12 OUT P Power-switch output
13 FAULT O Active-low open-drain output, asserted during over-temperature or current limit conditions
14 GND P Ground connection
15 ILIM_LO I External resistor used to set the low current-limit threshold and the load detection current threshold. A
resistor to ILIM_LO is optional; see Current-Limit Settings in DETAILED DESCRIPTION.
16 ILIM_HI I External resistor used to set the high current-limit threshold
NA PowerPAD Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect to GND
plane.
(1) G = Ground, I = Input, O = Output, P = Power
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C] «a» ___'I I ‘7 T; % I .———— ——-——> L. [J—’ []—> [J—F {L} TEXAS INSTRUMENTS
Disable + UVLO+Discharge
Driver
CS
Current
Limit Charge
Pump
UVLO Thermal
Sense
8-ms Deglitch
OTSD
Current
Sense
IN
EN
ILIM_HI
CTL1
DP_IN
DM_IN
OUT
GND
FAULT
8-ms Deglitch
(falling edge)
Current Limit
select
ILIM_LO
ILIM_SEL
STATUS
DP_OUT
DM_OUT
CTL2
CTL3
Logic
control
CDP
Detection
DCP
Detection Auto-Detection
Divider
Mode
ILIM_SEL
Discharge
discharge
LD cur set
LD cur set
Discharge
OC
OC
TPS2543
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FUNCTIONAL BLOCK DIAGRAM
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DETAILED DESCRIPTION
Overview
The following overview references various industry standards. It is always recommended to consult the most up-
to-date standard to ensure the most recent and accurate information. Rechargeable portable equipment requires
an external power source to charge its batteries. USB ports are a convenient location for charging because of an
available 5 V power source. Universally accepted standards are required to make sure host and client-side
devices operate together in a system to ensure power management requirements are met. Traditionally, USB
host ports following the USB 2.0 specification must provide at least 500 mA to downstream client-side devices.
Because multiple USB devices can be attached to a single USB port through a bus-powered hub, it is the
responsibility of the client-side device to negotiate its power allotment from the host to ensure the total current
draw does not exceed 500 mA. In general, each USB device is granted 100 mA and may request more current in
100 mA unit steps up to 500 mA. The host may grant or deny based on the available current.
Additionally, the success of USB has made the mini-USB connector a popular choice for wall adapter cables.
This allows a portable device to charge from both a wall adapter and USB port with only one connector. One
common difficulty has resulted from this. As USB charging has gained popularity, the 500 mA minimum defined
by USB 2.0 or 900 mA for USB 3.0 has become insufficient for many handset and personal media players which
need a higher charging rate. Wall adapters can provide much more current than 500mA/900mA. Several new
standards have been introduced defining protocol handshaking methods that allow host and client devices to
acknowledge and draw additional current beyond the 500mA/900mA minimum defined by USB 2.0/3.0 while still
using a single micro-USB input connector.
The TPS2543 supports three of the most common protocols:
USB Battery Charging Specification BC1.2
Chinese Telecommunications Industry Standard YD/T 1591-2009
Divider Mode
All three methods have similarities and differences, but the biggest commonality is that all three define three
types of charging ports that provide charging current to client-side devices. These charging ports are defined as:
Standard Downstream Port (SDP)
Charging Downstream Port (CDP)
Dedicated Charging Port (DCP)
BC1.2 defines a Charging Port as a downstream facing USB port that provides power for charging portable
equipment.
Table 1 shows the differences between these ports according to BC1.2 .
Table 1. Operating Modes
SUPPORT USB MAX. ALLOWABLE CURRENT
PORT TYPE 2.0 COMMUNICATION DRAW BY PORTABLE DEVICE (A)
SDP (USB 2.0) Yes 0.5
SDP (USB 3.0) Yes 0.9
CDP Yes 1.5
DCP No 1.5
BC1.2 defines the protocol necessary to allow portable equipment to determine what type of port it is connected
to so that it can allot its maximum allowable current draw. The hand-shaking process has two steps. During step
one, the primary detection, the portable equipment outputs a nominal 0.6-V output on its D+ line and reads the
voltage input on its D- line. The portable device concludes it is connected to an SDP if the voltage is less than
the nominal data detect voltage of 0.3 V. The portable device concludes that it is connected to a Charging Port if
the D- voltage is greater than the nominal data detect voltage of 0.3 V and less than 0.8 V. The second step, the
secondary detection, is necessary for portable equipment to determine between a CDP and a DCP. The portable
device outputs a nominal 0.6 V output on its D- line and reads the voltage input on its D+ line. The portable
device concludes it is connected to a CDP if the data line being read remains less than the nominal data detect
voltage of 0.3 V. The portable device concludes it is connected to a DCP if the data line being read is greater
than the nominal data detect voltage of 0.3V and less than 0.8 V.
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2 V
USB
Connector
D -
D +
VBUS
Device Side
D- Out
D+ Out
CDP
Detect
Auto
Detect
2.7 V
TPS2543
<200W
Host Side
TPS2543
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SLVSBA6 FEBRUARY 2012
Standard Downstream Port (SDP) USB 2.0/USB 3.0
An SDP is a traditional USB port that follows USB 2.0/3.0 protocol and supplies a minimum of 500 mA/900 mA
per port. USB 2.0/3.0 communications is supported, and the host controller must be active to allow charging.
Charging Downstream Port (CDP)
A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5 A per port. It provides power and
meets USB 2.0 requirements for device enumeration. USB 2.0 communications is supported, and the host
controller must be active to allow charging. What separates a CDP from an SDP is the host-charge handshaking
logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and allows for
additional current draw by the client device.
The CDP hand-shaking process is two steps. During step one the portable equipment outputs a nominal 0.6 V
output on its D+ line and reads the voltage input on its D- line. The portable device concludes it is connected to
an SDP if the voltage is less than the nominal data detect voltage of 0.3 V. The portable device concludes that it
is connected to a Charging Port if the D- voltage is greater than the nominal data detect voltage of 0.3V and less
than 0.8 V.
The second step is necessary for portable equipment to determine between a CDP and a DCP. The portable
device outputs a nominal 0.6 V output on its D- line and reads the voltage input on its D+ line. The portable
device concludes it is connected to a CDP if the data line being read remains less than the nominal data detect
voltage of 0.3 V. The portable device concludes it is connected to a DCP if the data line being read is greater
than the nominal data detect voltage of 0.3V and less than 0.8 V.
Dedicated Charging Port (DCP)
A DCP only provides power and does not provide data connection to an upstream port. A DCP is identified by
the electrical characteristics of its data lines. The TPS2543 emulates two common charging standards namely,
BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591-2009, and one brand unique DCP
charging scheme which will be referred to as Divider scheme.
DCP BC 1.2 and YD/T 1591-2009
Both standards defines that the D+ and D- data lines should be shorted together with a maximum series
impedance of 200 Ω. This is shown in Figure 28.
Figure 28. DCP Supporting BC 1.2/YD/T 1591-2009
DCP Divider Charging Scheme
There are two Divider charging schemes supported by the device, Divider 1 and Divider 2 as shown in Figure 29
and Figure 30. In Divider 1 charging scheme the device applies 2.0V and 2.7V to D+ and D- data line
respectively. This is reversed in Divider 2 mode shown in Figure 30.
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l TEXAS INSTRUMENTS "9
2 V
USB
Connector
D -
D +
VBUS
Device Side
D- Out
D+ Out
CDP
Detect
Auto
Detect
2.7 V
Host Side
TPS2543
CDP
Detect
Auto
Detect
D- Out
D+ Out
2 V
USB
Connector
D -
D +
VBUS
Device Side
2.7 V
Host Side
TPS2543
Divider 1/2
D -
D +
From Charging
Peripheral
TPS2543
To USB 2.0 Host
High BW Data Line SW
Controlled by CTL/EN pins
BC1.2 CDP/SDP
BC1.2 DCP
DCP Auto
TPS2543
SLVSBA6 FEBRUARY 2012
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Figure 29. DCP Divider 1 Scheme
Figure 30. Divider 2 Scheme
Divider 1 voltage configuration is required for 1A (max) iPhone device charging while Divider 2 will allow fast
charging iPAD devices at 2.1A.
DCP Auto Mode
The TPS2543 integrates an auto-detect feature that supports the above DCP schemes. It starts in Divider 1
scheme, if a BC1.2 or YD/T 1591-2009 compliant device is attached, the TPS2543 responds by discharging
OUT, turning back ON the power switch and operating in BC1.2 DCP. It then stays in that mode until the device
releases the data line, in which case it goes back to Divider Mode.
Also, the TPS2543 will automatically switch between the Divider 1 and Divider 2 schemes based on charging
current drawn by the connected device. Initially the device will set the data lines to Divider 1 mode. If charging
current of >750mA is measured by the TPS2543 it switches to Divider 2 scheme and test to see if the peripheral
device will still charge at a high current. If it does then it stays in Divider 2 scheme otherwise it will revert to
Divider 1 scheme.
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DCP Forced Shorted / DCP Forced Divider 1
In this mode the device is permanently set to one of the DCP schemes (BC 1.2/ YD/T 1591-2009 or Divider 1) as
commanded by its control pin setting per device truth table.
High-Bandwidth Data Line Switch
The TPS2543 passes the D+ and D- data lines through the device to enable monitoring and handshaking while
supporting charging operation. A wide bandwidth signal switch is used, allowing data to pass through the device
without corrupting signal integrity. The data line switches are turned on in any of CDP or SDP operating modes.
The EN input also needs to be at logic High for the data line switches to be enabled.
NOTE
1. While in CDP mode, the data switches are ON even while CDP handshaking is occurring.
2. The data line switches are OFF if EN or all CTL pins are held low, or if in DCP mode. They are not
automatically turned off if the power switch (IN to OUT) is in current limit.
3. The data switches are for USB 2.0 differential pair only. In the case of a USB 3.0 host, the super speed
differential pairs must be routed directly to the USB connector without passing through the TPS2543.
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l TEXAS INSTRUMENTS Note
Reset
DCH
1111
110X/
010X
Discharge
(310 ms)
SDP1
CDP
Not SDP2
DCH
Done
DCP Forced
DCP_SHORT/
DCP_DIVIDER
DCP Auto
DCP_Auto
DCH/SDP
CDP
DCH/SDP/
CDP
Note:
1) All shaded boxes are device charging modes
2) See below table for CTL settings corresponding to
flow line conditions
3) Mouse / keyboard wake function not shown
Initial
Not SDP1
Flow Line Condition CTL1 CTL2 CTL3 ILIM_SEL
DCH 0 0 0 X
CDP 1 1 1 1
1 1 1 0
1 1 0 X
0 1 0 X
DCP_SHORT 1 0 0 X
DCP_DIVIDER 1 0 1 X
0 1 1 X
0 0 1 X
SDP1
DCP_Auto
Device Control Pins
DCP_Auto
SDP2
SDP2
1110
1111 1110
Not CDP
TPS2543
SLVSBA6 FEBRUARY 2012
www.ti.com
Device Operation
Please refer to the simplified device state diagram in Figure 31. Power-on-reset (POR) holds device in initial
state while output is held in discharge mode. Any POR event will take the device back to initial state. After POR
clears, device goes to the next state depending on the CTL lines as shown in Figure 31.
Figure 31. TPS2543 Charging States
Output Discharge
To allow a charging port to renegotiate current with a portable device, TPS2543 uses the OUT discharge
function. It proceeds by turning off the power switch while discharging OUT, then turning back on the power
switch to reassert the OUT voltage. This discharge function is automatically applied as shown in device state
diagram.
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VOUT
DM_IN High
System in Sleep
CTL1 = 1 within 64ms of
sys wake, TPS2543 stays
in SDP/CDP and mouse
connection is maintained
CTL1 = 0 TPS2543
detects mouse and
ignores going to DCP
Mouse Clicked here
system wakes
V
2 V/div
OUT
V
1 V/div
CTL1
V
1 V/div
DM_IN
TPS2543
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SLVSBA6 FEBRUARY 2012
Mouse/Key Board Wake Function
The TPS2543 supports low speed HID (human interface device like mouse/key board) wake function. It does not
support Full Speed HID. There are two scenarios under which wake on mouse is supported by the TPS2543.
They are:
1. CDP/SDP2 (111X) to DCP/Auto (011X)
2. SDP1 (010X) to DCP/Auto (011X)
Below description illustrates wake on mouse operation for scenario 1, same holds true for scenario 2.
When a low speed compliant device is attached to the TPS2543, charging port D- line will be pulled high in its
idle state (mouse/keyboard not activated). TPS2543 will monitor D- data line continuously. When device is in
CDP (1111) or SDP2 (1110) or SDP1 (010X) mode and system is commanded to go to sleep state, the device
CTL setting is also changed. Assuming it is changed to DCP/Auto, 011X, having previously detected a HID
attachment the device will simply ignore the command to go to DCP/Auto mode and stay in CDP/SDP2 state to
support wake on mouse function. When the USB low speed HID is activated (clicked) while system is in S3
(sleep) mode the high speed switch within the TPS2543 allows the transfer of signal from the HID device to the
USB host. The USB host subsequently wakes the system and changes CTL setting of the TPS2543 back to
CDP/SDP2 mode. Activating (clicking) the low speed device makes the D- data line go back low momentarily,
this triggers an internal timer within the TPS2543 to count down. If after ~64ms the CTL lines are still set at 011X
(DCP/Auto) the device will immediately switch to DCP/Auto mode and disconnect the mouse from the host. To
prevent this, the CTL setting must be made in less then 64 ms after HID device activation otherwise mouse/KB
function will be lost. See Figure 32 scope plot for an event sequence where mouse connection is maintained at
wake.
Mouse Wake from Sleep
Figure 32. Mouse Wake from Sleep Scope Plot
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Device Truth Table (TT)
Device TT lists all valid bias combinations for the three control pins CTL1-3 and ILIM_SEL pin and their
corresponding charging mode. It is important to note that the TT purposely omits matching charging modes of the
TPS2543 with global power states (S0-S5) as device is agnostic to system power states. The TPS2543 monitors
its CTL inputs and will transition to whatever charging state it is commanded to go to (except when LS HID
device is detected). For example if sleep charging is desired when system is in standby or hibernate state then
user must set TPS2543 CTL pins to correspond to DCP_Auto charging mode per below table. When system is
put back to operation mode then set control pins to correspond to SDP or CDP mode and so on.
Table 2. Truth Table
CURRENT STATUS OUTPUT
CTL1 CTL2 CTL3 ILIM_SEL MODE LIMIT COMMENT
(Active low)
SETTING
0 0 0 0 Discharge NA OFF OUT held low
0 0 0 1 Discharge NA OFF
0 0 1 0 DCP_Auto ILIM_HI OFF Data Lines Disconnected
Data Lines Disconnected and Load Detect
0 0 1 1 DCP_Auto IOS_PW & ILIM_HI(1) DCP load present(2) Function Active
0 1 0 0 SDP ILIM_LO OFF Data Lines connected
0 1 0 1 SDP ILIM_HI OFF
0 1 1 0 DCP_Auto ILIM_HI OFF Data Lines Disconnected
Data Lines Disconnected and Load Detect
0 1 1 1 DCP_Auto ILIM_HI DCP load present(3) Function Active
1 0 0 0 DCP _Shorted ILIM_LO OFF Device Forced to stay in DCP BC 1.2 charging
mode
1 0 0 1 DCP_Shorted ILIM_HI OFF
1 0 1 0 DCP / Divider1 ILIM_LO OFF Device Forced to stay in DCP Divider 1
Charging Mode
1 0 1 1 DCP / Divider1 ILIM_HI OFF
1 1 0 0 SDP ILIM_LO OFF
1 1 0 1 SDP ILIM_HI OFF Data Lines Connected
1 1 1 0 SDP(4) ILIM_LO OFF
1 1 1 1 CDP(4) ILIM_HI CDP load present(5) Data Lines Connected and Load Detect Active
(1) TPS2543 : Current limit (IOS) is automatically switched between IOS_PW and the value set by ILIM_HI according to the Load Detect
Power Wake functionality.
(2) DCP Load present governed by the “Load Detection – Power Wake” limits.
(3) DCP Load present governed by the “Load Detection – Non Power Wake” limits.
(4) No OUT discharge when changing between 1111 and 1110.
(5) CDP Load present governed by the “Load Detection – Non Power Wake” limits and BC 1.2 primary detection.
Table 3 can be used as an aid to program the TPS2543 per system states however not restricted to below
settings only.
Table 3. Control Pin Settings Matched to System Power States
SYSTEM
GLOBAL CURRENT LIMIT
TPS2543 CHARGING MODE CTL1 CTL2 CTL3 ILIM_SEL
POWER SETTING
STATE
S0 SDP 1 1 0 1 or 0 ILIM_HI / ILIM_LO
S0 SDP, no discharge to / from CDP 1 1 1 0 ILIM_LO
CDP, load detection with ILIM_LO + 60mA thresholds or if a
S0 1 1 1 1 ILIM_HI
BC1.2 primary detection occurs
S4/S5 Auto mode, load detection with power wake thresholds 0 0 1 1 ILIM_HI
S3/S4/S5 Auto mode, no load detection 0 0 1 0 ILIM_HI
Auto mode, keyboard/mouse wake up, load detection with
S3 0 1 1 1 ILIM_HI
ILIM_LO + 60 mA thresholds
S3 Auto mode, keyboard/mouse wake-up, no load detection 0 1 1 0 ILIM_HI
S3 SDP, keyboard/mouse wake-up 0 1 0 1 or 0 ILIM_HI / ILIM_LO
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l TEXAS INSTRUMENTS DC-DC Disconnectedl
IN
OUT
5V_DC/DC
5V_LDO
EN
19V
EN
DP
DM
OC
POWER Block
USB Host
Controller
I/O_EN
I/O_Sx
DM_OUT
DP_OUT
FAULT
EN
CTL1
CTL2
CTL3
STATUS
ILIM_SEL
Switches
Power
between LDO
and DC/DC
based on
/STATUS
ILIM_LO
ILIM_HI
DM_IN
DP_OUT
GND
VBUS
D-
D+
GND
USB
Connector
0011
55 mA ilimit
Applied
Hi
CASE I: System in S4 /S 5 no Device Attached
TPS2543
Peripheral
Device
Not
Connected
DC-DC Disconnected/
Shut-Down
LDO Switched-In
Embedded
Controller
TPS2543
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SLVSBA6 FEBRUARY 2012
Load Detect
TPS2543 offers system designers unique power management strategy not available in the industry from similar
devices. There are two power management schemes supported by the TPS5243 via the STATUS pin, they are:
1. Power Wake (PW)
2. Port Power Management (PPM)
Either feature may be implemented in a system depending on power savings goals for the system. In general
Power Wake feature is used mainly in mobile systems like a notebook where it is imperative to save battery
power when system is in deep sleep (S4/S5) state. On the other hand Port Power Management feature would be
implemented where multiple charging ports are supported in the same system and system power rating is not
capable of supporting full charging on multiple ports simultaneously.
Power Wake
Goal of power wake feature is to save system power when system is in S4/S5 state. In S4/S5 state system is in
deep sleep and typically running of the battery; so every “mW” in system power savings will translate to
extending battery life. In this state the TPS2543 will monitor charging current at the OUT pin and provide a
mechanism via the STATUS pin to switch-out the high power DC-DC controller and switch-in a low power LDO
when charging current requirement is <45mA (typ). This would be the case when no peripheral device is
connected at the charging port or if a device has attained its full battery charge and draws <45mA.
As shown in below when system is in S4/S5 mode (0011 setting, see device truth table) and no device is
connected to the charging port (Case I) system runs off a 100mA LDO. Also note TPS2543 will automatically set
its ilimit to 55mA (typ) irrespective of ILIM_LO and ILIM_Hi setting.
Now when a device is attached (CASE II) and draws >55 mA of charging current the TPS2543 will hit its internal
current limit as the current drawn by the attached device will exceed the 55mA ilimit threshold. This will trigger
the device to assert STATUS to turn on the main power supply and discharge OUT for 310ms (typ) to allow the
main power supply to turn on. After the discharge the device will turn back on with current limit set by ILIM_HI. In
Case III as the attached device is being charged the TPS2543 will monitor its load current. STATUS remains
asserted until load current drops below 45mA (typ) for a continuous period of 15s indicating that the attached
device is fully charged. At this point STATUS de-asserts and ilimit is set back to 55mA as shown below.
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l TEXAS INSTRUMENTS CASE II: System in 54/55; Device Attached Conn CASE |l|: System in 54/55; Device Aflached Conn
IN
OUT
5V_DC/DC
5V_LDO
EN
19V
EN
DP
DM
OC
POWER Block
USB Host
Controller
I/O_EN
I/O_Sx
DM_OUT
DP_OUT
FAULT
EN
CTL1
CTL2
CTL3
STATUS
ILIM_SEL
Switches
Power
between LDO
and DC/DC
based on
/STATUS
ILIM_LO
ILIM_HI
DM_IN
DP_OUT
GND
USB
Connector
0011
55mA to ilimit_HI
after OUT discharge
LO
CASE II: System in S4 / S5; Device Attached
and Charging
TPS2543
Peripheral
Device
Connected
LDO Disconnected/
Shut-Down
DC-DC Switched-In
Embedded
Controller
VBUS
D-
D+
GND
IN
OUT
5V_DC/DC
5V_LDO
EN
19V
EN
DP
DM
OC
POWER Block
USB Host
Controller
I/O_EN
I/O_Sx
DM_OUT
DP_OUT
FAULT
EN
CTL1
CTL2
CTL3
STATUS
ILIM_SEL
Switches
Power
between LDO
and DC/DC
based on
/STATUS
ILIM_LO
ILIM_HI
DM_IN
DP_OUT
GND
USB
Connector
0011
Current falls to <45 mA
Ilimit set back to 55mA after 15s
Turns HI after 15s
CASE III: System in S4 /S 5 ; Device Attached
and Charging Completed
TPS2543
Peripheral
Device
Connected
DC-DC Disconnected /
Shut-Down
LDO Switched -In
Embedded
Controller
VBUS
D-
D+
GND
TPS2543
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l TEXAS INSTRUMENTS
#2 Embedded
Controller
/Status
Status
Charging Port
#2
2543
2543
#1
CTL/ILIM
CTL/ILIM
Notebook MB
HDD
Charging Port
#1
Port draws > Load detect setting
1. S3 DCP-Auto/S0 CDP
2. Force to SDP mode
TPS2543
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SLVSBA6 FEBRUARY 2012
Port Power Management
Port power management is for systems that have multiple charging ports but cannot power them all
simultaneously. Goal of this feature is two fold:
1. Enhances user experience since user does not have to search for charging port
2. Power supply only has to be designed for a reasonable charging load
All ports are allowed to broadcast high current charging, charging current limit is based on ILIM_HI resistor
setting. System monitors STATUS to see when high current loads are present. Once allowed number of ports
assert STATUS, remaining ports are toggled to a non-charging port. Non-charging ports are SDP ports with
current limit based on ILIM_LO. TPS2543 allows for a system to toggle between charging and non-charging ports
either with an OUT discharge or without an OUT discharge.
Figure 33. Implementing Port Power Management in a System Supporting Two Charging Ports
Over-Current Protection
When an over-current condition is detected, the device maintains a constant output current and reduces the
output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output has
been shorted before the device is enabled or before VIN has been applied. The TPS2543 senses the short and
immediately switches into a constant-current output. In the second condition, a short or an overload occurs while
the device is enabled. At the instant the overload occurs, high currents may flow for nominally one to two
microseconds before the current-limit circuit can react. The device operates in constant-current mode after the
current-limit circuit has responded. Complete shutdown occurs only if the fault is present long enough to activate
thermal limiting. The device will remain off until the junction temperature cools approximately 20°C and will then
re-start. The device will continue to cycle on/off until the over-current condition is removed.
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l TEXAS INSTRUMENTS 50,500 \umixx
OS_typ
ILIM_XX
50,500
I (mA) = (R (kΩ) + 0.1)
0
500
1000
1500
2000
2500
3000
3500
0 80 160 240 320 400 480 560 640 720 800
Current-Limit Programming Resistor (k)
OUT Short Circuit Current Limit (mA)
Full RILIM_XX Range
G018
TPS2543
SLVSBA6 FEBRUARY 2012
www.ti.com
Current-Limit Settings
The TPS2543 has two independent current limit settings that are each programmed externally with a resistor.
The ILIM_HI setting is programmed with RILIM_HI connected between ILIM_HI and GND. The ILIM_LO setting is
programmed with RILIM_LO connected between ILIM_LO and GND. Consult the Device Truth Table (Table 2) to
see when each current limit is used. Both settings have the same relation between the current limit and the
programming resistor.
RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:
1. ILIM_SEL is always set high
2. Load Detection - Port Power Management is not used
3. Mouse / Keyboard wake function is not used
If conditions 1 and 2 are met but the mouse / keyboard wake function is also desired, it is recommended to use
RILIM_LO < 80.6 kΩ.
The following equation programs the typical current limit:
(1)
RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.
TYPICAL CURRENT LIMIT SETTING
vs
PROGRAMMING RESISTOR
Figure 34.
26 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2543
TEXAS INSTRUMENTS '0 45,661 0 m M7XX '0 55,639 0 |L|M7XX \ I I \ \\ \ \\ \ \§§\ \\ \:\ \\:~~
OS_min 0.98422
ILIM_XX
45,661
I (mA) = - 30
(R (kΩ) + 0.1)
OS_max 1.0143
ILIM_XX
55,639
I (mA) = + 30
(R (kΩ) + 0.1)
0
500
1000
1500
2000
2500
3000
3500
0 10 20 30 40 50 60 70 80 90 100
Current-Limit Programming Resistor (k)
OUT Short Circuit Current Limit (mA)
Min IOS
Typ IOS
Max IOS
Lower RILIM_XX Range
G019
0
100
200
300
400
500
600
100 150 200 250 300 350 400 450 500 550 600 650 700 750
Current-Limit Programming Resistor (k)
OUT Short Circuit Current Limit (mA)
Min IOS
Typ IOS
Max IOS
Upper RILIM_XX Range
G020
TPS2543
www.ti.com
SLVSBA6 FEBRUARY 2012
Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance
limits, both the tolerance of the TPS2543 current limit and the tolerance of the external programming resistor
must be taken into account. The following equations approximate the TPS2543 minimum / maximum current
limits to within a few mA and are appropriate for design purposes. The equations do not constitute part of TI’s
published device specifications for purposes of TI’s product warranty. These equations assume an ideal - no
variation - external programming resistor. To take resistor tolerance into account, first determine the minimum /
maximum resistor values based on its tolerance specifications and use these values in the equations. Because of
the inverse relation between the current limit and the programming resistor, use the maximum resistor value in
the IOS_min equation and the minimum resistor value in the IOS_max equation.
(2)
(3)
CURRENT LIMIT SETTING CURRENT LIMIT SETTING
vs vs
PROGRAMMING RESISTOR PROGRAMMING RESISTOR
Figure 35. Figure 36.
The traces routing the RILIM_XX resistors should be a sufficiently low resistance as to not affect the current-limit
accuracy. The ground connection for the RILIM_XX resistors is also very important. The resistors need to reference
back to the TPS2543 GND pin. Follow normal board layout practices to ensure that current flow from other parts
of the board does not impact the ground potential between the resistors and the TPS2543 GND pin.
FAULT Response
The FAULT open-drain output is asserted (active low) during an over-temperature or current limit condition. The
output remains asserted until the fault condition is removed. The TPS2543 is designed to eliminate false FAULT
reporting by using an internal deglitch circuit for current limit conditions without the need for external circuitry.
This ensures that FAULT is not accidentally asserted due to normal operation such as starting into a heavy
capacitive load. Over-temperature conditions are not deglitched and assert the FAULT signal immediately.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPS2543
l TEXAS INSTRUMENTS
TPS2543
SLVSBA6 FEBRUARY 2012
www.ti.com
Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn-
on threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from large
current surges.
Thermal Sense
The TPS2543 protects itself with two independent thermal sensing circuits that monitor the operating temperature
of the power distribution switch and disables operation if the temperature exceeds recommended operating
conditions. The device operates in constant-current mode during an over-current condition, which increases the
voltage drop across power switch. The power dissipation in the package is proportional to the voltage drop
across the power switch, so the junction temperature rises during an over-current condition. The first thermal
sensor turns off the power switch when the die temperature exceeds 135°C and the part is in current limit. The
second thermal sensor turns off the power switch when the die temperature exceeds 155°C regardless of
whether the power switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns on
after the device has cooled by approximately 20°C. The switch continues to cycle off and on until the fault is
removed. The open-drain false reporting output FAULT is asserted (active low) during an over-temperature
shutdown condition.
28 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2543
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 5-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2543RTER ACTIVE WQFN RTE 16 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS2543RTET ACTIVE WQFN RTE 16 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
REEL DIMENSIONS TAPE DIMENSIONS I‘- KO <—p1—> 99000690 63 63 Cavily Dlmension deswgned to accommodate the componemwwdlh Dimension deswgned to accommodate the component \ength Dlmensian des‘gned [a accommodate the componentlhwckness Overa‘l widlh the carrier tape Ree‘ Dwameler A0 BO K0 — W i P1 Pucn beIween successwe cawa centers i 1 Reel w‘dm (W1) QUADRANTASSIGNMENTS 000 FOR PIN I ORIENTATION IN TAPE 0 O C O O SprocketHoles ,,,,, ‘ User DireCIion 0f Feed \1/ Pocket Quadranfis
PACKAGE OPTION ADDENDUM
14 –Jul – 2012
Pack Material Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1
(mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2543RTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS2543RTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
13.0
Q2
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2543RTER WQFN RTE 16 3000 367.0 367.0 35.0
TPS2543RTET WQFN RTE 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA TACK NC‘*¥:A[ / M hneur dwewsms are 'm muweters Dwmensmn'wg and :o‘eruncmq per ASME W4 SW 1994 Tm: drawing ‘3 sumact m mange w'mm name Quad F‘abuck‘ N07 suds (QTN) nuckuge conhgumtmn ’ne package thermu‘ pad mst be bo‘de'ed tn the buuvd rm Uvevmu‘ and mechun u‘ pevrcmuuce See Lre Product Daiu sree: 0' detufls vegc'd'vg me mused U'e'mu‘ pad dimens v MUS wmn ”who M07 0. {5 TEXAS INSTRUMENTS wwwxi .com
THERMAL PAD MECHANICAL DATA RTE ($7PWQFN7N16) PLASTIC QUAD FLATPACK N07LEAD THERMAL lNFORMATION This package incorporates an exposed thermal pad that is designed ta be attached directly to an external heatsink, The thermal pad must be saldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink, ln addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic lor the device. or alternatively. can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transier tram the integrated circuit (lC). For information on the Quad Flatpack NoiLead (OFN) package and its advantages, refer to Application Report, OFN/SON PCB Attachment, Texas instruments Literature No. SLUA271. This document is available at wwwdti.camt The exposed thermal pad dimensions ior this package are shown in the iollowing illustration. PlN 1 lNDlCATOR C 0,300 iExposed Thermal Pad fie i,66:l:0,10 $13 JUUL <—>—i,66:l:0,10 Bottom Mew Exposed Thermal Pod Dimensions 4206446—5/K 12/12 NOTE: At All linear dimensions are in millimeters {a TEXAS INSTRUMENTS ww.ti.com
LAND PATTERN DATA RTE (scPWQFNcNie) PLASTiC QUAD FLATPACK N07LEAD Exampie Board Layout Exampie Slencil Design (Note E) i«— 0.5 Note D U U U U— j E 1 — i— miis _ 7:19” Cl J 0.2 0.230 ) * ‘4 i( 2.1 3.8 4x0.7 z.i5 3,75 i_) J L_i 0.2 fijm \ \\ «7 2.i5 4» \ — 3,75 —— \\ 68% solder coverage on cenler pad i Non Solder Mask . 1 Defined Pad Euomple Wu Layout Design , “K ~ via pattern may vary due )‘/'/ '\ to layout constraints a Example (”0‘9 D- F) Saider Mask Opening ‘7 1,66 Rim 0,08 \ (Note F) 5x¢0,3 i _ ‘i' Gui—r 0,5 1i66 i,o Pod Geometry 0.07 , (Note C) Q 91 \ Ail around / / 0,5 i« 4» 1'0 AZOSMS—S/F i2/i2 NOTES: A. Ali linear dimensions are in millimelers, a, This drawing is suhiect to change wilnout notice. c, Pualicalion IPCr7351 is recommended for alternate designs. D. This package is designed to he soldered to a thermal pad on the poard. Reier ta Appiicui‘lon Note. Quad FlukPuck Packages. Texas instruments Literalure No. SLUA27i. and also the Product Data Sheets lor speciiic thermal inlarmation, viu requirements, and recommended oaard layout. These documents are aval'iubie at www.ii.cam . E. Laser cutting apertures wiln trapezoidal mails and also rounding corners w‘lii olier better paste release. Customers should contact their poard ossemply site lor stencil design recommendations. Reler lo we 7525 lor stencil design considerations. F. Customers silauid Contact their board fabrication siie for minimum Snider mask web toiemnces between signal pads. {I} TEXAS INSTRUMENTS 5 i .li.cam
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«m» Reel Diameter AD Dimension destgned to accommodate the component with ED Dimension destgned to accommodate the component \engm K0 Dimenslun destgneo to accommodate the component thickness , w OveraH wtdm loe earner tape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2543RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2543RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS2543RTET WQFN RTE 16 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2
TPS2543RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Apr-2015
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2543RTER WQFN RTE 16 3000 367.0 367.0 35.0
TPS2543RTER WQFN RTE 16 3000 338.0 355.0 50.0
TPS2543RTET WQFN RTE 16 250 338.0 355.0 50.0
TPS2543RTET WQFN RTE 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Apr-2015
Pack Materials-Page 2
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