PIC16(L)F1847 Errata Datasheet by Microchip Technology

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6‘ MICROCHIP Programmer > Reconnect Window > Dashboard
2011-2014 Microchip Technology Inc. DS80000525D-page 1
PIC16(L)F1847
The PIC16(L)F1847 family devices that you have
received conform functionally to the current Device
Data Sheet (DS40001453E), except for the anomalies
described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC16(L)F1847 silicon.
Data Sheet clarifications and corrections start on page
7, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1. Using the appropriate interface, connect the
device to the hardware debugger.
2. Open an MPLAB IDE project.
3. Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
4. Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select Programmer >
Reconnect.
b) For MPLAB X IDE, select Window >
Dashboard and click the Refresh Debug
Tool Status icon ( ).
5. Depending on the development tool used, the
part number and Device Revision ID value
appear in the Output window.
The DEVREV values for the various PIC16(L)F1847
silicon revisions are shown in Table 1.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (A3).
Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES
Part Number
DEVICE ID<13:0>(1),(2)
DEV<8:0> Revision ID for Silicon Revision
A2 A3
PIC16F1847 01 0100 100 0 0010 0 0011
PIC16LF1847 01 0100 101 0 0010 0 0011
Note 1: The Device ID is located in the configuration memory at address 8006h.
2: Refer to the “PIC16F/LF1847/PIC12F/LF1840 Memory Programming Specification” (DS41439) for
detailed information on Device and Revision IDs for your specific device.
PIC16(L)F1847 Family
Silicon Errata and Data Sheet Clarification
PIC16(L)F1847
DS80000525D-page 2 2011-2014 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item
Number Issue Summary
Affected
Revisions(1)
A2 A3
Timer1 Timer0 Gate Source 1.1 Toggle mode works improperly. X X
Timer1 T1 Gate Toggle mode 2.1 T1 gate flip-flop does not clear. X
Oscillator HFINTOSC Ready/
Stable bit 3.1 Bits remained set to1’ after initial
trigger. X
Oscillator Clock Switching 3.2 Clock switching can cause a single
corrupted instruction. X
Oscillator Oscillator Start-up
Timer (OST) bit 3.3 OST bit remains set. X
Enhanced Universal Syn-
chronous Asynchronous
Receiver (EUSART)
Auto-Baud Detect 4.1 Auto-Baud Detect may store
incorrect count value in the SPBRG
registers.
X
Enhanced Capture Compare
PWM (ECCP) Full-Bridge PWM 5.1 Pulse width is incorrect. X X
MSSP (Master Synchronous
Serial Port) SPI Master mode 6.1 Buffer Full (BF) bit or MSSP
Interrupt Flag (SSPIF) bit becomes
set half SCK cycle too early.
XX
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
Work around Affected Silicon Revisions Work around Affected con Revisions Work around Affected Silicon Revisions Work around Affected ' con Revisions
2011-2014 Microchip Technology Inc. DS80000525D-page 3
PIC16(L)F1847
Silicon Errata Issues
1. Module: Timer1
1.1 Timer1 Gate Toggle Mode with Timer0 as
Gate Source
Timer1 Gate Toggle mode provides unexpected
results when Timer0 overflow is selected as the
Timer1 gate source. We do not recommend using
Timer0 overflow as the Timer1 gate source while in
Timer1 Gate Toggle mode or when Toggle mode is
used in conjunction with Timer1 Gate Single-Pulse
mode.
Work around
None.
Affected Silicon Revisions
2. Module: Timer1
2.1 Timer1 Gate Toggle mode
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a
Timer1 gate signal. To perform this function, the
Timer1 gate source is routed through a flip-flop
that changes state on every incrementing edge of
the gate signal. Timer1 Gate Toggle mode is
enabled by setting the T1GTM bit of the T1GCON
register. When working properly, clearing either
the T1GTM bit or the TMR1ON bit would also clear
the output value of this flip-flop, and hold it clear.
This is done in order to control which edge is being
measured. The issue that exists is that clearing the
TMR1ON bit does not clear the output value of the
flip-flop and hold it clear.
Work around
Clear the T1GTM bit in the T1GCON register to
clear and hold clear the output value of the flip-flop.
Affected Silicon Revisions
3. Module: Oscillator
3.1 OSCSTAT bits: HFIOFR and HFIOFS
When HFINTOSC is selected, the HFIOFR and
HFIOFS bits will become set when the oscillator
becomes ready and stable. Once these bits are
set, they become “stuck”, indicating that
HFINTOSC is always ready and stable. If the
HFINTOSC is disabled, the bits fail to be cleared.
Work around
None.
Affected Silicon Revisions
3.2 Clock Switching
When switching clock sources between INTOSC
clock source and an external clock source, one
corrupted instruction may be executed after the
switch occurs.
This issue does not affect Two-Speed Start-up or
the Fail-Safe Clock Monitor operation.
Work around
When switching from an external oscillator clock
source, first switch to 16 MHz HFINTOSC. Once
running at 16 MHz HFINTOSC, configure IRCF to
run at desired internal oscillator frequency.
When switching from an internal oscillator
(INTOSC) to an external oscillator clock source,
first switch to HFINTOSC High-Power mode (8
MHz or 16 MHz). Once running from HFINTOSC,
switch to the external oscillator clock source.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A3).
A2 A3
XX
A2 A3
X
A2 A3
X
A2 A3
X
Work around Affected can Revisions Work around
PIC16(L)F1847
DS80000525D-page 4 2011-2014 Microchip Technology Inc.
3.3 Oscillator Start-up Timer (OST) bit
During the Two-Speed Start-up sequence, the
OST is enabled to count 1024 clock cycles. After
the count is reached, the OSTS bit is set, the sys-
tem clock is held low until the next falling edge of
the external crystal (LP, XT or HS mode), before
switching to the external clock source.
When an external oscillator is configured as the
primary clock and Fail-Safe Clock mode is enabled
(FCMEN = 1), any of the following conditions will
result in the Oscillator Start-up Timer (OST) failing
to restart:
•MCLR
Reset
Wake from Sleep
Clock change from INTOSC to Primary Clock
This anomaly will manifest itself as a clock failure
condition for external oscillators which take longer
than the clock failure time-out period to start.
Work around
None.
Affected Silicon Revisions
4. Module: Enhanced Universal
Synchronous Asynchronous
Receiver (EUSART)
4.1 Auto-Baud Detect
When using automatic baud detection (ABDEN),
on occasion, an incorrect count value can be
stored at the end of auto-baud detection in the
SPBRGH:SPBRGL (SPBRG) registers. The
SPBRG value may be off by several counts. This
condition happens sporadically when the device
clock frequency drifts to a frequency where the
SPBRG value oscillates between two different
values. The issue is present regardless of the
baud rate Configuration bit settings.
Work around
When using auto-baud, it is a good practice to
always verify the obtained value of SPBRG, to
ensure it remains within the application
specifications. Two recommended methods are
shown below.
For additional auto-baud information, see
Technical Brief TB3069, “Use of Auto-Baud for
Reception of LIN Serial Communications Devices:
Mid-Range and Enhanced Mid-Range”.
EXAMPLE 1: METHOD 1 – EUSART AUTO-BAUD DETECT WORK AROUND
A2 A3
X
In firmware, define default, minimum and maximum auto-baud (SPBRG) values according to the application requirements.
For example, if the application runs at 9600 baud at 16 MHz then, the default SPBRG value would be (assuming 16-bit/
Asynchronous mode) 0x67. The minimum and maximum allowed values can be calculated based on the application. In this
example, a +/-5% tolerance is required, so tolerance is 0x67 * 5% = 0x05.
#define SPBRG_16BIT *((*int)&SPBRG; // define location for 16-bit SPBRG value
const int DEFAULT_BAUD = 0x0067; // Default Auto-Baud value
const int TOL = 0x05; // Baud Rate % tolerance
const int MIN_BAUD = DEFAULT_BAUD - TOL; // Minimum Auto-Baud Limit
const int MAX_BAUD = DEFAULT_BAUD + TOL; // Maximum Auto-Baud Limit
ABDEN = 1; // Start Auto-Baud
while (ABDEN); // Wait until Auto-Baud completes
if((SPBRG_16BIT > MAX_BAUD)||(SPBRG_16BIT < MIN_BAUD))
{ // Compare if value is within limits
SPBRG_16BIT = DEFAULT_BAUD); // if out of spec, use DEFAULT_BAUD
}
// if in spec, continue using the
// Auto-Baud value in SPBRG
Affected Silicon Revisions
2011-2014 Microchip Technology Inc. DS80000525D-page 5
PIC16(L)F1847
EXAMPLE 2: METHOD 2 – EUSART AUTO-BAUD DETECT WORK AROUND
Affected Silicon Revisions
Similar to Method 1, define default, minimum and maximum auto-baud (SPBRG) values. In firmware, compute a running average of
SPBRG. If the new SPBRG value falls outside the minimum or maximum limits, then use the current running average value
(Average_Baud), otherwise use the auto-baud SPBRG value and calculate a new running average.
For example, if the application runs at 9600 baud at 16 MHz then, the default SPBRG value would be (assuming 16-bit/
Asynchronous mode) 0x67. The minimum and maximum allowed values can be calculated based on the application. In this
example, a +/-5% tolerance is required, so tolerance is 0x67 * 5% = 0x05.
#define SPBRG_16BIT *((*int)&SPBRG; // define location for 16-bit SPBRG value
const int DEFAULT_BAUD = 0x0067; // Default Auto-Baud value
const int TOL = 0x05; // Baud Rate % tolerance
const int MIN_BAUD = DEFAULT_BAUD - TOL; // Minimum Auto-Baud Limit
const int MAX_BAUD = DEFAULT_BAUD + TOL; // Maximum Auto-Baud Limit
int Average_Baud; // Define Average_Baud variable
int Integrator; // Define Integrator variable
Average_Baud = DEFAULT_BAUD; // Set initial average Baud rate
Integrator = DEFAULT_BAUD*15; // The running 16 count average
ABDEN = 1; // Start Auto-Baud
while (ABDEN); // Wait until Auto-Baud completes
Integrator+ = SPBRG_16BIT;
Average_Baud = Integrator/16;
if((SPBRG_16BIT > MAX_BAUD)||(SPBRG_16BIT < MIN_BAUD))
{ // Check if value is within limits
SPBRG_16BIT = Average_Baud; // If out of spec, use previous average
}
else // If in spec, calculate the running
{ // average but continue using the
Integrator+ = SPBRG_16BIT; // Auto-Baud value in SPBRG
Average_Baud = Integrator/16;
Integrator- = Average_Baud;
}
A2 A3
X
Work around Affected Silicon Revisions Work around Affected Silicon Revisions
PIC16(L)F1847
DS80000525D-page 6 2011-2014 Microchip Technology Inc.
5. Module: Enhanced Capture Compare
PWM (ECCP)
5.1 Full-Bridge PWM (CCPxM<3:0> = 11xx and
PxM<1:0> = 01 or 11)
In Full-Bridge mode of the PWM the pulse width
will be incorrect if using a Timer 2/4/6 prescaler
value other than 1:1 (TxCKPS<1:0> = 00). The
upper eight bits of the duty cycle have no effect on
this error. See Table 3 for details.
Work around
None.
Affected Silicon Revisions
6. Module: MSSP (Master Synchronous
Serial Port)
6.1 SPI Master mode
When the MSSP is used in SPI Master mode and
the CKE bit is clear (CKE = 0), the Buffer Full (BF)
bit and the MSSP Interrupt Flag (SSPIF) bit
becomes set half an SCK cycle early. If the user
software immediately reacts to either of the bits
being set, a write collision may occur as indicated
by the WCOL bit being set.
Work around
To avoid a write collision one of the following
methods should be used:
Method 1: Add a software delay of one SCK
period after detecting the
completed transfer (the BF bit or
SSPIF bit becomes set) and prior
to writing to the SSPBUF register.
Verify the WCOL bit is clear after
writing to SSPBUF. If the WCOL
bit is set, clear the bit in software
and rewrite the SSPBUF register.
Method 2: As part of the MSSP initialization
procedure, set the CKE bit
(CKE = 1).
Affected Silicon Revisions
TABLE 3: ECCP FULL-BRIDGE PULSE WIDTH PRESCALER CORRECTION
CCPxCON<5:4> Effect on Pulse
Width Prescaler = 1
(00)Prescaler = 4
(01)Prescaler = 16
(10)Prescaler = 64
(11)
00 No Effect No error No error No error No error
01 TOSC* (prescaler-1) No error TOSC* (-3) TOSC* (-15) TOSC* (-63)
10 TOSC* (prescaler*2) No error TOSC* (+8) TOSC* (+32) TOSC* (+128)
11 TOSC* (prescaler) No error TOSC* (+4) TOSC* (+16) TOSC* (+64)
A2 A3
XX
A2 A3
XX
2011-2014 Microchip Technology Inc. DS80000525D-page 7
PIC16(L)F1847
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS40001453E):
None.
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
Rev A Document (05/2011) Rev B Document (02/2012) Rev C Document (02/2013) Rev D Document (11/2014)
PIC16(L)F1847
DS80000525D-page 8 2011-2014 Microchip Technology Inc.
APPENDIX A: DOCUMENT
REVISION HISTORY
Rev A Document (05/2011)
Initial release of this document.
Rev B Document (02/2012)
Updated Table 1; Added Modules 3 and 4; Other minor
corrections.
Data Sheet Clarifications: Added Module 1, Oscillator.
Rev C Document (02/2013)
Added Silicon Revision A3; Modules 2, 3 and 4 have
been fixed; Added Module 5, ECCP; Added MPLAB X
IDE.
Data Sheet Clarifications: Removed Module 1,
Oscillator.
Rev D Document (11/2014)
Added module 6, MSSP; Other minor corrections.
YSTEM
2011-2014 Microchip Technology Inc. DS80000525D-page 9
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
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Generation, PICDEM, PICDEM.net, PICkit, PICtail,
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© 2011-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-772-1
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
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6‘ ‘MICRDCHIP
DS80000525D-page 10 2011-2014 Microchip Technology Inc.
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