MC74LVX4245 Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2011
July, 2017 − Rev. 6 1Publication Order Number:
MC74LVX4245/D
MC74LVX4245
Dual Supply Octal
Translating Transceiver
with 3−State Outputs
The 74LVX4245 is a 24−pin dual−supply, octal translating
transceiver that is designed to interface between a 5.0 V bus and a 3.0 V
bus in a mixed 3.0 V / 5.0 V supply environment such as laptop
computers using a 3.3 V CPU and 5.0 V LCD display. The A port
interfaces with the 5V bus; the B port interfaces with the 3.0 V bus.
The Transmit/Receive (T/R) input determines the direction of data
flow. Transmit (active−High) enables data from the A port to the B
port. Receive (active−Low) enables data from the B port to the A port.
The Output Enable (OE) input, when High, disables both A and B
ports by placing them in 3−State.
Features
Bi−directional Interface Between 5.0 V and 3.0 V Buses
Control Inputs Compatible with TTL Level
5.0 V Data Flow at A Port and 3.0 V Data Flow at B Port
Outputs Source/Sink 24 mA at 5.0 V Bus and 12 mA at 3.0 V Bus
Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
Available in SOIC and TSSOP Packages
Functionally Compatible with the 74 Series 245
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Figure 1. 24−Lead Pinout
(Top View)
2324 22 21 20 19 18
21 34567
VCCB
17
8
16
9
15
10
VCCB OE B0 B1 B2 B3 B4 B5 B6
VCCA T/R A0 A1 A2 A3 A4 A5 A6 A7
14
11
13
12
B7 GND
GND GND
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See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
PIN NAMES
Function
Output Enable Input
Transmit/Receive Input
Side A 3−State Inputs or 3−State
Outputs
Side B 3−State Inputs or 3−State
Outputs
Pins
OE
T/R
A0−A7
B0−B7
MARKING
DIAGRAMS
SOIC−24
DW SUFFIX
CASE 751E
1
24
LVX
4245G
ALYW
LVX4245
AWLYYWWG
1
24
1
24
1
24 TSSOP−24
DT SUFFIX
CASE 948H
LVX4245 = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
MC74LVX4245
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2
B0
OE 22
T/R 2
A0
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
Figure 2. Logic Diagram
3
4
5
6
7
8
9
10
21
20
19
18
17
16
15
14
INPUTS OPERATING MODE
Non−Inverting
OE T/R
L L B Data to A Bus
L H A Data to B Bus
H X Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level
and Transitions are Acceptable; For ICC reasons, Do Not Float Inputs
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ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Condition Unit
VCCA,
VCCB
DC Supply Voltage −0.5 to +7.0 V
VIDC Input Voltage OE, T/R −0.5 to VCCA +0.5 V
VI/O DC Input/Output Voltage An −0.5 to VCCA +0.5 V
Bn −0.5 to VCCB +0.5 V
IIK DC Input Diode Current OE, T/R ±20 VI < GND mA
IOK DC Output Diode Current ±50 VO < GND; VO > VCC mA
IODC Output Source/Sink Current ±50 mA
ICC,
IGND
DC Supply Current Per Output Pin
Maximum Current at ICCA
Maximum Current at ICCB
±50
±200
±100
mA
TSTG Storage Temperature Range −65 to +150 °C
Latchup DC Latchup Source/Sink Current ±300 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCCA,
VCCB
Supply Voltage VCCA
VCCB
4.5
2.7 5.5
3.6 V
VIInput Voltage OE, T/R 0 VCCA V
VI/O Input/Output Voltage An
Bn 0
0VCCA
VCCB
V
TAOperating Free−Air Temperature −40 +85 °C
Dt/DVMinimum Input Edge Rate
VIN from 30% to 70% of VCC; VCC at 3.0V, 4.5V, 5.5V 0 8 ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
TA = 25°C TA = −40 to +85°C
Symbol Parameter Condition VCCA VCCB Typ Guaranteed Limits Unit
VIHA Minimum HIGH
Level
Input Voltage
An,OE
T/R VOUT 0.1V
or
VCC − 0.1V
5.5
4.5 3.3
3.3 2.0
2.0 2.0
2.0 V
VIHB Bn 5.0
5.0 3.6
2.7 2.0
2.0 2.0
2.0 V
VILA Maximum LOW
Level
Input Voltage
An,OE
T/R VOUT 0.1V
or
VCC − 0.1V
5.5
4.5 3.3
3.3 0.8
0.8 0.8
0.8 V
VILB Bn 5.0
5.0 2.7
3.6 0.8
0.8 0.8
0.8 V
VOHA Minimum HIGH
Level
Output Voltage
IOUT = −100mA
IOH = −24mA 4.5
4.5 3.0
3.0 4.50
4.25 4.40
3.86 4.40
3.76 V
VOHB IOUT = −100mA
IOH = −12mA
IOH = −8mA
4.5
4.5
4.5
3.0
3.0
2.7
2.99
2.80
2.50
2.9
2.4
2.4
2.9
2.4
2.4
V
VOLA Maximum LOW
Level
Output Voltage
IOUT = 100mA
IOL = 24mA 4.5
4.5 3.0
3.0 0.002
0.18 0.10
0.36 0.10
0.44 V
VOLB IOUT = 100mA
IOL = 12mA
IOL = 8mA
4.5
4.5
4.5
3.0
3.0
2.7
0.002
0.1
0.1
0.10
0.31
0.31
0.10
0.40
0.40
V
MC74LVX4245
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4
DC ELECTRICAL CHARACTERISTICS
TA = −40 to +85°CTA = 25°C
Symbol UnitGuaranteed LimitsTypVCCB
VCCA
ConditionParameter
IIN Max Input Leak-
age
Current
OE,
T/R VI = VCCA, GND 5.5 3.6 ±0.1 ±1.0
mA
IOZA Max 3−State Out-
put Leakage An VI = VIH, VIL
OE = VCCA
VO = VCCA, GND 5.5 3.6 ±0.5 ±5.0
mA
IOZB Max 3−State Out-
put Leakage Bn VI = VIH, VIL
OE = VCCA
VO = VCCB, GND 5.5 3.6 ±0.5 ±5.0
mA
DICC Maximum ICCT
per Input An,OE
T/R VI=VCCA−2.1V 5.5 3.6 1.0 1.35 1.5 mA
Bn VI=VCCB−0.6V 5.5 3.6 0.35 0.5 mA
ICCA Quiescent VCCA
Supply Current An=VCCA or GND
Bn=VCCB or GND
OE=GND
T/R=GND
5.5 3.6 8 80
mA
ICCB Quiescent VCCB
Supply Current An=VCCA or GND
Bn=VCCB or GND
OE=GND
T/R=VCCA
5.5 3.6 5 50
mA
VOLPA
VOLPB
Quiet Output Max
Dynamic VOL Notes 1, 2 5.0
5.0 3.3
3.3 1.5
1.2 V
VOLVA
VOLVB
Quiet Output Min
Dynamic VOL Notes 1, 2 5.0
5.0 3.3
3.3 −1.2
−0.8 V
VIHDA
VIHDB
Min HIGH Level
Dynamic Input
Voltage Notes 1, 3 5.0
5.0 3.3
3.3 2.0
2.0
V
VILDA
VILDB
Max LOW Level
Dynamic Input
Voltage Notes 1, 3 5.0
5.0 3.3
3.3 0.8
0.8
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Worst case package.
2. Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND.
3. Max number of data inputs (n) switching. (n−1) inputs switching 0V to VCC level. Input under test switching: VCC level to threshold (VIHD),
0V to threshold (VILD), f = 1MHz.
CAPACITIVE CHARACTERISTICS
Symbol Parameter Condition Typical Unit
CIN Input Capacitance VCCA = 5.0V; VCCB = 3.3V 4.5 pF
CI/O Input/Output Capacitance VCCA = 5.0V; VCCB = 3.3V 15 pF
CPD Power Dissipation Capacitance BA
(Measured at 10MHz) ABVCCA = 5.0V
VCCB = 3.3V 55
40 pF
MC74LVX4245
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5
AC ELECTRICAL CHARACTERISTICS
TA = −40 to +85°C
CL = 50pF TA = −40 to +85°C
CL = 50pF
VCCA = 5V ±0.5V
VCCB = 3.3V ±0.3V VCCA = 5V ±0.5V
VCCB = 2.7V
Symbol Parameter Min Typ
(Note 4) Max Min Max Unit
tPHL
tPLH
Propagation Delay A to B 1.0
1.0 5.1
5.3 9.0
9.0 1.0
1.0 10.0
10.0 ns
tPHL
tPLH
Propagation Delay B to A 1.0
1.0 5.4
5.5 9.0
9.0 1.0
1.0 10.0
10.0 ns
tPZL
tPZH
Output Enable Time OE to B 1.0
1.0 6.5
6.7 10.5
10.5 1.0
1.0 11.5
11.5 ns
tPZL
tPZH
Output Enable Time OE to A 1.0
1.0 5.2
5.8 9.5
9.5 1.0
1.0 10.0
10.0 ns
tPHZ
tPLZ
Output Disable Time OE to B 1.0
1.0 6.0
3.3 10.0
7.0 1.0
1.0 10.0
7.5 ns
tPHZ
tPLZ
Output Disable Time OE to A 1.0
1.0 3.9
2.9 7.5
7.0 1.0
1.0 7.5
7.5 ns
tOSHL
tOSLH Output to Output Skew, Data to Output (Note 5) 1.0 1.5 1.5 ns
4. Typical values at VCCA = 5.0V; VCCB = 3.3V at 25°C.
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
ORDERING INFORMATION
Device Package Shipping
MC74LVX4245DWG SOIC−24
(Pb−Free)
30 Units / Rail
MC74LVX4245DWR2G 1000 / Tape & Reel
MC74LVX4245DTG
TSSOP−24
(Pb−Free)
62 Units / Rail
MC74LVX4245DTR2G 2500 / Tape & Reel
NLVLVX4245DTR2G* 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.cnsem iiii
MC74LVX4245
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6
Dual Supply Octal Translating Transceiver
The 74LVX4245 is a is a dual−supply device well capable
of bidirectional signal voltage translation. This level shifting
ability provides an excellent interface between low voltage
CPU local bus and a standard 5.0 V I/O bus. The device
control inputs can be controlled by either the low voltage
CPU and core logic or a bus arbitrator with 5.0 V I/O levels.
The LVX4245 is ideal for mixed voltage applications such
as notebook computers using a 3.3 V CPU and 5.0 V
peripheral devices.
Applications:
Mixed Mode Dual Supply Interface Solutions
The LVX4245 is designed to solve 3.0 V / 5.0 V interfaces
when CMOS devices cannot tolerate I/O levels above their
applied VCC. If an I/O pin of a 3.0 V device is driven by a 5.0
V device, the P−Channel transistor in the 3.0 V device will
conduct − causing current flow from the I/O bus to the 3.0 V
power supply. The result may be destruction of the 3.0 V
device through latchup effects. A current limiting resistor
may be used to prevent destruction, but it causes speed
degradation and needless power dissipation.
A better solution is provided in the LVX4245. It provides
two different output levels that easily handle the dual voltage
interface. The A port is a dedicated 5.0 V port; the B port is
a dedicated 3.0 V port.
Since the LVX4245 is a ‘245 transceiver, the user may
either use it for bidirectional or unidirectional applications.
The center 20 pins are configured to match a ‘245 pinout.
This enables the user to easily replace this level shifter with
a 3.0 V ‘245 device without additional layout work or re−
manufacture of the circuit board (when both buses are 3.0 V).
Figure 3. 3.3V/5V Interface Block Diagram
LVX4245
VCCB
VCCA
LVX4245
VCCB
VCCA
EISA - ISA - MCA
(5V I/O LEVELS)
LOW VOLTAGE CPU LOCAL BUS
Powering Up the LVX4245
When powering up the LVX4245, please note that if the
VCCB pin is powered−up well in advance of the VCCA pin,
several milliamps of either ICCA or ICCB current will result.
If the VCCA pin is powered−up in advance of the VCCB pin
then only nanoamps of Icc current will result. In actuality the
VCCB can be powered “slightly” before the VCCA without
the current penalty, but this “setup time” is dependent on the
power−up ramp rate of the VCC pins. With a ramp rate of
approximately 50 mV/ns (50V/ms) a 25 ns setup time was
observed (VCCB before VCCA). With a 7.0 V/ms rate, the
setup time was about 140ns. When all is said and done, the
safest powerup strategy is to simply power VCCA before
VCCB. One more note: if the VCCB ramp rate is faster than
the VCCA ramp rate then power problems might still occur,
even if the VCCA powerup began prior to the VCCB powerup.
+_. ._+ +_. ._+ +_. ._. ._. +_. ._+ *_. J. ._+ +_. , _ I _ :
MC74LVX4245
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7
Figure 4. MC74LVX4245 Fits Into a System with 3V Subsystem and 5V Subsystem
KEYBOARD
CONTROLLER
SUPER
I/O
CORE
LOGIC
TRANSCEIVERS
PCMCIA
CONTROLLER
VGA
CONTROLLER
LVX4245
A PORT
A0:7
CACHE
SRAM
CPU
386/486
ROM
BIOS
MEMORY
DRIVER
B PORT
B0:7
MICROCHANNEL/
EISA/ISA/AT
5V BUS
LOCAL
3V BUS 3V
5V
5V
VCCA
3V
VCCB
VCCA
(T/R) DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
GND
VCCB
VCCB
OE
B0
B1
B2
B3
B4
B5
B6
B7
GND
MC74LVX4245
STANDARD
74 SERIES
`245
Figure 5. MC74LVX4245 Pin Arrangement Is Compatible to 20−Pin 74 Series ‘245s
MC74LVX4245
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8
WAVEFORM 1 - PROPAGATION DELAYS
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
VCC
0V
VOH
VOL
An, Bn
Bn, An
tPHL
tPLH
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
VCCA
0V
0V
OE, T/R
An, Bn
tPZH
VCC
tPHZ
tPZL tPLZ
An, Bn
50% VCC
50% VCC
50% VCC
50% VCC
50% VCC 50% VCC
Figure 6. AC Waveforms
50% VCC
VCC
VOH - 0.3V
VOL + 0.3V
GND
50% VCC
OPEN
PULSE
GENERATOR
RT
DUT
VCC
RL
R1
CL
2 × VCC
TEST SWITCH
tPLH, tPHL, tPZH, tPHZ Open
tPZL, tPLZ 2 × VCC
CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500W or equivalent
RT = ZOUT of pulse generator (typically 50W)
Figure 7. Test Circuit
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MC74LVX4245
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9
PACKAGE DIMENSIONS
SOIC−24
DW SUFFIX
CASE 751E−04
ISSUE F
b
M
0.25 C
SEATING
PLANE
A1
M
L
DETAIL A
END VIEW
h_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b AND c APPLY TO THE FLAT SEC-
TION OF THE LEAD AND ARE MEASURED BE-
TWEEN 0.10 AND 0.25 FROM THE LEAD TIP.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 mm PER SIDE. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED
0.25 PER SIDE. DIMENSIONS D AND E1 ARE
DETERMINED AT DATUM H.
5. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
NOTE 3
PIN 1
12
1
24 13
TOP VIEW DIM MIN MAX
MILLIMETERS
A2.35 2.65
b0.35 0.49
e1.27 BSC
h0.25 0.75
c0.23 0.32
A1 0.13 0.29
L0.41 0.90
M0 8
__
D
E1
SIDE VIEW
11.00
24X
0.52
24X
1.62
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
E10.30 BSC
RECOMMENDED
INDICATOR A B
0.25 C
24X
B
A
C
A
NOTE 5
x 45
c
NOTE 3 DETAIL A
C
H
D15.25 15.54
E1 7.40 7.60
E
S S
e
.7uw nnmnnnnwn I ,, * D DETAIL A rm 1 WEAP JIeéb E-IE IIIIII IHIIIIIIIULIIli -IEE TOP VIEW ”-075 3 RECOMMEN SOLDERING FOO 24x 0.42 ‘Lnuuumn DIED I] I] I17 fL‘TJ + nunnnmmnnnnng, 06544 I+ PITCH WEN www mm cum sue Eur PalenFMakang ng
MC74LVX4245
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10
PACKAGE DIMENSIONS
TSSOP−24
DT SUFFIX
CASE 948H
ISSUE B
DIM
D
MIN MAX
7.90
MILLIMETERS
E1 4.30 4.50
A1.20
A1 0.05 0.15
L0.50 0.75
e0.65 BSC
c0.09 0.20
b0.19 0.30
L2 0.25 BSC
M0 8
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
DAMBAR PROTRUSION SHALL BE 0.08 MAX AT MMC. DAMBAR
CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS
OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMEN-
SION D IS DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 PER SIDE. DIMENSION E1 IS DETERMINED AT DA-
TUM PLANE H.
6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEAT-
ING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
7.70
---
24X
1.15
24X 0.42
0.65
DIMENSIONS: MILLIMETERS
PITCH
SOLDERING FOOTPRINT
E6.40 BSC
6.70
RECOMMENDED
L
L2
GAUGE
DETAIL A
PLANE
C
DETAIL A
M
END VIEW
c
H
0.10
SEATING
PLANE
SIDE VIEW
A
C
0.05 C
C
24X
A1
PIN 1
REFERENCE
D
E1
24X b
e
B
M
0.10 AC
TOP VIEW
B0.15 C
112
1324
A
B
NOTE 3
2X 12 TIPS
E
NOTE 6
NOTE 6
NOTE 4
NOTE 5
S S
S
MC74LVX4245/D
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