DM74LS90 Datasheet by onsemi

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© 2000 Fairchild Semiconductor Corporation DS006381 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS90 Decade and Binary Counters
DM74LS90
Decade and Binary Counters
General Description
Each of these monolithic counters contains four master-
slave flip-flops and additional gating to provide a divide-by-
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the DM74LS90.
All of these counters have a gated zero reset and the
DM74LS90 also has gated set-to-nine inputs for use in
BCD nine’s complement applications.
To use their maximum count length (decade or four bit
binary), the B input is connected to the QA output. The
input count pulses are applied to input A and the outputs
are as described in the appropriate truth table. A symmetri-
cal divide-by-ten count can be obtained from the
DM74LS90 counters by connecting the QD output to the A
input and applying the input count to the B input which
gives a divide-by-ten square wave at output QA.
Features
Typical power dissipation 45 mW
Count frequency 42 MHz
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Reset/Count Truth Table
Order Number Package Number Package Description
DM74LS90M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS90N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Reset Inputs Output
R0(1) R0(2) R9(1) R9(2) QDQCQBQA
H H L X LLLL
H H X L LLLL
XXHHHLLH
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT
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DM74LS90
Function Tables
BCD Count Sequence (Note 1)
Bi-Quinary (5-2) (Note 2)
H = HIGH Level
L = LOW Level
X = Don’t Care
Note 1: Output QA is connected to input B for BCD count.
Note 2: Output QD is connected to input A for bi-quinary count.
Note 3: Output QA is connected to input B.
Logic Diagram
The J and K inputs shown without connection are for reference only and
are functionally at a high level.
Count Output
QDQCQBQA
0 LLLL
1LLLH
2LLHL
3LLHH
4LHLL
5LHLH
6LHHL
7 LHHH
8 HLLL
9HLLH
Count Output
QAQDQCQB
0 LLLL
1LLLH
2LLHL
3LLHH
4LHLL
5 HLLL
6HLLH
7HLHL
8HLHH
9HHLL
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DM74LS90
Absolute Maximum Ratings(Note 4)
Note 4: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the “Electrical
Characteristics” table are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 5: CL = 15 pF, RL = 2 k, TA = 25°C and VCC = 5V.
Note 6: CL = 50 pF, RL = 2 k, TA = 25°C and VCC = 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 7: All typicals are at VCC = 5V, TA = 25°C.
Supply Voltage 7V
Input Voltage (Reset) 7V
Input Voltage (A or B) 5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range 65°C to +150°C
Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current 0.4 mA
IOL LOW Level Output Current 8 mA
fCLK Clock Frequency (Note 5) A to QA032MHz
B to QB016
fCLK Clock Frequency (Note 6) A to QA020MHz
B to QB010
tWPulse Width (Note 5) A 15
B30 ns
Reset 15
tWPulse Width (Note 6) A 25
B50 ns
Reset 25
tREL Reset Release Time (Note 5) 25 ns
tREL Reset Release Time (Note 6) 35 ns
TAFree Air Operating Temperature 0 70 °C
Symbol Parameter Conditions Min Typ Max Units
(Note 7)
VIInput Clamp Voltage VCC = Min, II = 18 mA 1.5 V
VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max (Note 8) VOutput Voltage VIL = Max, VIH = Min 0.35 0.5
IOL = 4 mA, VCC = Min 0.25 0.4
IIInput Current @ Max VCC = Max, VI = 7V Reset 0.1
mAInput Voltage VCC = Max A 0.2
VI = 5.5V B 0.4
IIH HIGH Level VCC = Max, VI = 2.7V Reset 20
µAInput Current A 40
B80
IIL LOW Level VCC = Max, VI = 0.4V Reset 0.4
mAInput Current A 2.4
B3.2
IOS Short Circuit Output Current VCC = Max (Note 9) 20 100 mA
ICC Supply Current VCC = Max (Note 7) 9 15 mA
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DM74LS90
Electrical Characteristics (Continued)
Note 8: QA outputs are tested at IOL = Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.
Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 10: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.
Switching Characteristics at VCC = 5V and TA = 25°C
From (Input) RL = 2 k
Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units
Min Max Min Max
fMAX Maximum Clock A to QA32 20 MHz
Frequency B to QB16 10
tPLH Propagation Delay Time A to QA16 20 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time A to QA18 24 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time A to QD48 52 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time A to QD50 60 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time B to QB16 23 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time B to QB21 30 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time B to QC32 37 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time B to QC35 44 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time B to QD32 36 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time B to QD35 44 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time SET-9 to QA, QD30 35 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time SET-9 to QB, QC40 48 ns
HIGH-to-LOW Level Output
tPHL Propagation Delay Time SET-0 to Any Q 40 52 ns
HIGH-to-LOW Level Output
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DM74LS90
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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DM74LS90 Decade and Binary Counters
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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