LTC6752(-1,-2,-3,-4) Datasheet

Linear Technology/Analog Devices

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Datasheet

LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
1
6752fc
For more information www.linear.com/LTC6752
Typical applicaTion
FeaTures DescripTion
280MHz, 2.9ns Comparator
Family with Rail-to-Rail Inputs
and CMOS Outputs
The LTC
®
6752 is a family of very high speed comparators
capable of supporting toggle rates up to 280MHz. These
comparators exhibit low propagation delays of 2.9ns, and
fast rise/fall times of 1.2ns. There are a total of 5 members
in the LTC6752 family, with different options for separate
input and output supplies, shutdown, output latch, adjust-
able hysteresis, complementary outputs, and package.
The LTC6752 comparators have rail-to-rail inputs that
operate from 2.45V, up to 3.5V or 5.25V, depending on
the option. The outputs are CMOS and the separate supply
options can operate down to 1.71V, allowing for directly
interfacing to 1.8V logic devices.
The low propagation delay of only 2.9ns combined with
low dispersion of only 1.8ns (10mV to 125mV overdrive
variation) makes these comparators an excellent choice
for critical timing applications. Similarly, the fast toggle
rate and the low jitter of 4.5ps RMS (100mVP-P, 100MHz
input) make the LTC6752 family ideally suited for high
frequency line driver and clock recovery circuits.
applicaTions
n Very High Toggle Rate: 280MHz
n Low Propagation Delay: 2.9ns
n Rail-to-Rail Inputs Extend Beyond Both Rails
n Output Current Capability: ±22mA
n Low Quiescent Current: 4.5mA
n Features within the LTC6752 Family:
n 2.45V to 5.25V Input Supply and 1.71V to 3.5V
Output Supply (Separate Supply Option)
n 2.45V to 3.5V Supply (Single Supply Option)
n Shutdown Pin for Reduced Power
n Output Latch and Adjustable Hysteresis
n Complementary Outputs
n Packages: TSOT-23, SC70, MSOP, 3mm × 3mm QFN
n Direct Replacement for ADCMP60X Family
n Fully Specified from –55°C to 125°C
n Clock and Data Recovery
n Level Shifting
n High Speed Data Acquisition Systems
n Window Comparators
n High Speed Line Receivers
n Fast Crystal Oscillators
n Time of Flight Measurements
n Time Domain Reflectometry
L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks of Analog
Devices, Inc. All other trademarks are the property of their respective owners.
500mV/DIV
–IN +INQ
50ns/DIV
6752 T01a
High Speed Differential Line Receiver with Excellent
Common Mode Rejection
VCC = 5V
+
Q
6752 T01a
SMALL DIFFERENTIAL SIGNAL WITH
LARGE COMMON MODE COMPONENT
VEE
+IN
–IN
LTC6752-2
VDD = 2.7V
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
2
6752fc
For more information www.linear.com/LTC6752
absoluTe MaxiMuM raTings
Total Supply Voltage (VCC to VEE)
(LTC6752-2/LTC6752-3/LTC6752-4) ....................5.5V
(LTC6752/LTC6752-1) ..........................................3.6V
Total Supply Voltage (VDD to VEE) ............................3.6V
Input Current (+IN, –IN, SHDN, LE/HYST)
(Note 2) ................................................................±10mA
Output Current (Q, Q) (Note 3) ............................ ±50mA
Specified Temperature Range (Note 4)
LTC6752I .............................................40°C to 8C
LTC6752H .......................................... 40°C to 125°C
LTC6752MP ....................................... 5C to 125°C
Storage Temperature Range .................. 65°C to 125°C
Maximum Junction Temperature (Note 3)............. 150°C
Lead Temperature Soldering (10s) ........................ 300°C
(Note 1)
LTC6752 LTC6752-1 LTC6752-2
Q 1
V
EE 2
TOP VIEW
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
+IN
3
5 V
CC
4 –IN
TJMAX = 150°C, JA = 215°C/W (NOTE 3)
Q 1
V
EE 2
+IN
3
6 VCC
5 LE
/HYST
4 –IN
TOP VIEW
SC6 PACKAGE
6-LEAD PLASTIC SC70
WITH LATCHING/ADJUSTABLE HYSTERESIS
TJMAX = 150°C, θJA = 270°C/W (NOTE 3)
1
2
3
4
VCC
+IN
–IN
SHDN
8
7
6
5
VDD
Q
VEE
LE
/HYST
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 163°C/W (NOTE 3)
LTC6752-3 LTC6752-4
12 11 10
456
TOP VIEW
13
VEE
UD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC QFN
7
8
9
3
2
1VDD
VCC
VEE
VEE
LE
/HYST
SHDN
Q
NC
Q
+IN
NC
–IN
TJMAX = 150°C, θJA = 68°C/W (NOTE 3)
EXPOSED PAD (PIN 13) IS VEE, MUST BE SOLDERED TO PCB
Q 1
V
EE 2
+IN
3
6 VCC
5 V
DD
4 –IN
TOP VIEW
SC6 PACKAGE
6-LEAD PLASTIC SC70
WITH SEPARATE INPUT/OUTPUT SUPPLIES
TJMAX = 150°C, θJA = 270°C/W (NOTE 3)
pin conFiguraTion
Table 1. Features and Part Numbers
PART#
LATCHING/ADJUSTABLE
HYSTERESIS
SEPARATE INPUT/
OUTPUT SUPPLIES SHUTDOWN
COMPLEMENTARY
OUTPUTS PACKAGE OFFERING
LTC6752 TSOT-23-5
LTC6752-1 lSC70-6
LTC6752-2 lll MS8
LTC6752-3 llll3mm × 3mm QFN
LTC6752-4 lSC70-6
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
3
6752fc
For more information www.linear.com/LTC6752
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6752IS5#TRMPBF LTC6752IS5#TRPBF LTGKT 5-Lead Plastic TSOT-23 –40°C to 85°C
LTC6752HS5#TRMPBF LTC6752HS5#TRPBF LTGKT 5-Lead Plastic TSOT-23 –40°C to 125°C
LTC6752MPS5#TRMPBF LTC6752MPS5#TRPBF LTGKT 5-Lead Plastic TSOT-23 –55°C to 125°C
LTC6752ISC6-1#TRMPBF LTC6752ISC6-1#TRPBF LGQK 6-Lead Plastic SC-70 –40°C to 85°C
LTC6752HSC6-1#TRMPBF LTC6752HSC6-1#TRPBF LGQK 6-Lead Plastic SC-70 –40°C to 125°C
LTC6752ISC6-4#TRMPBF LTC6752ISC6-4#TRPBF LGQM 6-Lead Plastic SC-70 –40°C to 85°C
LTC6752HSC6-4#TRMPBF LTC6752HSC6-4#TRPBF LGQM 6-Lead Plastic SC-70 –40°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6752IMS8-2#PBF LTC6752IMS8-2#TRPBF LTGKW 8-Lead Plastic MSOP –40°C to 85°C
LTC6752HMS8-2#PBF LTC6752HMS8-2#TRPBF LTGKW 8-Lead Plastic MSOP –40°C to 125°C
LTC6752IUD-3#PBF LTC6752IUD-3#TRPBF LGKV 12-Lead Plastic QFN (3mm × 3mm) –40°C to 85°C
LTC6752HUD-3#PBF LTC6752HUD-3#TRPBF LGKV 12-Lead Plastic QFN (3mm × 3mm) –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
elecTrical characTerisTics
(VCC = 2.5V, VDD = 2.5V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC - VEE Supply Voltage (Note 5) LTC6752/LTC6752-1 (Total Supply)
LTC6752-2/LTC6752-3/LTC6752-4 (Input Stage)
l
l
2.45
2.45
3.5
5.25
V
V
VDD - VEE Output Stage Supply Voltage (Note 5) LTC6752-2/LTC6752-3/LTC6752-4 l1.71 3.5 V
VCMR Input Voltage Range (Note 7) lVEE – 0.2 VCC + 0.1 V
VOS Input Offset Voltage (Note 6)
l
–5.5
–8.5
±1.2 5.5
8.5
mV
mV
TCVOS Input Offset Voltage Drift l18 µV/°C
VHYST Input Hysteresis Voltage (Note 6) LE/HYST Pin Floating 5 mV
CIN Input Capacitance 1.1 pF
RDM Differential Mode Resistance 57
RCM Common Mode Resistance 6.4
IBInput Bias Current VCM = VEE + 0.3V
l
–3.8
–4
–1.35 µA
µA
VCM = VCC – 0.3V
l
0.3 1.25
2.1
µA
µA
IOS Input Offset Current l–0.75 ±0.1 0.75 µA
CMRR_
LVCM
Common Mode Input Range, Low VCM
Region
VCM = VEE – 0.2V to VCC – 1.5V
l
51
46
69 dB
dB
CMRR_FR Common Mode Rejection Ratio (Measured at
Extreme Ends of VCMR)
VCM = VEE – 0.2V to VCC + 0.1V
l
50
45.5
65 dB
dB
orDer inForMaTion
http://www.linear.com/product/LTC6752#orderinfo
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
4
6752fc
For more information www.linear.com/LTC6752
elecTrical characTerisTics
(VCC = 2.5V, VDD = 2.5V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR_VCC Input Power Supply Rejection Ratio VCM = 0.3V, VDD = 2.5V, VCC Varied from 2.45V
to 5.25V (LTC6752-2/LTC6752-3/LTC6752-4)
l
59
57
74 dB
dB
Total Power Supply Rejection Ratio VCM = 0.3V, VCC Varied from 2.45V to 3.5V
(LTC6752/LTC6752-1)
l
53
51
73 dB
dB
PSRR_VDD Output Power Supply Rejection Ratio VCM = 0.3V, VDD Varied from 1.71V to 3.5V
(LTC6752-2/LTC6752-3/LTC6752-4)
l
56
51
71 dB
dB
AVOL Open Loop Gain LTC6752-1/LTC6752-2/LTC6752-3, Hysteresis
Removed (Note 12)
6000 V/V
VOH Output High Voltage (Amount Below
VDD (LTC6752-2/LTC5752-3/LTC6752-4),
VCC (LTC6752/LTC6752-1))
ISOURCE = 8mA
l
130 260
340
mV
mV
VOL Output Low Voltage (Referred to VEE) ISINK = 8mA
l
200 340
400
mV
mV
ISC Output Short-Circuit Current Source
l
16
12
30 mA
mA
Sink
l
15
9
22 mA
mA
IVCC VCC Supply Current, Device On LTC6752/LTC6752-1
l
4.5 5.0
5.9
mA
mA
LTC6752-2/LTC6752-3/LTC6752-4
l
1.9 2.25
2.5
mA
mA
IVDD VDD Supply Current, Device On LTC6752-2/LTC6752-4
l
2.6 3.2
3.4
mA
mA
LTC6752-3
l
4.3 4.75
5.2
mA
mA
ITOTAL Total Supply Current, Device On LTC6752/LTC6752-1/LTC6752-2/LTC6752-4
l
4.5 5.0
5.9
mA
mA
LTC6752-3
l
6.2 6.65
7.7
mA
mA
tR, tFRise/Fall time 10% to 90% 1.2 ns
tPD Propagation Delay (Note 8) VOVERDRIVE = 50mV
l
2.9 5
5.5
ns
ns
tSKEW Propagation Delay Skew, Rising to Falling
Transition (Note 9)
300 ps
tODD Overdrive Dispersion (Note 8) Overdrive Varied from 10mV to 125mV 1.8 ns
tCMD Common Mode Dispersion VCM Varied from VEE – 0.2V to VCC + 0.1V 240 ps
TR Toggle Rate (Note 11) 100mVP-P Input, LTC6752/LTC6752-1/
LTC6752-2/LTC6752-4
100mVP-P Input, LTC6752-3
280
250
MHz
MHz
tJITTER RMS Jitter VIN = 100mVP-P,
fIN = 100MHz, Jitter BW = 10Hz – 50MHz
fIN = 61.44MHz, Jitter BW = 10Hz 30.72MHz
fIN = 10MHz, Jitter BW = 10Hz – 5MHz
4.5
6.0
30
ps
ps
ps
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
5
6752fc
For more information www.linear.com/LTC6752
elecTrical characTerisTics
(VCC = 2.5V, VDD = 2.5V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Latching/Adjustable Hysteresis Characteristics (LTC6752-1/LTC6752-2/LTC6752-3 Only)
VLE/HYST LE/HYST Pin Voltage Open Circuit l1.05 1.25 1.45 V
RHYST Resistance Looking Into LE/HYST LE/HYST Pin Voltage < Open Circuit Value l15 20 25
VHYST_LARGE Hysteresis Voltage VLE/HYST = 800mV 40 mV
VIL_LE Latch Pin Voltage, Latch Guaranteed l0.3 V
VIH_LE Latch Pin Voltage, Hysteresis Disabled Output Not Latched l1.7 V
IIH_LE Latch Pin Current High VLE/HYST = 1.7V l30 72 µA
IIL_LE Latch Pin Current Low VLE/HYST = 0.3V l–70 –47 µA
tSETUP Latch Setup Time (Note 10) –2 ns
tHOLD Latch Hold Time (Note 10) 2 ns
tPL Latch to Output Delay 7 ns
Shutdown Characteristics (LTC6752-2/LTC6752-3 Only)
ISD_VCC Shutdown Mode Input Stage Supply Current VSHDN = 0.6V
l
400 585
620
µA
µA
ISD_VDD Shutdown Mode Output Stage Supply
Current
VSHDN = 0.6V, LTC6752-2
l
185 340
380
µA
µA
VSHDN = 0.6V, LTC6752-3
l
250 650
680
µA
µA
tSD Shutdown Time Output Hi-Z 80 ns
VIH_SD Shutdown Pin Voltage High Part Guaranteed to Be Powered On l1.3 V
VIL_SD Shutdown Pin Voltage Low Part Guaranteed to Be Powered Off l0.6 V
tWAKEUP Wake-Up Time from Shutdown VOD = 100mV, Output Valid 100 ns
(VCC = 3.3V, VDD = 3.3V, VEE = 0). The l denotes the specifications which apply over the specified temperature range, otherwise
specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN +
VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC - VEE Supply Voltage (Note 5) LTC6752/LTC6752-1 (Total Supply)
LTC6752-2/LTC6752-3/LTC6752-4 (Input Stage)
l
l
2.45
2.45
3.5
5.25
V
V
VDD - VEE Output Supply Voltage (Note 5) LTC6752-2/LTC6752-3/LTC6752-4 l1.71 3.5 V
VCMR Input Voltage Range (Note 7) lVEE – 0.2 VCC + 0.1 V
VOS Input Offset Voltage (Note 6)
l
–5.5
–9
±1.2 5.5
9
mV
mV
TCVOS Input Offset Voltage Drift l18 µV/°C
VHYST Input Hysteresis Voltage (Note 6) LE/HYST Pin Floating 4.7 mV
CIN Input Capacitance 1.1 pF
RDM Differential Mode Resistance 57
RCM Common Mode Resistance 6.4
IBInput Bias Current VCM = VEE + 0.3V
l
–3.8
–4.1
–1.4 µA
µA
VCM = VCC – 0.3V
l
0.33 1.5
2.3
µA
µA
IOS Input Offset Current l–0.75 ±0.1 0.75 µA
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
6
6752fc
For more information www.linear.com/LTC6752
elecTrical characTerisTics
(VCC = 3.3V, VDD = 3.3V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CMRR_
LVCM
Common Mode Input Range, Low VCM
Region
VCM = VEE – 0.2V to VCC – 1.5V
l
52
48
70 dB
dB
CMRR_FR Common Mode Rejection Ratio (Measured at
Extreme Ends of VCMR)
VCM = VEE – 0.2V to VCC + 0.1V
l
50
46
66 dB
dB
PSRR_VCC Input Power Supply Rejection Ratio VCM = 0.3V, VDD = 3.3V,VCC Varied from 2.45V
to 5.25V (LTC6752-2/LTC6752-3/LTC6752-4)
l
59
57
75 dB
Total Power Supply Rejection Ratio VCM = 0.3V,VCC Varied from 2.45V to 3.5V
(LTC6752/LTC6752-1)
l
53
51
73 dB
dB
PSRR_VDD Output Power Supply Rejection Ratio VCM = 0.3V, VDD Varied from 1.71V to 3.5V
(LTC6752-2/LTC6752-3/LTC6752-4)
l
56
51
71 dB
dB
AVOL Open Loop Gain LTC6752-1/LTC6752-2/LTC6752-3,Hysteresis
Removed (Note 12)
7000 V/V
VOH Output High Voltage (Amount Below VDD
(LTC6752-2/LTC5752-3/LTC6752-4), VCC
(LTC6752/LTC6752-1))
ISOURCE = 8mA
l
81 200
300
mV
mV
VOL Output Low Voltage (Referred to VEE) ISINK = 8mA
l
155 320
350
mV
mV
ISC Output Short-Circuit Current Source
l
35
30
70 mA
mA
Sink
l
20
15
39 mA
mA
IVCC VCC Supply Current, Device On LTC6752/LTC6752-1
l
4.8 5.8
6.2
mA
mA
LTC6752-2/LTC6752-3/LTC6752-4
l
1.9 2.35
2.55
mA
mA
IVDD VDD Supply Current, Device On LTC6752-2/LTC6752-4
l
2.9 3.45
3.65
mA
mA
LTC6752-3
l
4.75 5.35
5.75
mA
mA
ITOTAL Total Supply Current, Device On LTC6752/LTC6752-1/LTC6752-2/LTC6752-4
l
4.8 5.8
6.2
mA
mA
LTC6752-3
l
6.6 7.7
8.3
mA
mA
tR, tFRise/Fall Time 10% to 90% 1.35 ns
tPD Propagation Delay (Note 8) VOVERDRIVE = 50mV
l
3.00 5
5.5
ns
ns
tSKEW Propagation Delay Skew, Rising to Falling
Transition (Note 9)
600 ps
tODD Overdrive Dispersion (Note 8) Overdrive Varied from 10mV to 125mV 1.8 ns
tCMD Common Mode Dispersion VCM Varied from VEE—0.2V to VCC + 0.1V 240 ps
TR Toggle Rate (Note 11) 100mVP-P Input 215 MHz
tJITTER RMS jitter VIN = 100mVP-P, fIN = 100MHz,
Jitter BW = 10Hz – 50MHz
fIN = 61.44MHz, Jitter BW = 10Hz – 30.72MHz
fIN = 10MHz, Jitter BW = 10Hz – 5MHz
4.8
5.8
29
ps
ps
ps
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
7
6752fc
For more information www.linear.com/LTC6752
elecTrical characTerisTics
(VCC = 3.3V, VDD = 3.3V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Latching/Adjustable Hysteresis Characteristics (LTC6752-1/LTC6752-2/LTC6752-3 Only)
VLE/HYST LE/HYST Pin Voltage Open Circuit l1.05 1.25 1.45 V
RHYST Resistance Looking Into LE/HYST LE/HYST Pin Voltage < Open Circuit Value l15 20 25
VHYST_LARGE Hysteresis Voltage VLE/HYST = 800mV 40 mV
VIL_LE Latch Pin Voltage, Latch Guaranteed l0.3 V
VIH_LE Latch Pin Voltage, Hysteresis Disabled Output Not Latched l1.7 V
IIH_LE Latch Pin Current High VLE/HYST = 1.7V l30 72 µA
IIL_LE Latch Pin Current Low VLE/HYST = 0.3V l–70 –47 µA
tSETUP Latch Setup Time (Note 10) –2 ns
tHOLD Latch Hold Time (Note 10) 2 ns
tPL Latch to Output Delay 7 ns
Shutdown Characteristics (LTC6752-2/LTC6752-3 Only)
ISD_VCC Shutdown Mode Input Stage Supply Current VSHDN = 0.6V
l
430 600
660
µA
µA
ISD_VDD Shutdown Mode Output Stage Supply
Current
VSHDN = 0.6V, LTC6752-2
l
200 420
450
µA
µA
VSHDN = 0.6V, LTC6752-3
l
300 700
800
µA
µA
tSD Shutdown Time Output Hi-Z 80 ns
VIH_SD Shutdown Pin Voltage High Part Guaranteed to Be Powered On l1.3 V
VIL_SD Shutdown Pin Voltage Low Part Guaranteed to Be Powered Off l0.6 V
tWAKEUP Wake-Up Time from Shutdown VOD = 100mV, Output Valid 100 ns
(VCC = 5V, VDD = 1.8V, VEE = 0, LTC6752-2/LTC6752-3/LTC6752-4 only). The l denotes the specifications which apply over the
specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV,
–IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC - VEE Input Supply Voltage (Note 5) l2.45 5.25 V
VDD - VEE Output Supply Voltage (Note5) l1.71 3.5 V
VCMR Input Voltage Range (Note 7) lVEE – 0.2 VCC + 0.1 V
VOS Input Offset Voltage (Note 6)
l
–5.5
–9
±1.2 5.5
9
mV
mV
TCVOS Input Offset Voltage Drift l14 µV/°C
VHYST Input Hysteresis Voltage (Note 6) LE/HYST Pin Floating 5.2 mV
CIN Input Capacitance 1.1 pF
RDM Differential Mode Resistance 57
RCM Common Mode Resistance 6.4
IBInput Bias Current VCM = VEE + 0.3V
l
–3.9
–4.2
–1.5 µA
µA
VCM = VCC – 0.3V
l
0.36 1.6
2.5
µA
µA
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
8
6752fc
For more information www.linear.com/LTC6752
elecTrical characTerisTics
(VCC = 5V, VDD = 1.8V, VEE = 0, LTC6752-2/LTC6752-3/LTC6752-4 only).
The l denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C.
LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IOS Input Offset Current l–0.9 ±0.1 0.9 µA
CMRR_
LVCM
Common Mode Input Range, Low VCM
Region
VCM = VEE – 0.2V to VCC – 1.5V
l
54
51
70 dB
dB
CMRR_FR Common Mode Rejection Ratio (Measured at
Extreme Ends of VCMR)
VCM = VEE – 0.2V to VCC + 0.1V
l
53
48
68 dB
dB
PSRR_VCC Input Power Supply Rejection Ratio VCM = 0.3V, VDD = 1.8V,VCC Varied from 2.45V
to 5.25V
l
59
57
75 dB
PSRR_VDD Output Power Supply Rejection Ratio VCM = 0.3V, VDD Varied from 1.71V to 3.5V
l
57
51
71 dB
dB
AVOL Open Loop Gain LTC6752-2/LTC6752-3 Hysteresis Removed
(Note 12)
3500 V/V
VOH Output High Voltage (Amount Below VDD) ISOURCE = 5.5mA
l
200 400
450
mV
mV
VOL Output Low Voltage (Referred to VEE) ISINK = 5.5mA
l
200 400
550
mV
mV
ISC Output Short-Circuit Current Source
l
9
6.2
17 mA
mA
Sink
l
11
6.2
19 mA
mA
IVCC VCC Supply Current, Device On
l
2.1 2.65
2.85
mA
mA
IVDD VDD Supply Current, Device On LTC6752-2/LTC6752-4
l
2.5 3
3.25
mA
mA
LTC6752-3
l
3.4 4.4
4.8
mA
mA
ITOTAL Total Supply Current, Device On LTC6752-2/LTC6752-4
l
4.5 5.65
6.1
mA
mA
LTC6752-3
l
6 7.05
7.65
mA
mA
tR, tFRise/Fall Time 10% to 90% 1.25 ns
tPD Propagation Delay (Note 8) VOVERDRIVE = 50mV
l
3.4 5.3
5.7
ns
ns
tSKEW Propagation Delay Skew, Rising to Falling
Transition (Note 9)
400 ps
tODD Overdrive Dispersion (Note 8) Overdrive Varied from 10mV to 125mV 1.8 ns
tCMD Common Mode Dispersion VCM Varied from VEE – 0.2V to VCC + 0.1V 240 ps
TR Toggle Rate (Note 11) 100mVP-P Input, LTC6752-2/LTC6752-4
100mVP-P Input, LTC6752-3
230
185
MHz
MHz
tJITTER RMS Jitter VIN = 100mVP-P, fIN = 100MHz,
Jitter BW = 10Hz – 50MHz
fIN = 61.44MHz, Jitter BW = 10Hz – 30.72MHz
fIN = 10MHz, Jitter BW = 10Hz – 5MHz
4.3
5.8
28
ps
ps
ps
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
9
6752fc
For more information www.linear.com/LTC6752
elecTrical characTerisTics
(VCC = 5V, VDD = 1.8V, VEE = 0, LTC6752-2/LTC6752-3 only).
The l denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C.
LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Latching/Adjustable Hysteresis Characteristics (LTC6752-2/LTC6752-3 Only)
VLE/HYST LE/HYST Pin Voltage Open Circuit l1.05 1.25 1.45 V
RHYST Resistance Looking Into LE/HYST LE/HYST Pin Voltage < Open Circuit Value l15 20 25
VHYST_LARGE Modified Input Hysteresis Voltage (Note 2) VLE/HYST = 800mV 40 mV
VIL_LE Latch Pin Voltage, Latch Guaranteed l0.3 V
VIH_LE Latch Pin Voltage, Hysteresis Disabled Output Not Latched l1.7 V
IIH_LE Latch Pin Current High VLE/HYST = 1.7V l30 72 µA
IIL_LE Latch Pin Current Low VLE/HYST = 0.3V l–70 –47 µA
tSETUP Latch Setup Time (Note 10) –2 ns
tHOLD Latch Hold Time (Note 10) 2 ns
tPL Latch To Output Delay 7 ns
Shutdown Characteristics (LTC6752-2/LTC6752-3 Only)
ISD_VCC Shutdown Mode Input Stage Supply Current VSHDN = 0.6V
l
500 650
750
µA
µA
ISD_VDD Shutdown Mode Output Stage Supply
Current
VSHDN = 0.6V, LTC6752-2
l
170 400
450
µA
µA
VSHDN = 0.6V, LTC6752-3
l
240 600
650
µA
µA
tSD Shutdown Time Output Hi-Z 80 ns
VIH_SD Shutdown Pin Voltage High Part Guaranteed to Be Powered On l1.3 V
VIL_SD Shutdown Pin Voltage Low Part Guaranteed to Be Powered Off l0.6 V
tWAKEUP Wake-Up Time from Shutdown VOD = 100mV, Output Valid 100 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Reverse biased ESD protection diodes exist on all input,
shutdown, latching/hysteresis and output pins. If the voltage on these
pins goes 300mV beyond either supply rail, the current should be limited
to less than 10mA. This parameter is guaranteed to meet specification
through design and/or characterization. It is not production tested.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating. This parameter is guaranteed to meet
specified performance through design and/or characterization. It is not
production tested.
Note 4: The LTC6752I/LTC6752-1I/LTC6752-2I/LTC6752-3I/LTC6752-4I
are guaranteed to meet specified performance from –40°C to 85°C. The
LTC6752H/LTC6752-1H/LTC6752-2H/LTC6752-3H/LTC6752-4H are
guaranteed to meet specified performance from –40°C to 125°C.
Note 5: Total output supply voltage range is guaranteed by the PSRR_VDD
test. Total input supply voltage range for the LTC6752-2, LTC6752-3 and
LTC6752-4 is guaranteed by the PSRR_VCC test. For the LTC6752 and
LTC6752-1, the supply voltage range is guaranteed by the PSRR_VCC test.
The LTC6752MP is guaranteed to meet specified performance from –55°C
to 125°C.
Note 6: Both hysteresis and offset are measured by determining positive
and negative trip points (input values needed to change the output in the
opposite direction). Hysteresis is defined as the difference of the two trip
points and offset as the average of the two trip points.
Note 7: Guaranteed by CMRR test.
Note 8: Propagation delays are measured with a step size of 150mV.
Note 9: Propagation delay skew is defined as the difference of the
propagation delays for positive and negative steps for the LTC6752,
LTC6752-1, LTC6752-2 and LTC6752-4, and the difference in propagation
delays between the complementary outputs for the LTC6752-3.
Note 10: Latch setup time is defined as the minimum time before the
LE/HYST pin is asserted low for an input signal change to be acquired and
held at the output. Latch hold time is defined as the minimum time before
an input signal change for a high to low transition on the LE/HYST pin to
prevent the output from changing. See Figure 7 for a graphical definition of
these terms.
Note 11: Toggling is defined to be valid if the output swings as follows:
from 10% of VDD - VEE to 90% of VDD - VEE for the LTC6752-2/
LTC6752-3/LTC6752-4, and from 10% of VCC - VEE to 90% of VCC - VEE
for the LTC6752/LTC6752-1. It is tested with a 1kΩ load to VCM
Note 12: The devices have effectively infinite gain when hysteresis is
enabled.
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
10
6752fc
For more information www.linear.com/LTC6752
Typical perForMance characTerisTics Dc
Input Bias Current vs Differential
Input Voltage
Input Hysteresis vs LE/HYST Pin
Voltage LE/HYST Pin I-V Characteristics
INPUT DIFFERENTIAL VOLTAGE (V)
–5.4
BIAS CURRENT (µA)
1.0
0.5
–0.5
–1.5
–2.5
0
–1.0
–2.0
–3.0
–3.5 –0.6 4.2–3.0 1.8
6752 G07
5.4
–1.8 3.0–4.2 0.6
VCC = 5V
VDD = 2.5V
VCM = 2.5V
–IN
+IN
LE/HYST VOLTAGE (V)
0.75
HYSTERESIS (mV)
50
40
20
30
10
01.501.25
6752 G08
1.75
1.00
LE/HYST PIN VOLTAGE (V)
–0.3
LE/HYST PIN CURRENT (µA)
200
150
0
100
50
–50
–100 4.51.3 2.1 2.9 3.7
6752 G09
5.3
0.5
VCC = 2.5V
VCC = 5V
Input Offset Voltage and
Hysteresis vs Input Common Mode Input Bias Current vs Temperature
Input Bias Current vs Common
Mode Voltage
Input Offset Voltage and
Hysteresis vs Temperature
Input Offset Voltage and
Hysteresis vs VCC Voltage
Input Offset Voltage and
Hysteresis vs VDD Voltage
VCC = VDD = 2.5V, CLOAD = 5pF,
VOVERDRIVE = 50mV, VCM = 300mV,TA = 25°C unless otherwise noted. VCC VDD conditions applicable only to the LTC6752-2/LTC6752-3/
LTC6752-4.
TEMPERATURE (°C)
–55
OFFSET/HYSTERESIS (mV)
8
6
4
0
2
–2
–4 25 105–15 65
6752 G01
125
5 85–35 45
VHYST
VOS
INPUT COMMON MODE VOLTAGE (V)
OFFSET, HYSTERESIS (mV)
6752 G04
HYSTERESIS
OFFSET
–0.2
7
–2
4
2
6
5
3
1
–1
–3
0
1.0 1.80.2 1.4 2.2
2.6
0.6
INPUT COMMON MODE VOLTAGE (V)
INPUT BIAS CURRENT (µA)
6752 G06
VIN = VOS
–0.2
0.5
–1.0
0
–0.5
–1.5
–2.0 1.0 1.80.2 1.4 2.2
2.6
0.6
0.8
0.6
0.2
–0.4
–0.8
–1.2
0.4
–0.2
–0.6
–1.0
0
–1.4
TEMPERATURE (°C)
–55
INPUT BIAS CURRENT (µA)
25 105–15 65
6752 G05
125
5 85–35 45
VCM = 2.2V
VCM = 300mV
VCC VOLTAGE (V)
2.45
OFFSET, HYSTERESIS (mV)
6
5
4
2
3
1
04.553.85
6752 G02
5.25
3.15
HYSTERESIS
OFFSET
VDD VOLTAGE (V)
1.6
OFFSET, HYSTERESIS (mV)
7
6
5
4
2
3
1
03.12.6
6752 G03
3.6
2.1
HYSTERESIS
OFFSET
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
11
6752fc
For more information www.linear.com/LTC6752
Typical perForMance characTerisTics Dc
Supply Current vs Temperature
(LTC6752/LTC6752-1/LTC6752-2/
LTC6752-4)
Supply Current vs Temperature
(LTC6752-3)
Output Short-Circuit Current vs
Temperature
Output Low Voltage vs Load
Current
Output High Voltage vs Sourcing
Current
Output High/Low Voltage vs
Temperature
VCC = VDD = 2.5V, CLOAD = 5pF,
VOVERDRIVE = 50mV, VCM = 300mV,TA = 25°C unless otherwise noted. VCC VDD conditions applicable only to the LTC6752-2/ LTC6752-3/
LTC6752-4.
80
60
20
–40
40
–20
–60
0
–80
TEMPERATURE (°C)
–55
SHORT-CIRCUIT CURRENT (mA)
25 105–15 65
6752 G10
125
5 85–35 45
VCC = 5V, VDD = 1.8V
VCC = VDD = 2.5V
VCC = VDD = 3.3V
SOURCING
SINKING
5.0
TEMPERATURE (°C)
–55
SUPPLY CURRENT (mA)
25 105–15 65
6752 G14
125
5 85–35 45
4.5
4.0
3.0
2.0
1.0
3.5
2.5
1.5 IVCC (LTC6752-2/LTC6752-4)
IVDD (LTC6752-2/LTC6752-4)
ITOTAL (LTC6752-2/LTC6752-4)
ICC (LTC6752/LTC6752-1)
7
TEMPERATURE (°C)
–55
SUPPLY CURRENT (mA)
25 105–15 65
6752 G15
125
5 85–35 45
6
5
3
1
4
2IVCC
IVDD
ITOTAL
SINKING CURRENT (mA)
0
OUTPUT LOW VOLTAGE (V)
4.5
4.0
3.0
2.0
1.0
3.5
2.5
1.5
0.5
020 4010 30
6752 G11
45
15 355 25
VCC = 2.5V
VDD = 2.5V
VCC = 5V
VDD = 1.8V
VCC = 3.3V
VDD = 3.3V
MEASURED FROM VEE
SOURCING CURRENT (mA)
0
OUTPUT VOLTAGE RELATIVE TO V
DD
(V)
–4.5
–4.0
–3.0
–2.0
–1.0
–3.5
–2.5
–1.5
–0.5
0
20 7060504010 30
6752 G12
80
VCC = 2.5V
VDD = 2.5V
VCC = 5V
VDD = 1.8V
VCC = 3.3V
VDD = 3.3V
300
TEMPERATURE (°C)
–55
OUTPUT HIGH/LOW VOLTAGE (mV)
25 105–15 65
6752 G13
125
5 85–35 45
250
200
100
0
150
50
VOH
VOL
SOURCE/SINK CURRENT = 8mA
MEASURED
FROM VDD
MEASURED
FROM VEE
Supply Current vs Supply Voltage
(LTC6752/LTC6752-1/LTC6752-2/
LTC6752-4)
Supply Current vs Supply Voltage
(LTC6752-3)
Supply Current vs Input Common
Mode Voltage (LTC6752/LTC6752-1/
LTC6752-2/LTC6752-4)
6
SUPPLY VOLTAGE (V)
2.45
SUPPLY CURRENT (mA)
3.352.75
6752 G16
3.65
3.05
5
3
0
1
4
2
VCC = VDD
IVCC (LTC6752-2/LTC6752-4)
IVDD (LTC6752-2/LTC6752-4)
ITOTAL (LTC6752-2/LTC6752-4)
ICC (LTC6752/LTC6752-1)
8
7
6
SUPPLY VOLTAGE (V)
2.45
SUPPLY CURRENT (mA)
3.352.75
6752 G17
3.65
3.05
5
3
0
1
4
2IVCC
VCC = VDD
IVDD
ITOTAL
4.85
4.80
4.75
4.70
4.65
4.60
4.55
4.50
INPUT COMMON MODE VOLTAGE (V)
–0.2
TOTAL SUPPLY CURRENT I
VCC
+ I
VDD
(mA)
1.90.5
6752 G18
2.6
1.2
4.45
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
12
6752fc
For more information www.linear.com/LTC6752
Typical perForMance characTerisTics Dc
VCC = VDD = 2.5V, CLOAD = 5pF,
VOVERDRIVE = 50mV, VCM = 300mV,TA = 25°C unless otherwise noted. VCC VDD conditions applicable only to the LTC6752-2/LTC6752-3/
LTC6752-4.
Supply Current vs Temperature,
Shutdown (LTC6752-2)
Supply Current vs Temperature,
Shutdown (LTC6752-3)
SHDN Pin I-V Characteristics
Total Supply Current vs SHDN Pin
Voltage (LTC6752-2)
Total Supply Current vs SHDN Pin
Voltage (LTC6752-3)
Supply Current vs Input Common
Mode Voltage (LTC6752-3)
700
TEMPERATURE (°C)
–55
SHUTDOWN SUPPLY CURRENT (µA)
25 105–15 65
6752 G23
125
5 85–35 45
600
500
300
100
400
200 IVCC
IVDD
ITOTAL
700
TEMPERATURE (°C)
–55
SHUTDOWN SUPPLY CURRENT (µA)
25 105–15 65
6752 G24
125
5 85–35 45
600
500
300
100
400
200 IVCC
IVDD
ITOTAL
VOLTAGE BETWEEN SHDN PIN AND VEE (V)
–0.3
SHDN PIN CURRENT (µA)
2
0
–4
–10
–14
–2
–8
–12
–6
–16 2.1 4.5
6752 G20
5.3
1.3 3.70.5 2.9
VCC = 5V
VCC = 2.5V
5.0
SHDN PIN VOLTAGE (V)
–0.3
TOTAL SUPPLY CURRENT (mA)
1.70.7
6752 G21
2.7
1.20.2 2.2
4.5
4.0
3.5
3.0
2.5
2.0
1.5
0.5
1.0
0
6.45
6.40
6.35
6.30
6.25
6.20
6.15
INPUT COMMON MODE VOLTAGE (V)
–0.2
TOTAL SUPPLY CURRENT I
VCC
+ I
VDD
(mA)
1.90.5
6752 G19
2.6
1.2
6.10
7
6
5
SHDN PIN VOLTAGE (V)
–0.3
TOTAL SUPPLY CURRENT (mA)
1.70.7
6752 G22
2.71.20.2 2.2
4
3
2
1
0
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
13
6752fc
For more information www.linear.com/LTC6752
Typical perForMance characTerisTics ac
VCC = VDD = 2.5V, CLOAD = 5pF,
VOVERDRIVE = 50mV, VCM = 300mV, TA = 25°C, transient input voltage 10MHz, 150mVP-P square wave unless otherwise noted.
VCC ≠ VDD conditions applicable only to the LTC6752-2/LTC6752-3/LTC6752-4.
Propagation Delay vs Input Stage
Supply Voltage
Rise/Fall times vs
Capacitive Load
Propagation Delay vs Output
Stage Supply Voltage
Toggle Rate vs Input Amplitude,
LTC6752/LTC6752-1/LTC6752-2/
LTC6752-4
Propagation Delay vs
Capacitive Load
Toggle Rate vs Input Amplitude,
LTC6752-3
Propagation Delay vs Input
Overdrive
Propagation Delay vs Common
Mode Voltage
Propagation Delay vs
Temperature
OVERDRIVE (mV)
PROPAGATION DELAY (ns)
6752 G25
10
5.0
4.0
3.0
4.5
3.5
2.5
2.0 50 803020 60 100 12070 90 11040
tpdHL
tpdLH
VCC = 5V, VDD = 1.8V
VCC = 2.5V, VDD = 2.5V
VCC VOLTAGE (V)
2.45
PROPAGATION DELAY (ns)
3.00
2.95
2.90
2.75
2.65
2.80
2.70
2.85
2.60 3.65 4.85
6752 G28
5.25
3.25 4.452.85 4.05
tpdLH
tpdHL
3.5
LOAD CAPACITANCE (pF)
0
RISE/FALL TIME (ns)
2010
6752 G31
155
3.0
2.0
1.0
0
2.5
1.5
0.5
tRISE
tFALL
VCC = 5V, VDD = 1.8V
VCC = 2.5V, VDD = 2.5V
20 200
2000
360
INPUT AMPLITUDE (mVP-P)
TOGGLE RATE (MHz)
6752 G32
160
180
200
220
240
260
280
300
320
340 VCM = 1V
RL = 1kΩ
VCC = 5V, VDD = 1.8V
VCC = 2.5V, VDD = 2.5V
VCC = 3.3V, VDD = 3.3V
20 200
2000
300
INPUT AMPLITUDE (mVP-P)
TOGGLE RATE (MHz)
6752 G33
140
160
180
200
220
240
260
280
VCM = 1V
RL = 1kΩ
VCC = 5V, VDD = 1.8V
VCC = 2.5V, VDD = 2.5V
VCC = 3.3V, VDD = 3.3V
VDD VOLTAGE (V)
1.6
PROPAGATION DELAY (ns)
3.7
3.5
3.3
2.7
2.9
3.1
2.5 2.2 3.4
6752 G29
3.6
2.0 3.23.01.8 2.4 2.6 2.8
tpdLH
tpdHL
4.2
4.0
LOAD CAPACITANCE (pF)
0
PROPAGATION DELAY (ns)
2010
6752 G30
155
3.8
3.6
3.2
2.8
2.4
3.4
3.0
2.6
tpdHL
tpdLH
VCC = 5V, VDD = 1.8V
VCC = 2.5V, VDD = 2.5V
4.1
TEMPERATURE (°C)
–55
PROPAGATION DELAY (ns)
25 105–15 65
6752 G27
125
5 85–35 45
3.9
3.7
3.3
2.9
2.5
3.5
3.1
2.7
tpdHL
tpdLH
VCC = 5V, VDD = 1.8V
VCC = 2.5V, VDD = 2.5V
INPUT COMMON MODE VOLTAGE (V)
PROPAGATION DELAY (ns)
6752 G26
–0.2
3.5
3.0
2.5 1.0 1.80.2 1.4 2.2
2.6
0.6
tpd, OUTPUT FALLING (tpdHL)
tpd, OUTPUT RISING(tpdHL)
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
14
6752fc
For more information www.linear.com/LTC6752
Typical perForMance characTerisTics ac
Output Toggle Waveform,
LTC6752-2
Output Toggle Waveforms Q and
Q, LTC6752-3
Toggle Rate vs Capacitive Load,
LTC6752-3
Toggle Rate vs Temperature, (LTC6752/
LTC6752-1/LTC6752-2/LTC6752-4)
Toggle Rate vs Temperature,
LTC6752-3
Output Jitter vs Input Amplitude
Toggle Rate vs Capacitive Load,
(LTC6752/LTC6752-1/LTC6752-2/
LTC6752-4)
VCC = VDD = 2.5V, CLOAD = 5pF,
VOVERDRIVE = 50mV, VCM = 300mV, TA = 25°C, transient input voltage 10MHz, 150mVP-P square wave unless otherwise noted.
VCC ≠ VDD conditions applicable only to the LTC6752-2/ LTC6752-3/LTC6752-4.
350
TEMPERATURE (°C)
–55
TOGGLE RATE (MHz)
25 105–15 65
6752 G34
125
5 85–35 45
150
170
190
210
230
250
270
290
310
330
RL = 1kΩ
VIN = 100mVP-P
SINUSOID
VCC = 5V, VDD = 1.8V
VCC = 2.5V, VDD = 2.5V
VCC = 3.3V, VDD = 3.3V
TEMPERATURE (°C)
–55
TOGGLE RATE (MHz)
25 105–15 65
6752 G35
125
5 85–35 45
150
170
190
210
230
250
270
290
RL = 1kΩ
VIN = 100mVP-P
SINUSOID
VCC = 5V, VDD = 1.8V
VCC = 2.5V, VDD = 2.5V
VCC = 3.3V, VDD = 3.3V
500
450
LOAD CAPACITANCE (pF)
0
TOGGLE RATE (MHz)
2010
6752 G36
155
400
300
200
100
350
250
150 VCC = 5V, VDD = 1.8V
VCC = 2.5V, VDD = 2.5V
RL = 1kΩ
VIN = 100mVP-P
SINUSOID
VCC = 3.3V, VDD = 3.3V
380
330
LOAD CAPACITANCE (pF)
0
TOGGLE RATE (MHz)
2010
6752 G37
155
280
180
80
230
130 VCC = 5V, VDD = 1.8V
VCC = 2.5V, VDD = 2.5V
RL = 1kΩ
VIN = 100mVP-P
SINUSOID
VCC = 3.3V, VDD = 3.3V
INPUT AMPLITUDE (mVP-P)
0
RMS OUTPUT JITTER (ps)
16
14
12
6
2
8
4
10
0300 600
6752 G38
700
200 500100 400
VCC = 5V, VDD = 1.8V
100MHz SINOSOIDAL INPUT
JITTER BANDWIDTH: 10Hz TO 50MHz
VCC = 2.5V, VDD = 2.5V
VCC = 3.3V, VDD = 3.3V
2ns/DIV
6752 G39
500mV/DIV
LTC6752-2
VCC = VDD = 2.5V
CL = 5pF
200MHz
2ns/DIV
6752 G40
500mV/DIV
LTC6752-3
VCC = VDD = 2.5V
CL = 5pF
200MHz
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
15
6752fc
For more information www.linear.com/LTC6752
pin FuncTions
+IN: Positive Input of the Comparator. The voltage range
of this pin can go from VEE to VCC.
–IN: Negative Input of the Comparator. The voltage range
of this pin can go from VEE to VCC.
VCC: Positive Supply Voltage for the LTC6752/LTC6752-1,
Positive Supply Voltage for the Input Stage of the
LTC6752-2/LTC6752-3/LTC6752-4.
VDD: Positive Supply Voltage for the Output Stage of the
LTC6752-2/LTC6752-3/LTC6752-4. Typically the voltage
is from 1.71V to 3.5V. See the section High Speed Board
Design Techniques for proper power supply layout and
bypassing.
VEE: Negative power supply, normally tied to ground. This
can be tied to a voltage other than ground as long as the
constraints for total supply voltage relative to VCC (and
VDD for separate supply operation) are maintained.
SHDN: Active low comparator shutdown, threshold is
0.6V above VEE. The comparator is enabled when this pin
is left unconnected.
LE/HYST: This pin allows the user to adjust the compara-
tor’s hysteresis as well as latch the output state if the pin
voltage is taken within 300mV above VEE. Hysteresis can
be increased or disabled by voltage, current or a resistor
to VEE. Leaving the pin unconnected results in a typical
hysteresis of 5mV.
Q: Comparator Output. Q is driven high when +IN > –IN
and driven low when +IN < –IN.
Q: Comparator Complementary Output (Available on
LTC6752-3 Only). Logical inversion of Q.
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
16
6752fc
For more information www.linear.com/LTC6752
block DiagraM
VCC
VCC
VEE
VEE
6752 BD
+
+
V
EE
VCC
VEE VEE
–IN
VCC VEE
VCC
+IN
+
INPUT
STAGE
HYSTERESIS STAGE
V
DD
VEE
+
GAIN
STAGE
OUTPUT
DRIVER
STAGE
Q
LE/HYST
SHDN
LE/HYST PIN INTERFACE
20k
1.25V
350k
+
+
+
Figure 1. LTC6752/LTC6752-1/LTC6752-2/LTC6752-4 Block Diagram
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
17
6752fc
For more information www.linear.com/LTC6752
applicaTions inForMaTion
Circuit Description
The block diagram is shown in Figure 1. There are dif-
ferential inputs (+IN, IN), a negative power supply (VEE),
two positive supply pins: VCC for the input stage and VDD
for the output stage, an output pin (Q), a pin for latching
and adjusting hysteresis (LE/HYST), and a pin to put the
device in a low power mode (SHDN). In the LTC6752
and LTC6752-1, the two positive supply pins are bonded
together and referred to as VCC. The signal path consists
of a rail-to-rail input stage, an intermediate gain stage,
and an output stage driving a pair of complementary FETs
capable of taking the output pin to either supply rail. A
Latching/Hysteresis interface block allows the user to latch
the output state and/or remove or adjust the comparator
input hysteresis. All of the internal signal paths make use
of low voltage swings for high speed at low power.
The LTC6752-3 has an additional inverted output stage
(not shown) for a complementary logic output signal.
Power Supply Configurations
The LTC6752-2/LTC6752-3/LTC6752-4 have separate
positive supply pins for the input and output stages that
allow for separate voltage ranges for the analog input,
and the output logic. Figure 2 shows a few possible con-
figurations. For reliable and proper operation, the input
supply pin should be between 2.45V and 5.25V above the
negative supply pin, and the output supply pin should be
between 1.71V and 3.5V above the negative supply pin.
There are no restrictions regarding the sequence in which
the supplies are applied, as long as the absolute-maximum
ratings are not violated.
The LTC6752 and LTC6752-1 have only one positive sup-
ply pin. The supply voltage should be between 2.45V and
3.5V for proper and reliable operation.
Input Voltage Range and Offset
The LTC6752 family uses a rail-to-rail input stage that
consists of a pnp pair and an npn pair that are active over
different input common mode ranges. The pnp pair is ac-
tive for inputs between VEE 0.2V and approximately VCC
1.5V (low common mode region of operation). The npn
pair is active for inputs between approximately VCC – 1V
and VCC + 0.1V (high common mode region of operation).
Partial activation of both pairs occurs when one input is in
the low common mode region of operation and the other
input is in the high common mode region of operation, or
either of the inputs is between approximately VCC – 1.5V
and VCC 1V (transition region). The device has small,
trimmed offsets as long as both inputs are completely
in the low or high common mode region of operation.
In the transition region, the offset voltage may increase.
Applications that require good DC precision should avoid
the transition region.
Input Bias Current
When both inputs are in the low common mode region,
the input bias current is negative, with current flowing
out of the input pins. When both inputs are in the high
common mode region, the input bias current is positive,
with current flowing into the input pins.
The input stage has been designed to accommodate
large differential input voltages without large increases
in input bias current. With one input at the positive input
supply rail and the other input at the negative supply rail,
the magnitude of the input bias currents at either pin is
typically less than 3.5μA.
Figure 2. Typical Power Supply Configurations (Applicable to the LTC6752-2/LTC6752-3/LTC6752-4)
+
VCC
VDD
3V3V
6752 F02
Q
VEE
0V
(a) SINGLE SUPPLY
–IN
+IN
+
VCC
VDD
1.8V5V
Q
VEE
0V
(b) OUTPUT SUPPLY < INPUT SUPPLY
–IN
+IN
+
VCC
VDD
3.5V2.5V
Q
VEE
0V
(c) OUTPUT SUPPLY > INPUT SUPPLY
–IN
+IN
+
VCC
VDD
0V2.5V
Q
VEE
–2.5V
(d) NEGATIVE OUTPUT LOGIC
–IN
+IN
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
18
6752fc
For more information www.linear.com/LTC6752
applicaTions inForMaTion
Input Protection
The input stage is protected against damage from condi-
tions where the voltage on either pin exceeds the supply
voltage (VCC to VEE) without external protection. External
input protection circuitry is only needed if input currents
can exceed the absolute maximum rating. For example,
if an input is taken beyond 300mV of either the positive
or negative supply, an internal ESD protection diode will
conduct and an external resistor should be used to limit
the current to less than 10mA.
Outputs
The LTC6752 family has excellent drive capability. The
comparators can deliver typically ±22mA output current
for an output supply of 2.5V, and ±39mA output current
for a 3.3V output supply. Attention must be paid to keep
the junction temperature of the IC below 150°C should the
output have a continuous short-circuit condition.
Logic Drive Capability
The LTC6752 family has been designed to drive CMOS
logic with a supply of 3.3V, 2.5V and 1.8V. For device reli-
ability, the output power supply (VDD) should not be higher
than 3.6V above the negative supply. When VDD is 3V or
higher the CMOS outputs of the LTC6752 family provide
valid TTL logic threshold levels and can easily interface
with TTL logic devices operating with a 5V supply. This is
possible because all of the threshold levels associated with
TTL logic (VIH/VIL/VOH/VOL) are less than or equal to 2.4V
Capacitive Loads
The LTC6752 family can drive capacitive loads. Transient
performance parameters in the Electrical Characteristics
Tables and Typical Characteristics section are for a load
of 5pF, corresponding to a standard TTL/CMOS load. The
devices are fully functional for larger capacitive loads,
however speed performance will degrade. The graphs titled
Propagation Delay vs Capacitive Load and Toggle Rate vs
Capacitive Load illustrate the impact of changes to the total
capacitive load. For optimal speed performance, output
load capacitance should be reduced as much as possible.
ESD
The LTC6752 family members have reverse-biased ESD
protection diodes on pins as shown in Figure 1.
There are additional clamps between the positive and
negative supplies that further protect the device during
ESD strikes. Hot-plugging of the device into a powered
socket is not recommended since this can trigger the clamp
resulting in large currents flowing between the supply pins.
Hysteresis
Comparators have very high open-loop gain. With slow
input signals that are close to each other, input noise can
cause the output voltage to switch randomly. This can be
addressed by hysteresis which is positive feedback that
increases the trip point in the direction of the input signal
transition when the output switches. This pulls the inputs
away from each other, and prevents continuous switching
back and forth. The addition of positive feedback also has
the effect of making the small signal gain infinite around the
trip points. Hysteresis is designed into most comparators
and the LTC6752 family has adjustable hysteresis with a
default hysteresis of 5mV.
The input-output transfer characteristic is illustrated in
Figure 3 showing the definitions of VOS and HYST based
upon the two measurable trip points.
In some cases, additional noise immunity is required
above what is provided by the nominal 5mV hysteresis.
Figure 3
VOH
VOL
0
VOS = 6752 F03
V
OUT
VOS
VTRIP+
VHYST
(= VTRIP+ – VTRIP)
∆VIN = VIN+ – VIN
VTRIP+ + VTRIP
2
VTRIP
FOR VTRIP+ = 3mV,
VTRIP = –2mV,
VOS = 0.5mV,
VHYST = 5mV
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
19
6752fc
For more information www.linear.com/LTC6752
applicaTions inForMaTion
Conversely, when processing small or fast differential sig-
nals, hysteresis may need to be eliminated. The LTC6752-1/
LTC6752-2/LTC6752-3 provide a hysteresis pin, LE/
HYST, that can be used to increase the internal hysteresis,
completely remove it, or enable the output to latch. For
these 3 options of the LTC6752, the internal hysteresis
is disabled when the LE/HYST pin voltage is above 1.7V.
Although eliminating hysteresis does reduce the voltage
gain of the comparator to a finite value, in many cases it
will be high enough (typically 6000V/V) to process small
input signals. The output will latch when the LE/HYST pin
voltage is below 0.3V. The internal hysteresis will increase
as the voltage of the pin is adjusted from its default open
circuit value of 1.25V to 800mV.
The LE/HYST pin can be modeled as a 1.25V voltage
source in series with a 20k resistor. The simplest method
to increase the internal hysteresis is to connect a single
resistor as shown in Figure 4 between the LE/HYST pin and
VEE to adjust hysteresis. Figure 5 shows how hysteresis
typically varies with the value of the resistor.
In addition to adjusting hysteresis using the LE/HYST
pin, additional hysteresis can be added using positive
feedback from the output back to the positive input, as
shown in Figure 6.
The offset (with respect to the input signal) and hysteresis
become
VOS _ FB =
V
DD
+V
EE
( )
2
R1
R1+R2+VREF R2
R1+R2 VOS
VOH
2
R1
R1+R2
+VOL
R2
R1+R2
(1)
VHYST _FB =VDD VEE
( )
R1
R1+R2+VOL
R2
R1+R2+
VOH
R1
R1+R2
+VHYST (2)
VOS_FB and VHYST_FB denote the values of offset and
hysteresis with positive feedback present. VHYST denotes
the hysteresis of the device without positive feedback.
For light loads, VOH (output swing high) and VOL (output
swing low) are typically a few mV (typically are less than
10mV for a 500µA load).
On a 3.0V total supply with VEE = 0V, an increase in
hysteresis of approximately 300mV can be obtained with
VREF = 1.25V, R2 = 4.53kΩ , R1 = 511Ω, with an induced
offset of approximately 1.275V.
Figure 4. Adjusting Hysteresis Using an External
Resistor at the LE/HYST Pin
Figure 5. Hysteresis vs Control Resistor
Figure 6. Additional Hysteresis Using Positive Feedback
6752 F04
+
VCC
VDD Q
VEE
LE/HYST
R
–IN
+IN
6752 F06
+
VCC
V
REF
SIGNAL
VDD Q
VEE
R2
R1
50
CONTROL RESISTANCE (kΩ)
30
HYSTERISIS (mV)
230 430130 330
6752 F05
480
180 38080 280
0
5
10
15
20
25
30
35
40
45 VCC = VDD = 2.5V
VCM = 0.3V
TA = 25°C
CONTROL RESISTOR CONNECTED
BETWEEN LE/HYST PIN AND VEE
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
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6752fc
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applicaTions inForMaTion
Latching
The internal latch of the LTC6752-1/LTC6752-2/LTC6752-3
retains the output state when the LE/HYST pin is taken to
less than 300mV above the negative supply.
Figures 7a to 7e illustrate the latch timing definitions. The
latch setup time is defined as the time for which the input
should be stable before the latch pin is asserted low to
ensure that the correct state will be held at the output. The
latch hold time is the interval after which the latch pin is
asserted in which the input signal must remain stable for
the output to be the correct state at the time latch was
asserted. The latch to output delay (tPL) is the time taken
for the output to return to input control after the latch
pin is released. Latching is disabled if the LE/HYST pin
is left floating. Both outputs of the LTC6752-3 are latch
controlled simultaneously.
6752 F07a
+IN – –IN
t > tSETUP
tPD
Q
LE/HYST
6752 F07d
+IN – –IN
t > tHOLD
tPD
Q
LE/HYST
t > tSETUP
6752 F07e
+IN – –IN
tPL
Q
LE/HYST
6752 F07c
+IN – –IN
t < tHOLD
tPD
Q
LE
/HYST
6752 F07b
+IN – –IN
t < tSETUP
Q
LE/HYST
Figure 7a. Input State Change Properly Latched
Figure 7b. Input Change Setup Time Too Short
Figure 7c. Input State Not Held Long Enough.
Wrong Output State Latched
Figure 7d. Short Input Pulse Properly
Captured and Latched
Figure 7e. Latched Output Disabled
Shutdown
The LTC6752-2 and LTC6752-3 have shutdown pins
(SHDN, active low) that can reduce the total supply cur-
rent to a typical value of 580μA for the LTC6752-2 and
650µA for the LTC6752-3 (2.5V supply). When the part is
in shutdown, the outputs are placed in a high-impedance
state, since PFET and NFET output transistors whose drains
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
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applicaTions inForMaTion
are tied to the output pins are cut off and cannot source/
sink any current. The shutdown pin needs to be taken to
within 600mV of the negative supply for the part to shut
down. When left floating, the shutdown pin is internally
pulled towards the positive supply, and the comparator
remains fully biased on.
Dispersion
Dispersion is defined as the change in propagation delay
for different input conditions. It becomes very crucial in
timing sensitive applications. Overdrive dispersion from
10mV overdrive to 125mV overdrive is typically less than
1.8ns (150mV total step size). The graph titled Propagation
Delay vs Common Mode Voltage shows the dispersion
due to shifts in input common mode voltage.
Jitter
The LTC6752 family has been designed for low phase
noise and jitter. This allows it to be used in applications
where high frequency low amplitude sine waves need to
be converted to full-logic level square waves with mini-
mal additive jitter. The graph titled Output Jitter vs Input
Amplitude demonstrates the additive jitter of the LTC6752
family for different amplitudes of a sinusoidal input. Refer
to the Electrical Characteristics table to see how jitter varies
with signal frequency.
High Speed Board Design Techniques
Being very high speed devices, members of the LTC6752
family are prone to output oscillations if certain guidelines
are not followed at the board level. Low impedance supply
planes, especially for the VDD and VEE pins, help to reduce
supply bounce related oscillations. Supply bounce tends to
worsen at higher output supply voltages due to larger swings
and higher output current drive capability. Parasitic feedback
between the output and input pins should be minimized. The
pinouts of the LTC6752 family members have been arranged
to minimize parasitic feedback. Input and output traces on
the board should be placed away from each other. If that is
not possible a ground or supply trace should be used as a
guard to isolate them. If possible, a supply/ground trace that
is not directly connected to the supply pins of the device,
but rather directly connected to the supply terminal of the
board, should be used for such a purpose.
The positive supply pins should be adequately bypassed
to the VEE pin to minimize transients on the supply. Low
ESR and ESL capacitors are required due to the high speed
nature of the device. Even a few nanohenries of parasitic
trace inductance in series with the supply bypassing can
cause several hundred millivolts of disturbance on the supply
pins during output transitions. A 2.2µF capacitor in parallel
with multiple low ESL, low ESR 100nF capacitors connected
as close to the supply pins as possible to minimize trace
impedance is recommended. In many applications the VEE
pin will be connected to ground. In applications where the
VEE pin is not connected to ground, the positive supplies
should still be bypassed to VEE. The VEE pin should also then
be bypassed to a ground plane with a 2.2µF capacitor in
parallel with low ESL, low ESR 100nF capacitors if possible.
For devices with separate positive input and output sup-
plies, capacitors should not be placed between the two
positive supplies; otherwise disturbances due to output
switching can couple back to the inputs.
To minimize supply bounce, the board layout must be made
with careful consideration of the supply current return
paths. The output current will return back to the supply
via the lowest impedance path available. If the terminating
connection of the load is easily available on the board, VEE
should be bypassed to the terminating connection using
2.2µF and 100nF capacitors as described previously.
Due to the fast rise and fall times of the LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/LTC6752-4, output traces should be
shielded with a low impedance ground plane to minimize
electromagnetic interference. Due to the complementary
nature of its outputs, the LTC6752-3 can provide a first
order cancellation of EMI effects.
When the input slew rate is small, sustained oscillations
can occur at the output pin while the input is transitioning
due to even one millivolt of ground bounce. For applica-
tions where the input slew rate is low, internal hysteresis
should not be removed by taking the LE/HYST pin high,
as the addition of hysteresis makes the comparators more
immune to disturbances such as ground bounce. Increas-
ing hysteresis by adjusting the LE/HYST pin voltage or by
adding positive feedback as discussed in the section on
hysteresis can further improve noise immunity.
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
22
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Typical applicaTions
High Speed Clock Restoration/Level Translation
Circuit
High speed comparators are often used in digital systems
to recover distorted clock waveforms. The separate input/
output supplies feature of the LTC6752-2 allows it to be
used in applications where signals need to be shifted from
one voltage domain to another. Figure 8 shows a circuit that
can perform both recovery and level translation functions.
In this application, the input clock signal comes from a
source operating from 5V, and the signal is required to
drive a receiver operating on 1.8V. The 5V input supply/1.8V
output supply feature of this part is ideal for such a situation.
If the input signal gets distorted and its amplitude severely
reduced due to stray capacitance, stray inductance or due
to reflections on the transmission line, the LTC6752-2 can
be used to convert it into a full scale digital output signal
that can drive the receiver.
Figure 9 shows the input and output waveforms of the
LTC6752-2, used to recover a distorted 150mVP-P 200MHz
signal at a common mode of 2.5V with respect to its nega-
tive supply, into a full scale 1.8V output signal. AC-coupling
could have been used at the input of the comparator, how-
ever to preserve input duty cycle information DC-coupling
may be preferable, and that is where having a wide input
common mode range is an advantage.
Optical Receiver Circuit
The LTC6752, along with a high speed high performance
FET input operational amplifier like the LTC6268, can be
used to implement an optical receiver as shown in Figure 10.
Figure 11 shows the output of the LTC6268 driving the –IN
pin of the LTC6752-2, the +IN pin of the LTC6752-2, and
the LTC6752-2 output. The photodiode is being driven by
a light source of sinusoidally varying intensity.
Figure 10. Optical Receiver Circuit
Figure 9
V
OUT, 500mV/DIV
VIN, 50mV/DIV
2ns/DIV 6752 F09
VREF
3.3V
3.3V
3.3V
3.3V 5.49k
20k
+
LTC6268
0V TO 3.3V
OUT
1k
6752 F10
+VCC
LTC6752-2
VDD
VEE
LE/HYST
SHDN
Q
4.53k
0.1µF
0.1µF
47.6k
FCI-125
1k
Figure 8. High Speed Clock Restoration/Level
Translation/Level Shifting Circuit
+
VCC
VDD
VEE + 1.8V
VEE
V
EE
+ 1.8VV
EE
+ 5V
6752 F08
200MHz
CLOCK
SIGNAL
ATTENUATED
150mVP-P
200MHz,
VCM = 2.5V
~1.8VP-P
200MHz,
CLOCK
SIGNAL
LONG
TRACE
VEE
VREF = VEE + 2.5V
CLOCK/DATA
RECEIVER
LTC6752-2
VEE
CLOCK/DATA
SOURCE
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
23
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For more information www.linear.com/LTC6752
Typical applicaTions
COMPARATOR U2
TIMING
RESISTOR R
TIMING
CAPACITOR C
3.3V
100pF
2k
22k
+
6.65k
22k
VCC
3.3V
COMPARATOR U1
3.3V
15k
OUTPUT 3.3V 100ns PULSE
+VCC
LTC6752-2
INPUT 15mV TO 3.3V PULSE
MINIMUM PULSE WIDTH 5ns
VDD
VEE
LE/HYST
SHDN
OUT
49.9Ω 1000pF
1k
SOD-123
OSA
49.9Ω
Z
OUT = 50Ω
LTC6752-2
VDD
VEE
LE/HYST
SHDN
OUT
Figure 11
Figure 12
Figure 13
500mV/DIV
IN
IN+
OUT
0
0.5
1.0
1.5
2.0
2.5
4.0
3.5
3.0
4.5
5.0
10ns/DIV
90
80706050403020100
6752 F11
OUTPUT, 2V/DIV
INPUT, 20mV/DIV
20ns/DIV 6752 F13
Pulse Stretcher Circuit/Monostable Multivibrator
For detecting short pulses from a single sensor, a pulse
stretcher is often required. The circuit of Figure 12 acts as
a one-shot, stretching the width of an incoming pulse to a
consistent ~100ns. The circuit works as follows: Compara-
tor U1 functions as a threshold detector, and Comparator
U2 functions as a one-shot. Comparator U1 is biased with
a threshold of 11mV to overcome comparator and system
offsets, and establish a low output in the absence of an
input signal. An input pulse causes the output of U1 to go
high, which then causes the output of U2 to go high. The
output of U2 is fed back to the input of the 1st compara-
tor, Timing Capacitor C now begins charging through R.
After 100ns, U2 goes low, allowing U1 also to go low. A
new pulse at the input of U2 can now restart the process.
Timing capacitor C can be increased without limit for
longer output pulses.
Figure 13 shows input and output waveforms for the pulse
stretcher circuit.
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
24
6752fc
For more information www.linear.com/LTC6752
Typical applicaTions
Common Mode Rejecting Line Receiver
Differential electrical signals being transmitted over long
cables are often attenuated. Electrical noise on the cables
can take the form of common mode signals.
The LTC6752 comparators can be used to retrieve attenu-
ated differential signals that have been corrupted by high
frequency common mode noise, as shown in Figure 14.
Figure 15 shows an LTC6752-2 retrieving a 200MHz,
200mVP-P differential input signal that has 2.5V of random,
common mode noise superimposed on it. The input supply
(VCC) used was 5V and the output supply used was 2.7V.
A small amount of modulation is seen at the output due
to a small amount of differential modulation at the inputs,
which causes cycle to cycle variations in propagation delay.
Fast Event Capture
The circuit shown in Figure 16 can be used to capture
small and fast events. The comparator output is used to
signal the latch pin and hold the output in the HIGH state.
The circuit will reset when the RESET line is low. An open
drain 1.5ns NAND gate is used to both invert the output
signal and is used to MUX in the RESET line from the
supervising circuit. One important feature of the NAND is
that it is open drain which allows the comparator to use
either its default 5mV of hysteresis or a user programmed
hysteresis. The latch recovery time of this circuit is roughly
210ns and is dominated by the time constant created by the
capacitance seen at the output of the NAND gate and the
20k series resistance of the LE/HYST pin. The waveforms
are shown in Figure 17.
Figure 14
Figure 15
+
VCC = 5V
VDD = 2.7V
Q
6752 F14
SMALL DIFFERENTIAL SIGNAL WITH
LARGE COMMON MODE COMPONENT
VEE
+IN
–IN
LTC6752-2
500mV/DIV
–IN +INQ
50ns/DIV 6752 F15
Figure 16
Figure 17
500mV/DIV
50ns/DIV 6752 F17
RESET
INPUT REF
OUT
3.3V
6752 F16
+VCC
LTC6752-2
VDD
VEE
LE/HYST
SHDN
Q
2.2μF 0.1μF
0.1μF
200Ω182k
EVENT IN
50mV, 10ns INPUT
RESET
3.3V
REF
NXP 74LVC1G38
OUT
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
25
6752fc
For more information www.linear.com/LTC6752
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S5 TSOT-23 0302
PIN ONE
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
package DescripTion
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
26
6752fc
For more information www.linear.com/LTC6752
MSOP (MS8) 0213 REV G
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ±0.152
(.193 ±.006)
8765
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.52
(.0205)
REF
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ±.0015)
TYP
0.65
(.0256)
BSC
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev G)
package DescripTion
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
27
6752fc
For more information www.linear.com/LTC6752
1.15 – 1.35
(NOTE 4)
1.80 – 2.40
0.15 – 0.30
6 PLCS (NOTE 3)
SC6 SC70 1205 REV B
1.80 – 2.20
(NOTE 4)
0.65 BSC
PIN 1
0.80 – 1.00
1.00 MAX
0.00 – 0.10
REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB
2.8 BSC
0.47
MAX
0.65
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.8 REF
1.00 REF
INDEX AREA
(NOTE 6)
0.10 – 0.18
(NOTE 3)
0.26 – 0.46
GAUGE PLANE
0.15 BSC
0.10 – 0.40
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638 Rev B)
package DescripTion
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
28
6752fc
For more information www.linear.com/LTC6752
3.00 ± 0.10
(4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(4-SIDES)
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
1
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
11 12
2
0.50 BSC
0.200 REF
2.10 ±0.05
3.50
±0.05
0.70 ±0.05
0.00 – 0.05
(UD12) QFN 0709 REV Ø
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
UD Package
12-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1855 Rev Ø)
package DescripTion
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
29
6752fc
For more information www.linear.com/LTC6752
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 01/15 Addition of LTC6752-1 and LTC6752-4 options.
SC6 Package added.
Fast Event Capture added to Typical Applications.
All
2
24
B 06/15 Test condition for CMRR_LVCM updated: VCM = VEE – 0.2V to VCC – 1.5V
Electrical Characteristics section updated to show that VLE/HYST, RHYST, IIH_LE, IIL_LE specifications apply over the
specified temperature range.
Figure 1 updated to show hysteresis symbol.
The latched output disable description and Figure 7 corrected to show the latch to output delay (tPL) instead of latch
propagation delay (tPDL).
3, 6, 8
5, 7, 9
16
20
C 04/17 Addition of extended temperature range under Features
Addition of MP, extended temperature part
Addition of extended temperature range on Note 5
Updated web links
1
2, 3
9
25 to 28
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
30
6752fc
For more information www.linear.com/LTC6752
LINEAR TECHNOLOGY CORPORATION 2014
LT 0417 REV C • PRINTED IN USA
www.linear.com/LTC6752
Typical applicaTion
relaTeD parTs
PART NUMBER DESCRIPTION COMMENTS
High Speed Comparators
LT1715 4ns 150MHz Dual Comparators 4.6mA at 3V
LT1711 High Speed Rail-to-Rail Comparators 3V/5V/±5V, 4.5ns at 20mV Overdrive
LT1713/LT1714 Single/Dual Low Power Rail-to-Rail Comparators 2.7V/5V/±5V, 7ns at 20mV Overdrive
LT1719/LT1720 Dual/Quad 4.5ns Rail-to-Rail Output Comparators 4mA/Comparator, 7ns at 5mV Overdrive
LT1394 7ns Single Supply Ground Sensing Comparator 6mA, 800μV Offset
Clock Buffers/Logic Converters
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Low Phase Noise, Dual Output Buffer/Driver/Logic
Converter
LVPECL/LVDS/CMOS Outputs, Additive Jitter 45fsRMS (LTC6957-1)
High Speed Operational Amplifiers
LTC6252/LTC6253/
LTC6254
Single/Dual/Quad 3.5mA 720MHz 280V/μs, 2.75nV/√Hz, Rail-to-Rail I/O
LTC6246/LTC6247/
LTC6248
Single/Dual/Quad 1mA, 180MHz 90V/μs, 4.2nV/√Hz,Rail-to-Rail I/O
LTC6255/LTC6256/
LTC6257
Single/Dual/Quad 65µA, 6.5MHz
LTC6240/LTC6241/
LTC6242
18MHz, Low Noise, CMOS Rail-to-Rail Outputs
LTC6406 3GHz, Differential Amplifier/Driver Rail-to-Rail Inputs
LTC6409 10GHz Differential Amplifier/ADC Driver 1.1nV/√Hz
200MHz Clock Restoration/Level shifting
+
VCC
VDD
VEE + 1.8V
VEE
V
EE
+ 1.8VV
EE
+ 5V
6752 TA02a
200MHz
CLOCK
SIGNAL
ATTENUATED
150mVP-P
200MHz,
VCM = 2.5V
~1.8VP-P
200MHz,
CLOCK
SIGNAL
LONG
TRACE
VEE
VREF = VEE + 2.5V
CLOCK/DATA
RECEIVER
LTC6752-2
VEE
CLOCK/DATA
SOURCE
V
OUT, 500mV/DIV
VIN, 50mV/DIV
2ns/DIV 6752 TA02b
VREF

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