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LT1719 Datasheet

Linear Technology/Analog Devices

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Datasheet

LT1719
1
1719fa
TYPICAL APPLICATION
FEATURES DESCRIPTION
APPLICATIONS
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. UltraFast is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
OVERDRIVE (mV)
0
DELAY (ns)
30 50
1719 TA02
10 20 40
8
7
6
5
4
3
2
1
0
25°C
V
STEP
= 100mV
V
+
= 5V
C
LOAD
= 10pF
RISING EDGE
(t
PDLH
)
FALLING EDGE
(t
PDHL
)
n UltraFast: 4.5ns at 20mV Overdrive
7ns at 5mV Overdrive
n Low Power: 4.2mA at 3V
n Separate Input and Output Power Supplies
(SO-8 Only)
n Output Optimized for 3V and 5V Supplies
n TTL/CMOS Compatible Rail-to-Rail Output
n Low Power Shutdown Mode: 0.1μA
n Low Profi le (1mm) SOT-23 (ThinSOT™) Package
The LT
®
1719 is an UltraFast™ comparator optimized for low
voltage operation. The input voltage range extends from
100mV below VEE to 1.2V below VCC. Internal hysteresis
makes the LT1719 easy to use even with slow moving input
signals. The rail-to-rail outputs directly interface to TTL
and CMOS. Alternatively the symmetric output drive can be
harnessed for analog applications or for easy translation to
other single supply logic levels. A shutdown control allows
for reduced power consumption and extended battery life
in portable applications.
The LT1719 is available in the SO-8 and 6-lead SOT-23
package. The SO-8 package has separate supplies which
allow fl exible operation, accomodating separate analog
input ranges and output logic levels.
For a dual/quad comparator with similar performance, see
the LT1720/LT1721.
n High Speed Differential Line Receiver
n Crystal Oscillator Circuits
n Level Translators
n Threshold Detectors/Discriminators
n Zero-Crossing Detectors
n High Speed Sampling Circuits
n Delay Lines
2.7V to 6V Crystal Oscillator with TTL/CMOS Output Propagation Delay vs Overdrive
+
C1
LT1719
2.7V TO 6V
2k
620Ω
220Ω
1MHz TO 10MHz
CRYSTAL (AT-CUT)
2k
1719 TA01
0.1μF 1.8k
OUTPUT
GROUND
CASE
4.5ns Single/Dual Supply
3V/5V Comparator with
Rail-to-Rail Output
LT1719
2
1719fa
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(Note 1)
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1719CS8#PBF LT1719CS8#TRPBF 1719 8-Lead Plastic SO 0°C to 70°C
LT1719IS8#PBF LT1719IS8#TRPBF 1719I 8-Lead Plastic SO –40°C to 85°C
LT1719CS6#PBF LT1719CS6#TRPBF LTHW 6-Lead Plastic TSOT-23 0°C to 70°C
LT1719IS6#PBF LT1719IS6#TRPBF LTJF 6-Lead Plastic TSOT-23 –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
Supply Voltage
+VS to GND (LT1719S8) ........................................ 7V
V
CC to VEE (LT1719S8) ........................................ 12V
+VS to VEE (LT1719S8) ....................................... 12V
V
EE to GND (LT1719S8) ....................... –12V to 0.3V
V
+ to V (LT1719S6) ...............................................7V
Input Current (+IN, –IN or SHDN) ...................... ±10mA
Output Current (Continuous) ........................... ±20mA
Operating Temperature Range
C-Grade .................................................. 0°C to 70°C
I-Grade ............................................... –40°C to 85°C
Junction Temperature ......................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................. 300°C
TOP VIEW
+VS
OUT
SHDN
GND
VCC
+IN
–IN
VEE
S8 PACKAGE
8-LEAD PLASTIC SO
1
2
3
4
8
7
6
5
+
–IN 1
V 2
+IN 3
6 SHDN
5 OUT
4 V+
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 110°C/W TJMAX = 150°C, θJA = 230°C/W
LT1719
3
1719fa
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC – VEE Input Supply Voltage (LT1719S8 Only) l2.7 10.5 V
+VSOutput Supply Voltage (LT1719S8 Only) l2.7 6 V
V+ – VSupply Voltage (LT1719CS6 Only) l2.7 6 V
VCMR Input Voltage Range (Note 2) (LT1719S8)
(LT1719S6)
l
l
VEE – 0.1
V – 0.1
VCC – 1.2
V+ – 1.2
V
V
VTRIP+
VTRIPInput Trip Points (Note 3) l
l
–1.5
–5.5
5.5
1.5
mV
mV
VOS Input Offset Voltage (Note 3)
l
0.4 2.5
3.5
mV
mV
VHYST Input Hysteresis Voltage (Note 3) l2.0 3.5 7 mV
ΔVOS/ΔT Input Offset Voltage Drift l10 μV/°C
IBInput Bias Current l–6 –2.5 0 μA
IOS Input Offset Current l0.2 0.6 μA
CMRR Common Mode Rejection Ratio (Note 4) (LT1719S8)
(Note 5) (LT1719S6)
l
l
55
55
70
65
dB
dB
PSRR Power Supply Rejection Ratio (Note 6) (LT1719S8)
(Note 7) (LT1719S6)
65
65
80
80
dB
dB
AVVoltage Gain (Note 8)
VOH Output High Voltage ISOURCE = 4mA, VIN = VTRIP+ + 10mV (LT1719S8)
(LT1719S6)
l
l
+VS – 0.4
V+ – 0.4
V
V
VOL Output Low Voltage ISINK = 10mA, VIN = VTRIP – 10mV l0.4 V
tPD20 Propagation Delay VOVERDRIVE = 20mV (Note 9) VEE = 0V(LT1719S8)
V = 0V(LT1719S6) l
4.5 6.5
8.0
ns
ns
VOVERDRIVE = 20mV, VEE = –5V (LT1719S8 Only) 4.2 ns
tPD5 Propagation Delay VOVERDRIVE = 5mV (Notes 9, 10) VEE = 0V(LT1719S8)
V = 0V(LT1719S6) l
710
13
ns
ns
tSKEW Propagation Delay Skew (Note 11) 0.5 1.5 ns
trOutput Rise Time 10% to 90% 2.5 ns
tfOutput Fall Time 90% to 10% 2.2 ns
tJITTER Output Timing Jitter VIN = 1.2VP-P (6dBm), ZIN = 50Ω tPD+
f = 20MHz tPD
15
11
psRMS
psRMS
fMAX Maximum Toggle Frequency VOVERDRIVE = 50mV, +VS or V+ = 3V
VOVERDRIVE = 50mV, +VS or V+ = 5V
70
62.5
MHz
MHz
tOFF Turn-Off Delay Time to ZOUT10kΩ 75 ns
tON Wake-Up Delay Time to VOH or VOL, ILOAD = 1mA 350 ns
ICC Positive Input Stage Supply Current +VS = VCC = 5V, VEE = –5V l1 2.2 mA
(LT1719S8 Only) +VS = VCC = 3V, VEE = 0V l0.9 1.8 mA
IEE Negative Input Stage Supply Current +VS = VCC = 5V, VEE = –5V l–4.8 –2.6 mA
(LT1719S8 Only) +VS = VCC = 3V, VEE = 0V l–3.8 –2.2 mA
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCM = 1V, VSHDN = 0.5V, VOVERDRIVE = 20mV, COUT = 10pF and for the
LT1719S8 VCC = +VS = 5V and VEE = –5V, for the LT1719S6 V+ = 5V, V = 0V, unless otherwise specifi ed.
LT1719
4
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ISPositive Output Stage Supply Current +VS = VCC = 5V, VEE = –5V l4.2 8 mA
(LT1719S8 Only) VS = VCC = 3V, VEE = 0V l3.3 6 mA
I+Supply Current (LT1719S6) V+ = 5V l4.6 9 mA
V+ = 3V l4.2 7 mA
ISHDN5 Shutdown Pin Current +VS or V+ = 5V l–300 –110 –30 μA
ISHDN3 Shutdown Pin Current +VS or V+ = 3V l–200 –80 –20 μA
ICCS
ISS
IEES
I+S
ICCSO
ISSO
IEEO
I+O
Disabled Supply Currents (LT1719S8)
(LT1719S8)
(LT1719S8)
(LT1719S6)
(LT1719S8)
(LT1719S8)
(LT1719S8)
(LT1719S6)
+VS = 6V, VCC = 5V, VEE = –5V
VSHDN = +VS – 0.5V
l
l
l–30
0.2
7
–0.2
30
50
μA
μA
μA
V+ = 6V, VSHDN = +VS – 0.5V l780 μA
+VS = 6V, VCC = 5V, VEE = –5V
Shutdown Pin Open
l
l
l–20
0.1
0.1
0.1
20
20
μA
μA
μA
V+ = 6V, Shutdown Pin Open l0.2 40 μA
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCM = 1V, VSHDN = 0.5V, VOVERDRIVE = 20mV, COUT = 10pF and for the
LT1719S8 VCC = +VS = 5V and VEE = –5V, for the LT1719S6 V+ = 5V, V = 0V, unless otherwise specifi ed.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: If one input is within these common mode limits, the other input
can go outside the common mode limits and the output will be valid.
Note 3: The LT1719 comparator includes internal hysteresis. The trip
points are the input voltage needed to change the output state in each
direction. The offset voltage is defi ned as the average of VTRIP+ and VTRIP,
while the hysteresis voltage is the difference of these two.
Note 4: The LT1719S8 common mode rejection ratio is measured with
VCC = 5V, VEE = – 5V and is defi ned as the change in offset voltage measured
from VCM = –5.1V to VCM = 3.8V, divided by 8.9V.
Note 5: The LT1719S6 common mode rejection ratio is measured with
V+ = 5V and is defi ned as the change in offset voltage measured from
VCM = –0.1V to VCM = 3.8V, divided by 3.9V.
Note 6: The LT1719S8 power supply rejection ratio is measured with
VCM = 1V and is defi ned as the worst of: the change in offset voltage from
VEE = –5.5V to VEE = 0V divided by 5.5V, or the change in offset voltage
from VCC = +VS = 2.7V to VCC = +VS = 6V (with VEE = 0V) divided by 3.3V.
Note 7: The LT1719S6 power supply rejection ratio is measured with
VCM = 1V and is defi ned as the change in offset voltage measured from
V+ = 2.7V to V+ = 6V, divided by 3.3V.
Note 8: Because of internal hysteresis, there is no small-signal region in
which to measure gain. Proper operation of internal circuity is ensured by
measuring VOH and VOL with only 10mV of overdrive.
Note 9: Propagation delay measurements made with 100mV steps.
Overdrive is measured relative to VTRIP±.
Note 10: tPD cannot be measured in automatic handling equipment with
low values of overdrive. The LT1719 is 100% tested with a 100mV step
and 20mV overdrive. Correlation tests have shown that tPD limits can be
guaranteed with this test, if additional DC tests are performed to guarantee
that all internal bias conditions are correct.
Note 11: Propagation Delay Skew is defi ned as:
t
SKEW = |tPDLH – tPDHL|
LT1719
5
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TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Supply Current
vs Supply Voltage
SUPPLY VOLTAGE, V
CC
= +V
S
OR V
+
(V)
2.5
V
OS
AND TRIP POINT VOLTAGE (mV)
3
2
1
0
–1
–2
–3 4.0 5.0
1719 G01
3.0 3.5 4.5 5.5 6.0
V
TRIP+
V
OS
V
TRIP
25°C
V
CM
= 1V
V
EE
OR V
= GND
TEMPERATURE (°C)
–3
V
OS
AND TRIP POINT VOLTAGE (mV)
–1
1
3
–2
0
2
–20 20 60 100
1719 G02
140–40–60 0 40 80 120
V
TRIP+
V
OS
V
TRIP
+V
S
= V
CC
or V
+
= 5V
V
CM
= 1V
V
EE
OR V
= GND
TEMPERATURE (°C)
–50
0
3.8
4.2
25 75
1719 G03
–0.2
–5.0
–25 0 50 100 125
–5.2
–5.4
4.0
COMMON MODE INPUT VOLTAGE (V)
+V
S
= V
CC
OR V
+
= 5V
V
EE
= –5V (LT1719S8)
V
= GND (LT1719S6)
DIFFERENTIAL INPUT VOLTAGE (V)
–5
–7
INPUT BIAS (μA)
–6
–4
–3
–2
1234
2
1719 G04
–5
–4 –3 –2 –1 0 5
–1
0
1
25°C
TEMPERATURE (°C)
–50
SUPPLY CURRENT (mA)
100
1339 G05
050
10
8
6
4
2
0
–2
–4
–6 –25 25 75 125
V
CC
= +V
S
OR V
+
= 5V
V
EE
= GND I
+
(LT1719S6)
+I
S
(LT1719S8)
I
CC
(LT1719S8)
I
EE
(LT1719S8)
SUPPLY VOLTAGE, V
CC
= +V
S
OR V
+
(V)
0
SUPPLY CURRENTS (mA)
2
6
5
4
3
2
1
0
–1
–2
–3
1719 G06
173456
T
A
= 25°C
V
EE
= GND
I
+
(LT1719S6)
I
S
(LT1719S8)
I
CC
(LT1719S8)
I
EE
(LT1719S8)
TEMPERATURE (°C)
–50
PROPAGATION DELAY (ns)
7.5
25
1719 G08
6.0
5.0
–25 0 50
4.5
4.0
8.0
7.0
6.5
5.5
75 100 125
OVERDRIVE = 5mV
OVERDRIVE = 20mV
3V
5V
t
PDLH
V
CM
= 1V
V
STEP
= 100mV
C
LOAD
= 10pF
V
EE
OR V
= GND
+V
S
= V
CC
= V
+
3V
5V
SUPPLY VOLTAGE, +V
S
= V
CC
OR V
+
(V)
2.5
4.0
3.5
PROPAGATION DELAY (ns)
5.5
5.0 t
TPLH
t
TPLH
t
TPHL
t
TPHL
4.5
4.0 5.0
1719 G09
3.0 3.5 4.5 5.5 6.0
25°C
V
STEP
= 100mV
OVERDRIVE = 20mV
C
LOAD
= 10pF
V
EE
/V
= GND
V
EE
= –5V
(V
CC
, +V
S
= 5.5V
MAX
)
(LT1719S8 ONLY)
OUTPUT LOAD CAPACITANCE (pF)
0
PROPAGATION DELAY (ns)
30 50
1719 G07
10 20 40
9
8
7
6
5
4
3
2
1
0
25°C
V
STEP
= 100mV
OVERDRIVE = 20mV
+V
S
= V
CC
OR V
+
= 5V
V
EE
OR V
= 0V
RISING EDGE
(t
PDLH
)
FALLING EDGE
(t
PDHL
)
Propagation Delay
vs Supply Voltage
Propagation Delay
vs Temperature
Propagation Delay
vs Load Capacitance
Quiescent Supply Current
vs Temperature
Input Current
vs Differential Input Voltage
Input Offset and Trip Voltages
vs Supply Voltage
Input Offset and Trip Voltages
vs Temperature
Input Common Mode Limits
vs Temperature
LT1719
6
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TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
0
6
8
30
NO LOAD
1719 G12
4
3
10 20 40
2
5
7
9
+V
S
SUPPLY CURRENT (mA)
25°C
+V
S
= 5V
C
LOAD
= 20pF
C
LOAD
= 10pF
OUTPUT SINK CURRENT (mA)
0
OUTPUT VOLTAGE (V)
0.3
0.4
16
1719 G10
0.2
0.1 4812 20
0.5
125°C
25°C
125°C
V
CC
= 2.7V
+V
S
OR V
+
= 5V
V
IN
= –10mV
–55°C
OUTPUT SOURCE CURRENT (mA)
0
OUTPUT VOLTAGE RELATIVE TO +V
S
(V)
–0.4
–0.2
0.0
16
1719 G11
–0.6
–0.8
–1.0 4812 20
125°C
–55°C
25°C
25°C
V
CC
= 2.7V
+V
S
OR V
+
= 5V
V
IN
= 10mV
SHDN PIN VOLTAGE (V)
V
S
–4
SHDN PIN
CURRENT (μA)
SUPPLY
CURRENTS (mA)
4
3
2
1
0
–50
–100 V
S
–3 V
S
–2 V
S
–1 V
S
1719 G13a
T
A
= 25°C
V
EE
= GND
+V
S
= V
CC
= 5V
LT1719S8
I
S
I
CC
SHDN PIN VOLTAGE (V)
V+ –4
SHDN PIN
CURRENT (μA)
SUPPLY I+
CURRENT (mA)
5
4
3
2
1
0
–50
–100 V+ –3 V+ –2 V+ –1 V+
1719 G13b
TA = 25°C
V+ = 5V
LT1719S6
Supply Current vs Frequency
Output High Voltage
vs Load Current
Output Low Voltage
vs Load Current
Shutdown Currents
vs Shutdown Voltage
Shutdown Currents
vs Shutdown Voltage
TEMPERATURE (°C)
–50
WAKE-UP DELAY (ns)
500
600
700
25 75
1719 G15
400
300
–25 0 50 100 125
200
100
Wake-Up Delay
vs Temperature
TEMPERATURE (°C)
SHUTDOWN CURRENTS (μA)
0.1
1
10
–50 25 50 75 100 125–25 0 150
1719 G14
SHUTDOWN PIN OPEN
SHUTDOWN = +V
S
– 0.5V
+I
S
+I
S
SHUTDOWN
PIN
CURRENT
V
CC
= +V
S
= 5V
V
EE
= –5V
Shutdown Currents
vs Temperature
LT1719
7
1719fa
PIN FUNCTIONS
LT1719S8
VCC (Pin 1): Positive Supply Voltage for Input Stage.
+IN (Pin 2): Noninverting Input of Comparator.
–IN (Pin 3): Inverting Input of Comparator.
VEE (Pin 4): Negative Supply Voltage for Input Stage and
Chip Substrate.
GND (Pin 5): Ground.
SHDN (Pin 6): Shutdown. Pull to ground to enable
comparator.
OUT (Pin 7): Output of Comparator.
+VS (Pin 8): Positive Supply Voltage for Output Stage.
LT1719S6
–IN (Pin 1): Inverting Input of Comparator.
V (Pin 2): Negative Supply, Usually Grounded.
+IN (Pin3): Noninverting Input of Comparator.
V+ (Pin 4): Positive Supply Voltage.
OUT (Pin 5): Output of Comparator.
SHDN (Pin 6): Shutdown. Pull to ground to enable
comparator.
LT1719
8
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TEST CIRCUITS
±V
TRIP Test Circuit
Response Time Test Circuit
+
–3V
–100mV 1
8
7
6(6)
2
3
5
4
–5V
PULSE
IN
0V
0V
50Ω
1N5711
400Ω
130Ω
25Ω
50Ω
+V
s
– V
CM
(V
+
– V
CM
)
V
CC
– V
CM
V
EE
– V
CM
–V
CM
50k
DUT
LT1719S8
25Ω
0.1μF
1719 TC02
10 × SCOPE PROBE
(C
IN
≈ 10pF)
0.01μF
0.01μF
750Ω
2N3866 V1*
*V1 = –1000 • (OVERDRIVE + V
TRIP+
)
NOTE: RISING EDGE TEST SHOWN.
FOR FALLING EDGE, REVERSE LT1719 INPUTS
LT1719
9
1719fa
APPLICATIONS INFORMATION
Figure 1. Variety of SO-8 Power Supply Confi gurations
When either input signal falls below the negative com-
mon mode limit, the internal PN diode formed with the
substrate can turn on, resulting in signifi cant current
ow through the die. An external Schottky clamp diode
between the input and the negative rail can speed up re-
covery from negative overdrive by preventing the substrate
diode from turning on.
When both input signals are below the negative common
mode limit, phase reversal protection circuitry prevents
false output inversion to at least –400mV common mode.
However, the offset and hysteresis in this mode will increase
dramatically, to as much as 15mV each. The input bias
currents will also increase.
When both input signals are above the positive common
mode limit, the input stage will get debiased and the output
polarity will be random. However, the internal hysteresis
will hold the output to a valid logic level. When at least one
of the inputs returns to within the common mode limits,
recovery from this state can take as long as 1μs.
Power Supply Confi gurations (SO-8 Package)
The LT1719S8 has separate supply pins for the input and
output stages that allow fl exible operation, accommodating
separate voltage ranges for the analog input and the output
logic. Of course, a single 3V/5V supply may be used by
tying +VS and VCC together as well as GND and VEE.
The minimum voltage requirement can be simply stated
as both the output and the input stages need at least 2.7V
and the VEE pin must be equal to or less than ground.
The following rules must be adhered to in any
confi guration:
2.7V ≤ (VCC – VEE) ≤ 10.5V
2.7V ≤ (+VS – GND) ≤ 6V
(+VS – VEE) ≤ 10.5V
V
EE ≤ Ground
Although the ground pin need not be tied to system ground,
most applications will use it that way. Figure 1 shows three
common confi gurations. The nal one is uncommon, but
it will work and may be useful as a level translator; the
input stage is run from –5.2V and ground while the output
stage is run from 3V and ground. In this case the com-
mon mode input voltage range does not include ground,
so it may be helpful to tie VCC to 3V anyway. Conversely,
VCC may also be tied below ground, as long as the above
rules are not violated.
Input Voltage Considerations
The LT1719 is specifi ed for a common mode range of
100mV to 3.8V when used with a single 5V supply. A
more general consideration is that the common mode
range is 100mV below VEE/V to 1.2V below VCC/V+. The
criterion for this common mode limit is that the output still
responds correctly to a small differential input signal. If
one input is within the common mode limit, the other
input signal can go outside the common mode limits, up
to the absolute maximum limits, and the output will retain
the correct polarity.
+
V
EE
V
CC
2.7V TO 6V
+V
S
GND
Single Supply
+
V
EE
V
CC
5V
–5V
3V
+V
S
GND
±5V
IN
, 3V
OUT
+
V
EE
V
CC
10V
5V
+V
S
GND
10V
IN
, 5V
OUT
+
V
EE
V
CC
–5.2V
3V
+V
S
GND
1719 F01
Front End Entirely Negative
LT1719S8 LT1719S8
LT1719S8
LT1719S8
LT1719
10
1719fa
APPLICATIONS INFORMATION
The propagation delay does not increase signifi cantly when
driven with large differential voltages, but with low levels
of overdrive, an apparent increase may be seen with large
source resistances due to an RC delay caused by the 2pF
typical input capacitance.
Input Protection
The input stage is protected against damage from large
differential signals, up to and beyond a differential voltage
equal to the supply voltage, limited only by the absolute
maximum currents noted. External input protection cir-
cuitry is only needed if currents would otherwise exceed
these absolute maximums. The internal catch diodes can
conduct current up to these rated maximums without
latchup, even when the supply voltage is at the absolute
maximum rating.
The LT1719 input stage has general purpose internal ESD
protection for the human body model. For use as a line
receiver, additional external protection may be required.
As with most integrated circuits, the level of immunity to
ESD is much greater when residing on a printed circuit
board where the power supply decoupling capacitance will
limit the voltage rise caused by an ESD pulse.
Input Bias Current
Input bias current is measured with both inputs held at
1V. As with any PNP differential input stage, the LT1719
bias current fl ows out of the device. It will go to zero
on the higher of the two inputs and double on the lower
of the two inputs. With more than two diode drops of
differential input voltage, the LT1719’s input protection
circuitry activates, and current out of the lower input will
increase an additional 30% and there will be a small bias
current into the higher of the two input pins, of 4μA or
less. See the Typical Performance curve Input Current vs
Differential Input Voltage.
High Speed Design Considerations
Application of high speed comparators is often plagued by
oscillations. The LT1719 has 4mV of internal hysteresis,
which will prevent oscillations as long as parasitic output
to input feedback is kept below 4mV. However, with the
2V/ns slew rate of the LT1719 outputs, a 4mV step can
be created at a 100Ω input source with only 0.02pF of
output to input coupling. The LT1719’s pinout has been
arranged to minimize problems by placing the sensitive
inputs away from the outputs, shielded by the power rails.
The input and output traces of the circuit board should
also be separated, and the requisite level of isolation is
readily achieved if a topside ground plane runs between
the output and the inputs. For multilayer boards where the
ground plane is internal, a topside ground or supply trace
should be run between the inputs and the output.
Figure 2 shows a typical topside layout of the LT1719S8
on such a multilayer board. Shown is the topside metal
etch including traces, pin escape vias, and the land pads
for an SO-8 LT1719 and its adjacent X7R 10nF bypass
capacitors in the 1206 case. The same principles should
be used with the SOT 23-6.
1719 F02
Figure 2. Typical Topside Metal for Multilayer PCB Layouts
The ground trace from Pin 5 runs under the device up
to the bypass capacitor, shielding the inputs from the
outputs. Note the use of a common via for the LT1719
and the bypass capacitors, which minimizes interference
from high frequency energy running around the ground
plane or power distribution traces.
The supply bypass should include an adjacent
10nF ceramic capacitor and a 2.2μF tantalum capacitor
no farther than 5cm away; use more capacitance on +VS
if driving more than 4mA loads. To prevent oscillations,
it is helpful to balance the impedance at the inverting and
noninverting inputs; source impedances should be kept
low, preferably 1kΩ or less.
LT1719
11
1719fa
APPLICATIONS INFORMATION
The outputs of the LT1719 are capable of very high slew
rates. To prevent overshoot, ringing and other problems
with transmission line effects, keep the output traces
shorter than 10cm, or be sure to terminate the lines
to maintain signal integrity. The LT1719 can drive DC
terminations of 200Ω or more, but lower characteristic
impedance traces can be used with series termination or
AC termination topologies.
Shutdown Control
The LT1719 features a shutdown control pin for reduced
quiescent current when the comparator is not needed.
During shutdown, the inputs and the outputs become high
impedances. The LT1719 is enabled when the shutdown
input is pulled low with a threshold roughly two diode drops
below +VS or V+. Therefore, if driven by a standard TTL
gate, a pull-up resistor should be used. Because shutdown
is active high, this resistor adds little power drain during
shutdown. A logic high disables the comparator. The
LT1719S8 logic interface is based on the output power
rails, +VS and GND.
For applications that do not use the shutdown feature,
it may be helpful to tie the shutdown control to ground
through a 100Ω resistor rather than directly. This allows
the SHDN pin to be pulled high during debug or in-circuit
test (bed of nails) so that the output node can be wiggled
without damaging the low impedance output driver of
the LT1719.
The shutdown state is not guaranteed to be useful as a
multiplexer. Digital signals can have extremely fast edge
rates that may be enough to momentarily activate the
LT1719 output stage via internal capacitive coupling. No
damage to the LT1719 will result, but this could prove
deleterious to the intended recipient of the signal.
The LT1719 includes a FET pull-up on the shutdown control
pin (see the Simplifi ed Schematic) as well as other inter-
nal structures to make the shutdown state current drain
<<1μA. Shutdown is guaranteed with an open circuit on the
shutdown control pin. When the shutdown control pin is
driven to +VS/V+ – 0.5V, the 70kΩ linear region impedance
of the pull-up FET will cause a current fl ow of 7μA (typ)
into the +VS/V+ pin and out the shutdown pin. Currents in
all other power supply terminals will be <1μA.
Power Supply Sequencing
The LT1719S8 is designed to tolerate any power supply
sequencing at system turn-on and power down. In any
of the previously shown power supply confi gurations, the
various supplies can activate in any order without exces-
sive current drain by the LT1719.
As always, the Absolute Maximum Ratings must not be
exceeded, either on the power supply terminals or the input
terminals. Power supply sequencing problems can occur
when input signals are powered from supplies that are
independent of the LT1719’s supplies. For the compara-
tor inputs, the signals should be powered from the same
VCC and VEE supplies as the LT1719. For the shutdown
input, the signal should be powered from the same +VS
as the LT1719.
Hysteresis
The LT1719 includes internal hysteresis, which makes it
easier to use than many other similar speed comparators.
The input-output transfer characteristic is illustrated in
Figure 3 showing the defi nitions of VOS and VHYST based
upon the two measurable trip points. The hysteresis band
makes the LT1719 well behaved, even with slowly moving
inputs.
Figure 3. Hysteresis I/O Characteristics
V
HYST
(= V
TRIP+
– V
TRIP
)
V
HYST
/2
V
OL
1719 F03
V
OH
V
TRIP
V
TRIP+
ΔV
IN
= V
IN+
– V
IN
V
TRIP+
+ V
TRIP
2
V
OS
=
V
OUT
0
LT1719
12
1719fa
on the common mode and power supply dependence of
the hysteresis voltage.
Additional hysteresis may be added externally. The rail-
to-rail outputs of the LT1719 make this more predictable
than with TTL output comparators due to the LT1719’s
small variability of VOH (output high voltage).
To add additional hysteresis, set up positive feedback
by adding additional external resistor R3 as shown in
Figure 4. Resistor R3 adds a portion of the output to the
threshold set by the resistor string. The LT1719 pulls the
outputs to +VS and ground to within 200mV of the rails
with light loads, and to within 400mV with heavy loads.
For the load of most circuits, a good model for the voltage
on the right side of R3 is 300mV or +VS – 300mV, for a
total voltage swing of (+VS – 300mV) – (300mV) = +VS
– 600mV.
The exact amount of hysteresis will vary from part to part
as indicated in the specifi cations table. The hysteresis level
will also vary slightly with changes in supply voltage and
common mode voltage. A key advantage of the LT1719
is the signifi cant reduction in these effects, which is im-
portant whenever an LT1719 is used to detect a threshold
crossing in one direction only. In such a case, the relevant
trip point will be all that matters, and a stable offset volt-
age with an unpredictable level of hysteresis, as seen in
competing comparators, is useless. The LT1719 is many
times better than prior comparators in these regards. In
fact, the CMRR and PSRR tests are performed by check-
ing for changes in either trip point to the limits indicated
in the specifi cations table. Because the offset voltage is
the average of the trip points, the CMRR and PSRR of the
offset voltage is therefore guaranteed to be at least as good
as those limits. This more stringent test also puts a limit
+
LT1719S8
INPUT
1719 F04
R2
VREF R3
R1
Figure 4. Additional External Hysteresis
APPLICATIONS INFORMATION
LT1719
13
1719fa
+
LT1719S8
1719 F05
R2ʹ
VREF
VTH R3 +VS
2
VAVERAGE =
R1
Figure 5. Model for Additional Hysteresis Calculations
With this in mind, calculation of the resistor values needed
is a two-step process. First, calculate the value of R3 based
on the additional hysteresis desired, the output voltage
swing and the impedance of the primary bias string:
R3 = (R1⏐⏐ R2)(+VS – 0.6V)/(additional hysteresis)
Additional hysteresis is the desired overall hysteresis less
the internal 4mV hysteresis.
The second step is to recalculate R2 to set the same av-
erage threshold as before. The average threshold before
was set at VTH = (VREF)(R1)/(R1 + R2). The new R2 is
calculated based on the average output voltage (+VS/2)
and the simplifi ed circuit model in Figure 5. To assure
that the comparators noninverting input is, on average,
the same VTH as before:
R2ʹ = (VREF – VTH)/(VTH/R1 + [VTH – (+VS)/2]/R3)
For additional hysteresis of 10mV or less, it is not un-
common for R2ʹ to be the same as R2 within 1% resistor
tolerances.
This method will work for additional hysteresis of up to a
few hundred millivolts. Beyond that, the impedance of R3 is
low enough to effect the bias string, and adjustment of R1
may also be required. Note that the currents through the
R1/R2 bias string should be many times the input currents
of the LT1719. For 5% accuracy, the current must be at
least 20 times the input current, more for higher accuracy.
This illustration used an LT1719S8; with an LT1719S6 the
same procedure is used with V+ substituted for +VS.
APPLICATIONS INFORMATION
LT1719
14
1719fa
Figure 6a shows the standard TTL to Positive ECL (PECL)
resistive level translator. This translator cannot be used
for the LT1719, or with CMOS logic, because it depends
on the 820Ω resistor to limit the output swing (VOH) of
the all-NPN TTL gate with its so-called totem-pole output.
The LT1719 is fabricated in a complementary bipolar
process and the output stage has a PNP driver that pulls
the output nearly all the way to the supply rail, even when
sourcing 10mA.
Interfacing the LT1719 to ECL
The LT1719 comparators can be used in high speed ap-
plications where emitter-coupled logic (ECL) is deployed.
To interface the output of the LT1719 to ECL logic inputs,
standard TTL/CMOS to ECL level translators such as the
10H124, 10H424 and 100124 can be used. These com-
ponents come at a cost of a few nanoseconds additional
delay as well as supply currents of 50mA or more, and
are only available in quads. A faster, simpler and lower
power translator can be constructed with resistors as
shown in Figure 6.
APPLICATIONS INFORMATION
Figure 6
5V
5V
180Ω
DO NOT USE FOR LT1719
LEVEL TRANSLATION. SEE TEXT
270Ω
820Ω
10KH/E
R2
+VS or V+
R3
R1
10KH/E
100K/E
+VS OR V+
5V OR 5.2V
4.5V
R1
510Ω
620Ω
R2
180Ω
180Ω
R3
750Ω
510Ω
(a) STANDARD TTL TO PECL TRANSLATOR
(b) LT1719 OUTPUT TO PECL TRANSLATOR
LSTTL
LT1719
R2
VECL
3V
R3R4
R1
10KH/E
100K/E
VECL
5V OR 5.2V
4.5V
R1
300Ω
330Ω
R2
180Ω
180Ω
R3
OMIT
1500Ω
(c) 3V LT1719 OUTPUT TO PECL TRANSLATOR
LT1719 R4
560Ω
1000Ω
R4
VECL
+VS or V+
R3
1719 F06
R2
R1 ECL FAMILY
10KH/E
VECL
–5.2V
R1
560Ω
270Ω
+VS OR V+
5V
3V
R2
270Ω
510Ω
R3
330Ω
300Ω
(d) LT1719 OUTPUT TO STANDARD ECL TRANSLATOR
LT1719
R4
1200Ω
330Ω
100K/E –4.5V 680Ω
330Ω
5V
3V
270Ω
390Ω
300Ω
270Ω
1500Ω
430Ω
LT1719
15
1719fa
Figure 6b shows a three resistor level translator for inter-
facing the LT1719 to ECL running off the same supply rail.
No pull-down on the output of the LT1719 is needed, but
pull-down R3 limits the VIH seen by the PECL gate. This
is needed because ECL inputs have both a minimum and
maximum VIH specifi cation for proper operation. Resis-
tor values are given for both ECL interface types; in both
cases it is assumed that the LT1719 operates from the
same supply rail.
Figure 6c shows the case of translating to PECL from
an LT1719 powered by a 3V supply rail. Again, resistor
values are given for both ECL interface types. This time
four resistors are needed, although with 10KH/E, R3 is not
needed. In that case, the circuit resembles the standard
TTL translator of Figure 6a, but the function of the new
resistor, R4, is much different. R4 loads the LT1719 output
when high so that the current fl owing through R1 doesn’t
forward bias the LT1719’s internal ESD clamp diode.
Although this diode can handle 20mA without damage,
normal operation and performance of the output stage can
be impaired above 100μA of forward current. R4 prevents
this with the minimum additional power dissipation.
Finally, Figure 6d shows the case of driving standard,
negative-rail, ECL with the LT1719. Resistor values are
given for both ECL interface types and for both a 5V
and 3V LT1719 supply rail. Again, a fourth resistor, R4
is needed to prevent the low state current from fl owing
out of the LT1719, turning on the internal ESD/substrate
diodes. Resistor R4 again prevents this with the minimum
additional power dissipation.
Of course, in the SO-8 package, if the VEE of the LT1719
is the same as the ECL negative supply, the GND pin can
be tied to it as well and +VS grounded. Then the output
stage has the same power rails as the ECL and the circuits
of Figure 6b can be used.
For all the dividers shown, the output impedance is about
110Ω. This makes these fast, less than a nanosecond,
with most layouts. Avoid the temptation to use speedup
capacitors. Not only can they foul up the operation of the
ECL gate because of overshoots, they can damage the ECL
inputs, particularly during power-up of separate supply
confi gurations.
Similar circuits can be used with the emerging LVECL and
LVPECL standards.
The level translator designs shown assume one gate
load. Multiple gates can have signifi cant IIH loading, and
the transmission line routing and termination issues also
make this case diffi cult.
ECL, and particularly PECL, is valuable technology for high
speed system design, but it must be used with care. With
less than a volt of swing, the noise margins need to be
evaluated carefully. Note that there is some degradation of
noise margin due to the ±5% resistor selections shown.
With 10KH/E, there is no temperature compensation of
the logic levels, whereas the LT1719 and the circuits
shown give levels that are stable with temperature. This
will lower the noise margin over temperature. In some
confi gurations it is possible to add compensation with
diode or transistor junctions in series with the resistors
of these networks.
For more information on ECL design, refer to the ECLiPS
data book (DL140), the 10KH system design handbook
(HB205) and PECL design (AN1406), all from Motorola,
now ON Semiconductor.
APPLICATIONS INFORMATION
LT1719
16
1719fa
Circuit Description
The block diagram of the LT1719 is shown in Figure 7.
The circuit topology consists of a differential input stage,
a gain stage with hysteresis and a complementary com-
mon-emitter output stage. All of the internal signal paths
utilize low voltage swings for high speed at low power.
The input stage topology maximizes the input dynamic
range available without requiring the power, complexity
and die area of two complete input stages such as are
found in rail-to-rail input comparators. With a single
2.7V supply, the LT1719 still has a respectable 1.6V of
input common mode range. The differential input volt-
age range is rail-to-rail, without the large input currents
found in competing devices. The input stage also features
phase reversal protection to prevent false outputs when
the inputs are driven below the –100mV common mode
voltage limit.
The internal hysteresis is imp lemented by positive, nonlin-
ear feedback around a second gain stage. Until this point,
the signal path has been entirely differential. The signal
path is then split into two drive signals for the upper and
lower output transistors. The output transistors are con-
nected common emitter for rail-to-rail output operation.
The Schottky clamps limit the output voltages at about
300mV from the rail, not quite the 50mV or 15mV of Linear
Technologys rail-to-rail amplifiers and other products. But
the output of a comparator is digital, and this output stage
can drive TTL or CMOS directly. It can also drive ECL, as
described earlier, or analog loads as demonstrated in the
applications to follow.
The bias conditions and signal swings in the output stage
are designed to turn their respective output transistors off
faster than on. This helps minimize the surge of current from
+VS/V+ to ground that occurs at transitions, to minimize
the frequency-dependent increase in power consumption.
The frequency dependence of the supply current is shown
in the Typical Performance Characteristics.
Speed Limits
The LT1719 comparator is intended for high speed ap-
plications, where it is important to understand a few
limitations. These limitations can roughly be divided into
APPLICATIONS INFORMATION
OUT
GND OR V
+V
S
OR V
+
+
+
+
+
+IN
–IN
A
V1
V
CC
OR V
+
V
EE
OR V
SHUTDOWN
A
V2
NONLINEAR STAGE
1719 F07
+
+
BIAS CONTOL
Figure 7. LT1719 Block Diagram
LT1719
17
1719fa
three categories: input speed limits, output speed limits,
and internal speed limits.
There are no significant input speed limits except the shunt
capacitance of the input nodes. If the 2pF typical input
nodes are driven, the LT1719 will respond.
The output speed is constrained by two mechanisms, the
rst of which is the slew currents available from the output
transistors. To maintain low power quiescent operation,
the LT1719 output transistors are sized to deliver 25mA
to 45mA typical slew currents. This is sufficient to drive
small capacitive loads and logic gate inputs at extremely
high speeds. But the slew rate will slow dramatically with
heavy capacitive loads. Because the propagation delay (tPD)
definition ends at the time the output voltage is halfway
between the supplies, the fixed slew current makes the
LT1719 faster at 3V than 5V with large capacitive loads
and suffi cient input overdrive.
Another manifestation of this output speed limit is skew,
the difference between tPD+ and tPD. The slew currents
of the LT1719 vary with the process variations of the
PNP and NPN transistors, for rising edges and falling
edges respectively. The typical 0.5ns skew can have either
polarity, rising edge or falling edge faster. Again, the skew
will increase dramatically with heavy capacitive loads.
A separate output speed limit is the clamp turnaround.
The LT1719 output is optimized for fast initial response,
with some loss of turnaround speed, limiting the toggle
frequency. The output transistors are idled in a low power
state once VOH or VOL is reached, by detecting the Schottky
clamp action. It is only when the output has slewed from
the old voltage to the new voltage, and the clamp circuitry
has settled, that the idle state is reached and the LT1719
is fully ready to toggle again. This is typically 8ns for each
direction, resulting in a maximum toggle frequency of
62.5MHz. With higher frequencies, dropout and runt pulses
can result. Increases in capacitive load will increase the time
needed for slewing due to the limited slew currents and
the maximum toggle frequency will decrease further. For
high toggle frequency applications, consider the LT1394,
whose linear output stage can toggle at 100MHz typical.
The internal speed limits manifest themselves as disper-
sion. All comparators have some degree of dispersion,
defined as a change in propagation delay versus input
overdrive. The propagation delay of the LT1719 will vary
with overdrive, from a typical of 4.5ns at 20mV overdrive
to 7ns at 5mV overdrive (typical). The LT1719’s primary
source of dispersion is the hysteresis stage. As a change
of polarity arrives at the gain stage, the positive feedback
of the hysteresis stage subtracts from the overdrive avail-
able. Only when enough time has elapsed for a signal to
propagate forward through the gain stage, backwards
through the hysteresis path and forward through the gain
stage again, will the output stage receive the same level
of overdrive that it would have received in the absence
of hysteresis.
The LT1719S8 is several hundred picoseconds faster when
VEE = –5V, relative to single supply operation. This is due
to the internal speed limit; the gain stage operates between
VEE and +VS, and it is faster with higher reverse voltage
bias due to reduced silicon junction capacitances.
In many applications, as shown in the following examples,
there is plenty of input overdrive. Even in applications pro-
viding low levels of overdrive, the LT1719 is fast enough
that the absolute dispersion of 2.5ns (= 7 – 4.5) is often
small enough to ignore.
The gain and hysteresis stage of the LT1719 is simple, short
and high speed to help prevent parasitic oscillations while
adding minimum dispersion. This internal “self-latch” can
be usefully exploited in many applications
because it occurs
early in the signal chain, in a low power, fully differential
stage. It is therefore highly immune to disturbances from
other parts of the circuit, such as the output, or on the
supply lines. Once a high speed signal trips the hysteresis,
the output will respond, after a fixed propagation delay,
without regard to these external influences that can cause
trouble in nonhysteretic comparators.
APPLICATIONS INFORMATION
LT1719
18
1719fa
+
+
C1
LT1719
A1
LT1636
V
CC
2.7V TO 6V
2k
620Ω
220Ω
1MHz TO 10MHz
CRYSTAL (AT-CUT)
100k
200k
200k
1720 F07
1.8k
2k
1k
0.1μF
0.1μF
0.1μF
OUTPUT
V
CC
GROUND
CASE
Figure 8. Crystal Oscillator with a Forced 50% Duty Cycle
APPLICATIONS INFORMATION
±VTRIP Test Circuit
The input trip points test circuit uses a 1kHz triangle wave
to repeatedly trip the comparator being tested. The LT1719
output is used to trigger switched capacitor sampling of the
triangle wave, with a sampler for each direction. Because the
triangle wave is attenuated 1000:1 and fed to the LT1719’s
differential input, the sampled voltages are therefore 1000
times the input trip voltages. The hysteresis and offset are
computed from the trip points as shown.
Crystal Oscillator
A simple crystal oscillator using an LT1719 is shown on
the fi rst page of this data sheet. The 2k-620Ω resistor pair
set a bias point at the comparators noninverting input.
The 2k-1.8k-0.1μF path sets the inverting input node at
an appropriate DC average level based on the output.
The crystal’s path provides resonant positive feedback
and stable oscillation occurs. Although the LT1719 will
give the correct logic output when one input is outside
the common mode range, additional delays may occur
when it is so operated, opening the possibility of spurious
operating modes. Therefore, the DC bias voltages at the
inputs are set near the center of the LT1719’s common
mode range and the 220Ω resistor attenuates the feedback
to the noninverting input. The circuit will operate with any
AT-cut crystal from 1MHz to 10MHz over a 2.7V to 6V sup-
ply range. As the power is applied, the circuit remains off
until the LT1719 bias circuits activate, at a typical VCC of
2V to 2.2V (25°C), at which point the desired frequency
output is generated.
The output duty cycle of this circuit is roughly 50%, but
it is affected by resistor tolerances and to a lesser extent,
by comparator offsets and timings. If a 50% duty cycle is
required, the circuit of Figure 8 forces a 50% duty cycle.
Crystals are narrow-band elements, so the feedback to
the noninverting input is a fi ltered analog version of the
square wave output. Changing the noninverting reference
level can therefore vary the duty cycle. C1 operates as in
the previous example while A1 compares a band-limited
version of the output and biases C1’s negative input. C1’s
only degree of freedom to respond is variation of pulse
width; hence the output is forced to 50% duty cycle.
Again, the circuit operates from 2.7V to 6V. There is a
slight duty cycle dependence on comparator loading, so
minimal capacitive and resistive loading should be used
in critical applications.
LT1719
19
1719fa
–IN
+IN
V
EE
(V
)
1719 SS
OUTPUT
GND (V
)
+V
S
(V
+
)
V
CC
(V
+
)
150Ω
150Ω
TO BIAS
SOURCES
15k
SHDN
SIMPLIFIED SCHEMATIC
LT1719
20
1719fa
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°8° TYP
.008 – .010
(0.203 0.254)
SO8 0303
.053 – .069
(1.346 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
PACKAGE DESCRIPTION
LT1719
21
1719fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302 REV B
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
PACKAGE DESCRIPTION
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
LT1719
22
1719fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2000
LT 0809 REV A • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT1016 UltraFast Precision Comparator Industry Standard 10ns Comparator
LT1116 12ns Single Supply Ground-Sensing Comparator Single Supply Version of LT1016
LT1394 7ns, UltraFast, Single Supply Comparator 6mA Single Supply Comparator
LT1671 60ns, Low Power, Single Supply Comparator 450μA Single Supply Comparator
LT1713/LT1714 Single/Dual 7ns, Rail-to-Rail Comparator Rail-to-Rail Inputs and Outputs
LT1720/LT1721 Dual/Quad 4.5ns, Single Supply 3V/5V Comparator Dual/Quad Comparator Similar to the LT1719
High Performance Sine Wave
to Square Wave Converter
Propagation delay of comparators is typically specifi ed for
a 100mV step with some fraction of that for overdrive. But
in many signal processing applications, such as in com-
munications, the goal is to convert a sine wave, such as
a carrier, to a square wave for use as a timing clock. The
desired behavior is for the output timing to be dependent
on the input timing only. No phase shift should occur as
a function of the input amplitude, which would result in
AM to FM conversion.
The circuit of Figure 9a is a simple LT1719S8-based sine
wave to square wave converter. The ± 5V supplies on the
input allow very large swing inputs, while the 3V logic
supply keeps the output swing small to minimize cross
talk. Figure 9b shows the time delay vs input amplitude
with a 10MHz sine wave. The LT1719 delay changes just
0.65ns over the 26dB amplitude range; 2.33° at 10MHz.
The delay is particularly fl at yielding excellent AM rejection
Figure 9a. LT1719-Based Sine Wave to Square Wave Converter
from 0dBm to 15dBm. If a 2:1 transformer is used to drive
the input differentially, this exceptionally fl at zone spans
–5dBm to 10dBm, a common range for RF signal levels.
Similar delay performance is achieved with input frequen-
cies as high as 50MHz. There is, however, some additional
encroachment into the central fl at zone by both the small
amplitude and large amplitude variations.
With small input signals, the hysteresis and dispersion
make the LT1719 act like a comparator with a 12mV
hysteresis span. In other words, a 12mVP-P sine wave at
10MHz will barely toggle the LT1719, with 90° of phase
lag or 25ns additional delay.
Above 5VP-P at 10MHz, the LT1719 delay starts to decrease
due to internal capacitive feed-forward in the input stage.
Unlike some comparators, the LT1719 will not falsely an-
ticipate a change in input polarity, but the feed-forward is
enough to make a transition propagate through the LT1719
faster once the input polarity does change.
+
LT1719S8
50Ω
1719 F09a
SINE WAVE
INPUT SQUARE WAVE
OUTPUT
5V
–5V
3V
INPUT AMPLITUDE (dBm)
–5
0
TIME DELAY (ns)
1
2
3
4
5
051015
1719 F09b
20 25
632mV
P-P
2V
P-P
6.32V
P-P
25°C
V
CC
= 5V
V
EE
= –5V
+V
S
= 3V
10MHz
Figure 9b. Time Delay vs Sine Wave Input Amplitude

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