JPY | USD

IS25LP064A Datasheet

ISSI, Integrated Silicon Solution Inc

Download PDF Datasheet

Datasheet

IS25LP064A
64Mb
3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD
I/O QPI DTR INTERFACE
DATA SHEET
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 2
Rev. A12
04/15/2019
FEATURES
Industry Standard Serial Interface
- IS25LP064A: 64Mbit/8Mbyte
- 256 bytes per Programmable Page
- Supports standard SPI, Fast, Dual, Dual
I/O, Quad, Quad I/O, SPI DTR, Dual I/O
DTR, Quad I/O DTR, and QPI
- Supports Double Transfer Rate (DTR)
- Supports Serial Flash Discoverable
Parameters (SFDP)(4)
High Performance Serial Flash (SPI)
- 133Mhz Fast Read at Vcc=2.7V to 3.6V
- 104Mhz Fast Read at Vcc=2.3V to 3.6V
- 532MHz equivalent at QPI operation
- 50MHz Normal Read
- DTR (Dual Transfer Rate) up to 66MHz
- Selectable dummy cycles
- Configurable drive strength
- Supports SPI Modes 0 and 3
- More than 100,000 erase/program cycles
- More than 20-year data retention
Flexible & Efficient Memory Architecture
- Chip Erase with Uniform Sector/Block
Erase (4/32/64 Kbyte)
- Program 1 to 256 bytes per page
- Program/Erase Suspend & Resume
Efficient Read and Program modes
- Low Instruction Overhead Operations
- Continuous Read 8/16/32/64-Byte burst
Wrap
- Selectable burst length
- QPI for reduced instruction overhead
Low Power with Wide Temp. Ranges
- Single 2.3V to 3.6V Voltage Supply
- 5 mA Active Read Current (typ.)
- 10 µA Standby Current (typ.)
- 5 µA Deep Power Down (typ.)
- Temp Grades:
Extended: -40°C to +105°C
Auto Grade (A3): -40°C to +125°C
Advanced Security Protection
- Software and Hardware Write Protection
- Power Supply lock protect
- 4x256-Byte dedicated security area
with OTP user-lockable bits
- 128 bit Unique ID for each device (Call
Factory)
Industry Standard Pin-out & Packages(1),(2)
- B = 8-pin SOIC 208mil
- T = 8-contact USON 4x3mm
- E = 8-contact XSON 4x4mm
- K = 8-contact WSON 6x5mm
- L = 8-contact WSON 8x6mm
- M = 16-pin SOIC 300mil(3)
- G= 24-ball TFBGA 6x8mm 4x6(3)
- H = 24-ball TFBGA 6x8mm 5x5 (Call
Factory)(3)
- KGD (Call Factory)
Notes:
1. Call Factory for other package options available.
2. For the RESET# pin option instead of HOLD# pin, call
Factory.
3. For the dedicated RESET# option, see the Ordering
Information
64Mb
3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 3
Rev. A12
04/15/2019
GENERAL DESCRIPTION
The IS25LP064A Serial Flash memory offers a versatile storage solution with high flexibility and performance in
a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash are for systems that require
limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire SPI Interface
consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins,
which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock
frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to
66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate)
commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform
16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in place) operation.
Initial state of the memory array is erased (all bits are set to 1) when shipped from the factory.
QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be
erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector
and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety
of applications requiring solid data retention.
GLOSSARY
Standard SPI
In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),
Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,
addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check the
status of the device. This device supports SPI bus operation modes (0,0) and (1,1).
Multi I/O SPI
Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input
and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode
will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.
QPI
The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from
Standard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol
requires that the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The
QPI mode utilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can
significantly reduce the SPI instruction overhead and improve system performance. Only QPI mode or
SPI/Dual/Quad mode can be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used
to switch between these two modes, regardless of the non-volatile Quad Enable (QE) bit status in the Status
Register. Power Reset or Hardware/Software Reset will return the device into the standard SPI mode. SI and SO
pins become bidirectional I/O0 and I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively during
QPI mode.
DTR
In addition to SPI and QPI features, the device also supports Fast READ DTR operation, which allows high data
throughput while running at lower clock frequencies. DTR READ mode uses both rising and falling edges of the
clock to drive output, resulting in reducing input and output cycles by half.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 4
Rev. A12
04/15/2019
TABLE OF CONTENTS
FEATURES .......................................................................................................................................................... 2
GENERAL DESCRIPTION .................................................................................................................................. 3
TABLE OF CONTENTS ....................................................................................................................................... 4
1. PIN CONFIGURATION ................................................................................................................................. 7
2. PIN DESCRIPTIONS .................................................................................................................................... 9
3. BLOCK DIAGRAM ...................................................................................................................................... 11
4. SPI MODES DESCRIPTION ...................................................................................................................... 12
5. SYSTEM CONFIGURATION ...................................................................................................................... 14
5.1 BLOCK/SECTOR ADDRESSES .......................................................................................................... 14
6. REGISTERS ............................................................................................................................................... 15
6.1 STATUS REGISTER ............................................................................................................................ 15
6.2 FUNCTION REGISTER ........................................................................................................................ 18
6.3 READ REGISTER................................................................................................................................. 19
7. PROTECTION MODE................................................................................................................................. 21
7.1 HARDWARE WRITE PROTECTION.................................................................................................... 21
7.2 SOFTWARE WRITE PROTECTION .................................................................................................... 21
8. DEVICE OPERATION ................................................................................................................................ 22
8.1 NORMAL READ OPERATION (NORD, 03h) ....................................................................................... 25
8.2 FAST READ OPERATION (FRD, 0Bh) ................................................................................................ 27
8.3 HOLD OPERATION .............................................................................................................................. 29
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ........................................................................... 29
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh) ................................................................... 32
8.6 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh).................................................................. 33
8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh) .......................................................................... 35
8.8 PAGE PROGRAM OPERATION (PP, 02h) .......................................................................................... 39
8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h) ........................................................ 41
8.10 ERASE OPERATION ......................................................................................................................... 42
8.11 SECTOR ERASE OPERATION (SER, D7h/20h) ............................................................................... 43
8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................ 44
8.13 CHIP ERASE OPERATION (CER, C7h/60h) ..................................................................................... 46
8.14 WRITE ENABLE OPERATION (WREN, 06h) .................................................................................... 47
8.15 WRITE DISABLE OPERATION (WRDI, 04h) ..................................................................................... 48
8.16 READ STATUS REGISTER OPERATION (RDSR, 05h) ................................................................... 49
8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h) ................................................................. 50
8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h) ............................................................... 51
8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)............................................................. 52
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 5
Rev. A12
04/15/2019
8.20 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN, 35h; QPIDI, F5h) 53
8.21 PROGRAM/ERASE SUSPEND & RESUME ...................................................................................... 54
8.22 ENTER DEEP POWER DOWN (DP, B9h) ......................................................................................... 56
8.23 RELEASE DEEP POWER DOWN (RDPD, ABh) ............................................................................... 57
8.24 SET READ PARAMETERS OPERATION (SRP, C0h) ...................................................................... 58
8.25 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................ 60
8.26 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh) 62
8.27 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) ........................ 63
8.28 READ UNIQUE ID NUMBER (RDUID, 4Bh) ...................................................................................... 64
8.29 READ SFDP OPERATION (RDSFDP, 5Ah) ...................................................................................... 65
8.30 NO OPERATION (NOP, 00h) ............................................................................................................. 65
8.31 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE
RESET ........................................................................................................................................................ 66
8.32 SECURITY INFORMATION ROW ...................................................................................................... 67
8.33 INFORMATION ROW ERASE OPERATION (IRER, 64h) ................................................................. 68
8.34 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) ............................................................. 69
8.35 INFORMATION ROW READ OPERATION (IRRD, 68h) ................................................................... 70
8.36 FAST READ DTR MODE OPERATION (FRDTR, 0Dh) ..................................................................... 71
8.37 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh) .................................................. 73
8.38 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh) ................................................. 76
8.39 SECTOR LOCK/UNLOCK FUNCTIONS ............................................................................................ 80
9. ELECTRICAL CHARACTERISTICS ........................................................................................................... 82
9.1 ABSOLUTE MAXIMUM RATINGS (1) ................................................................................................... 82
9.2 OPERATING RANGE ........................................................................................................................... 82
9.3 DC CHARACTERISTICS ...................................................................................................................... 83
9.4 AC MEASUREMENT CONDITIONS .................................................................................................... 84
9.5 PIN CAPACITANCE ............................................................................................................................. 84
9.6 AC CHARACTERISTICS ...................................................................................................................... 85
9.7 SERIAL INPUT/OUTPUT TIMING ........................................................................................................ 87
9.8 POWER-UP AND POWER-DOWN ...................................................................................................... 89
9.9 PROGRAM/ERASE PERFORMANCE ................................................................................................. 90
9.10 RELIABILITY CHARACTERISTICS ................................................................................................... 90
10. PACKAGE TYPE INFORMATION ......................................................................................................... 91
10.1 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (B) ............................ 91
10.2 8-Contact Ultra-Thin Small Outline No-Lead (USON) Package 4x3mm (T) ....................................... 92
10.3 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 6x5mm (K)...................................... 93
10.4 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 8x6mm (L) ...................................... 94
10.5 16-lead Plastic Small Outline package (300 mils body width) (M) ..................................................... 95
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 6
Rev. A12
04/15/2019
10.6 24-Ball Thin Profile Fine Pitch BGA 6x8mm 4x6 BALL ARRAY (G) .................................................. 96
10.7 24-Ball Thin Profile Fine Pitch BGA 6x8mm 5x5 BALL ARRAY (H) ................................................... 97
10.8 8-Contact Extremely-Thin Small Outline No-Lead (XSON) Package 4x4mm (E) .............................. 98
11. ORDERING INFORMATION- Valid Part Numbers ................................................................................ 99
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 7
Rev. A12
04/15/2019
1. PIN CONFIGURATION
6
3
CE#
Vcc
SI (IO0)
7
8
5
4
1
2
GND
WP# (IO2)
SO (IO1)
HOLD# (IO3)
8-pin SOIC 208mil
8-contact WSON 6x5mm
8-contact WSON 8x6mm
8-contact XSON 4x4mm
8-contact USON 4x3mm
HOLD# (IO3)
Vcc
CE#
GND
1
2
3
4
7
6
5
SO (IO1)
SI (IO0)
8
WP# (IO2)
(1)
(1)
16-pin SOIC 300mil
(2)
(1)
12
10
11
9
13
15
14
5
7
6
8
4
2
3
16
1
Vcc
HOLD# (IO3)
CE#
WP# (IO2)
GND
NC
NC
NC
NC
NC
SI (IO0)
SO (IO1)
NC
NC
RESET#/NC
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 8
Rev. A12
04/15/2019
Top View, Balls Facing Down
NC NC NC NC
F1 F2 F3 F4
NC NC or RESET#
NC SCK GND VCC
NC CE#NC WP#(IO2)
NC SO(IO1) SI(IO0) HOLD# or
RESET# (IO3)
NC NC NC NC
NC
A2 A3 A4
B1 B2 B3 B4
C1 C2 C3 C4
D1 D2 D3 D4
E1 E2 E3 E4
A1 (2)
(1)
24-ball TFBGA, 4x6 Ball Array (Package:G)
NC NC
NC SCK GND VCC
NC CE#NC WP#(IO2)
NC SO(IO1) SI(IO0) HOLD# or
RESET# (IO3)
NC NC NC NC
NC
NC
NC
NC
Top View, Balls Facing Down
NC
24-ball TFBGA, 5x5 Ball Array (Package:H)
A2 A3 A4
B1 B2 B3 B4
C1 C2 C3 C4
D1 D2 D3 D4
E1 E2 E3 E4
A5
B5
C5
D5
E5
NC
(2)
(1)
NC
NC or RESET#
Notes:
1. For RESET# (IO3) pin (or ball) option instead of HOLD# (IO3) pin (or ball), call Factory.
2. In case of 16-pin SOIC and 24-ball TFBGA packages, pin3/ball A4 will become NC or RESET# based on part
number. Below is the summary. Also see the Ordering Information.
Standard(1)
Dedicated RESET#(2)
Pin3 or Ball A4
NC
RESET#
Pin1or Ball D4
Hold#(IO3) or RESET#(IO3)
Hold#(IO3)
Part Number Option
J or S
R or P
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 9
Rev. A12
04/15/2019
2. PIN DESCRIPTIONS
For the device without dedicated RESET#
SYMBOL
TYPE
DESCRIPTION
CE#
INPUT
Chip Enable: The Chip Enable (CE#) pin enables and disables the devices
operation. When CE# is high the device is deselected and output pins are in a high
impedance state. When deselected the devices non-critical internal circuitry power
down to allow minimal levels of power consumption while in a standby state.
When CE# is pulled low the device will be selected and brought out of standby mode.
The device is considered active and instructions can be written to, data read, and
written to the device. After power-up, CE# must transition from high to low before a
new instruction will be accepted.
Keeping CE# in a high state deselects the device and switches it into its low power
state. Data will not be accepted when CE# is high.
SI (IO0),
SO (IO1)
INPUT/OUTPUT
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard
SPI instructions use the unidirectional SI (Serial Input) pin to write instructions,
addresses, or data to the device on the rising edge of the Serial Clock (SCK).
Standard SPI also uses the unidirectional SO (Serial Output) to read data or status
from the device on the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.
WP# (IO2)
INPUT/OUTPUT
Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from
being written in conjunction with the SRWD bit. When the SRWD is set to “1” and
the WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0)
are write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the
Status Register is not write-protected regardless of WP# state.
When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available
since this pin is used for IO2.
HOLD# (IO3) or
RESET# (IO3)
INPUT/OUTPUT
HOLD# (IO3) or RESET#/ (IO3): When the QE bit of Status Register is set to “1”,
HOLD# pin or RESET# is not available since it becomes IO3. When QE=0 the pin
acts as HOLD# or RESET#. The pin defaults HOLD#.
RESET# (IO3) pin instead of HOLD# (IO3) can be supported by optional part
(Call Factory).
The HOLD# pin allows the device to be paused while it is selected. It pauses serial
communication by the master device without resetting the serial sequence. The
HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin
will be at high impedance. Device operation can resume when HOLD# pin is brought
to a high state.
In optional device, RESET# pin is a hardware RESET signal. When RESET# is
driven HIGH, the memory is in the normal operating mode. When RESET# is driven
LOW, the memory enters reset mode and output is High-Z. If RESET# is driven
LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data
may be lost.
SCK
INPUT
Serial Data Clock: Synchronized Clock for input and output timing operations.
Vcc
POWER
Power: Device Core Power Supply
GND
GROUND
Ground: Connect to ground when referenced to Vcc
NC
Unused
NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 10
Rev. A12
04/15/2019
For the device with dedicated RESET#
SYMBOL
TYPE
DESCRIPTION
CE#
INPUT
Same as the description in previous page
SI (IO0),
SO (IO1)
INPUT/OUTPUT
Same as the description in previous page
WP# (IO2)
INPUT/OUTPUT
Same as the description in previous page
HOLD# (IO3)
INPUT/OUTPUT
Hold/Serial Data IO (IO3): When the QE bit of Status Register is set to “1”, HOLD#
pin is not available since it becomes IO3. When QE=0 the pin acts as HOLD#.
The HOLD# pin allows the device to be paused while it is selected. It pauses serial
communication by the master device without resetting the serial sequence. The
HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin
will be at high impedance. Device operation can resume when HOLD# pin is brought
to a high state.
RESET#
INPUT/OUTPUT
RESET: Dedicated RESET# function is available only for specific parts. The
RESET# pin (or ball) will be independent of the QE bit of Status Register.
The RESET# is a hardware RESET signal. When RESET# is driven HIGH, the
memory is in the normal operating mode. When RESET# is driven LOW, the
memory enters reset mode and output is High-Z. If RESET# is driven LOW while an
internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.
It has an internal pull-up resistor and may be left floating if not used.
SCK
INPUT
Same as the description in previous page
Vcc
POWER
Same as the description in previous page
GND
GROUND
Same as the description in previous page
NC
Unused
Same as the description in previous page
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 11
Rev. A12
04/15/2019
3. BLOCK DIAGRAM
Note1: For RESET# (IO3) pin option instead of HOLD# (IO3) pin, call Factory. In case of device with dedicated RESET#
function, RESET# is on pin3/ball A4. See the Ordering Information for the dedicated RESET# option.
Control Logic High Voltage Generator
I/O Buffers and
Data Latches
256 Bytes
Page Buffer
Y-Decoder
X-Decoder
Serial Peripheral Interface
Status
Register
Address Latch &
Counter
Memory Array
CE#
SCK
WP#
(IO2)
SI
(IO0)
SO
(IO1)
HOLD# or RESET#
(IO3)
WP# (IO2)
(1)
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 12
Rev. A12
04/15/2019
4. SPI MODES DESCRIPTION
Multiple IS25LP064A devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e.
microcontroller, as shown in Figure 4.1. The devices support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the
serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer
to Figure 4.2 and Figure 4.3 for SPI and QPI mode. In both modes, the input data is latched on the rising edge of
Serial Clock (SCK), and the output data is available from the falling edge of SCK.
Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
Notes:
1. For RESET# (IO3) option instead of HOLD# (IO3), call Factory.
2. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively
during QPI mode.
SPI interface with
(0,0) or (1,1)
SPI Master
(i.e. Microcontroller) SPI
Memory
Device
SPI
Memory
Device
SPI
Memory
Device
SCK SO SI
SCK
SDI
SDO
CE#
WP#HOLD#
SCK SO SI
CE#
WP#HOLD#
SCK SO SI
CE#
WP#
CS3CS2CS1
HOLD#
(1)
(1)
(1)
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 13
Rev. A12
04/15/2019
Figure 4.2 SPI Mode Support
SCK
SO
SI
Mode 0 (0,0)
Mode 3 (1,1)
MSB
MSB
SCK
Figure 4.3 QPI Mode Support
20
CE#
SCK
40 4 0
3-byte Address
16 12 8
0 1 2 3 4 5 6 78 9 10 11 12 13 14 15
Mode 3
Mode 0
IO0
IO121 51 5 1
17 13 9
22 62 6 2
18 14 10
73 3
19 15 11
Mode Bits
IO2
IO3
C4 C0
C1C5
C2C6
C3C71
40 4 0
51 5 1
62 6 2
3 3
4
5
6
0
1
2
3
...
...
...
...
Data 1 Data 2 Data 3
23171717171
6
Note1: MSB (Most Significant Bit)
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 14
Rev. A12
04/15/2019
5. SYSTEM CONFIGURATION
The memory array of the IS25LP064A is divided into uniform 4 Kbyte sectors or uniform 32/64 Kbyte blocks (a
block consists of eight/sixteen adjacent sectors respectively).
Table 5.1 illustrates the memory map of the device. The Status Register controls how the memory is protected.
5.1 BLOCK/SECTOR ADDRESSES
Table 5.1 Block/Sector Addresses of IS25LP064A/032A
Memory
Density
Block No.
(64Kbyte)
Block No.
(32Kbyte)
Sector No.
Sector Size
(Kbyte)
Address Range
64Mb
Block 0
Block 0
Sector 0
4
000000h 000FFFh
:
:
:
Block 1
:
:
:
Sector 15
4
00F000h - 00FFFFh
Block 1
Block 2
Sector 16
4
010000h 010FFFh
:
:
:
Block 3
:
:
:
Sector 31
4
01F000h - 01FFFFh
Block 2
Block 4
Sector 32
4
020000h 020FFFh
:
:
:
Block 5
:
:
:
Sector 47
4
02F000h 02FFFFh
:
:
:
:
:
Block 63
Block 126
Sector 1008
4
3F0000h 3F0FFFh
:
:
:
Block 127
:
:
:
Sector 1023
4
3FF000h 3FFFFFh
:
:
:
:
:
Block 127
Block 254
Sector 2032
4
7F0000h 7F0FFFh
:
:
:
Block 255
:
:
:
Sector 2047
4
7FF000h 7FFFFFh
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 15
Rev. A12
04/15/2019
6. REGISTERS
The device has various sets of Registers: Status, Function, and Read.
When the register is read continuously, the same byte is output repeatedly until CE# goes HIGH.
6.1 STATUS REGISTER
Status Register Format and Status Register Bit Definitions are described in Table 6.1 & Table 6.2.
Table 6.1 Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
QE
BP3
BP2
BP1
BP0
WEL
WIP
Default
0
0
0
0
0
0
0
0
Table 6.2 Status Register Bit Definition
Bit
Name
Definition
Read-
/Write
Type
Bit 0
WIP
Write In Progress Bit:
"0" indicates the device is ready(default)
"1" indicates a write cycle is in progress and the device is busy
R
Volatile
Bit 1
WEL
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
R/W1
Volatile
Bit 2
BP0
Block Protection Bit: (See Table 6.4 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
R/W
Non-Volatile
Bit 3
BP1
Bit 4
BP2
Bit 5
BP3
Bit 6
QE
Quad Enable bit:
“0” indicates the Quad output function disable (default)
“1” indicates the Quad output function enable
R/W
Non-Volatile
Bit 7
SRWD
Status Register Write Disable: (See Table 7.1 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
R/W
Non-Volatile
Note1: WEL bit can be written by WREN and WRDI commands, but cannot by WRSR command.
The BP0, BP1, BP2, BP3, QE, and SRWD are non-volatile memory cells that can be written by a Write Status
Register (WRSR) instruction. The default value of the BP0, BP1, BP2, BP3, QE, and SRWD bits were set to 0
at factory. The Status Register can be read by the Read Status Register (RDSR).
The function of Status Register bits are described as follows:
WIP bit: The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a
program or erase operation. When the WIP bit is “0”, the device is ready for write Status Register, program or
erase operation. When the WIP bit is “1”, the device is busy.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the WEL
is “0”, the write enable latch is disabled and the write operations described in Table 6.3 are inhibited. When the
WEL bit is “1”, the write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction. Each
write register, program and erase instruction except for Set Read Register must be preceded by a WREN
instruction. The WEL bit can be reset by a Write Disable (WRDI) instruction. It will automatically reset after the
completion of any write operation.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 16
Rev. A12
04/15/2019
Table 6.3 Instructions requiring WREN instruction ahead
Instructions must be preceded by the WREN instruction
Name
Hex Code
Operation
PP
02h
Serial Input Page Program
PPQ
32h/38h
Quad Input Page Program
SER
D7h/20h
Sector Erase
BER32 (32Kb)
52h
Block Erase 32K
BER64 (64Kb)
D8h
Block Erase 64K
CER
C7h/60h
Chip Erase
WRSR
01h
Write Status Register
WRFR
42h
Write Function Register
IRER
64h
Erase Information Row
IRP
62h
Program Information Row
BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of
the memory area to be protected. Refer to Table 6.4 for the Block Write Protection (BP) bit settings. When a
defined combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any
program or erase operation to that area will be inhibited.
Note: A Chip Erase (CER) instruction will be ignored unless all the Block Protection Bits are “0”s.
SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection (WP#)
signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not write-
protected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register (SRWD, QE,
BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to “1” and
WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) is a non-volatile bit in the Status Register that allows quad operation. When the
QE bit is set to 0, the pin WP# and HOLD# are enabled. When the QE bit is set to 1, the IO2 and IO3 pins are
enabled.
WARNING: The QE bit must be set to 0 if WP# or HOLD# pin is tied directly to the power supply.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 17
Rev. A12
04/15/2019
Table 6.4 Block (64Kbyte) assignment by Block Write Protect (BP) Bits
Status Register Bits
Protected Memory Area (IS25LP064A, 128Blocks)
BP3
BP2
BP1
BP0
TBS(T/B selection) = 0, Top area
TBS(T/B selection) = 1, Bottom area
0
0
0
0
0( None)
0( None)
0
0
0
1
1(1 block : 127th)
1(1 block : 0th)
0
0
1
0
2(2 blocks : 126th and 127th)
2(2 blocks : 0th and 1st)
0
0
1
1
3(4 blocks : 124th to 127th)
3(4 blocks : 0th to 3rd)
0
1
0
0
4(8 blocks : 120th to 127th)
4(8 blocks : 0th to 7th)
0
1
0
1
5(16 blocks : 112nd to 127th)
5(16 blocks : 0th to 15th)
0
1
1
0
6(32 blocks : 96th to 127th)
6(32 blocks : 0th to 31st)
0
1
1
1
7(64 blocks : 64th to 127th)
7(64 blocks : 0th to 63rd)
1
x
x
x
8~15(128 blocks : 0th to 127th) All blocks
8~15(128 blocks : 0th to 127th) All blocks
Note: x is don’t care
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 18
Rev. A12
04/15/2019
6.2 FUNCTION REGISTER
Function Register Format and Bit definition are described in Table 6.5 and Table 6.6.
Table 6.5 Function Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRL3
IRL2
IRL1
IRL0
ESUS
PSUS
TBS
Reserved
Default
0
0
0
0
0
0
0
0
Table 6.6 Function Register Bit Definition
Bit
Name
Definition
Read-
/Write
Type
Bit 0
Reserved
Reserved
R
Reserved
Bit 1
Top/Bottom
Selection
Top/Bottom Selection. (See Table 6.4 for details)
“0” indicates Top area.
“1” indicates Bottom area.
R/W
OTP
Bit 2
PSUS
Program suspend bit:
“0” indicates program is not suspend
“1” indicates program is suspend
R
Volatile
Bit 3
ESUS
Erase suspend bit:
"0" indicates Erase is not suspend
"1" indicates Erase is suspend
R
Volatile
Bit 4
IR Lock 0
Lock the Information Row 0:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
R/W
OTP
Bit 5
IR Lock 1
Lock the Information Row 1:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
R/W
OTP
Bit 6
IR Lock 2
Lock the Information Row 2:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
R/W
OTP
Bit 7
IR Lock 3
Lock the Information Row 3:
“0” indicates the Information Row can be programmed
“1” indicates the Information Row cannot be programmed
R/W
OTP
Note: Once OTP bits of Function Register are written to “1”, it cannot be modified to “0” any more.
Top/Bottom Selection: BP0~3 area assignment can be changed from Top (default) to Bottom by setting TBS bit
to “1”. However, once Bottom is selected, it cannot be changed back to Top since TBS bit is OTP. See Table 6.4
for details
PSUS bit: The Program Suspend Status bit indicates when a Program operation has been suspended. The PSUS
changes to 1 after a suspend command is issued during the program operation. Once the suspended Program
resumes, the PSUS bit is reset to 0”.
ESUS bit: The Erase Suspend Status indicates when an Erase operation has been suspended. The ESUS bit is
1 after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, the
ESUS bit is reset to 0”.
IR Lock bit 0 ~ 3: The default is 0” so that the Information Row can be programmed. If the bit set to “1”, the
Information Row cant be programmed. Once it set to “1”, it cannot be changed back to “0” since IR Lock bits are
OTP.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 19
Rev. A12
04/15/2019
6.3 READ REGISTER
Read Register format and Bit definitions pertaining to QPI mode are described below.
READ PARAMETER BITS
Table 6.7 defines all bits that control features in SPI/QPI modes. The ODS2, ODS1, ODS0 (P7, P6, P5) bits
provide a method to set and control driver strength. The Dummy Cycle bits (P4, P3) define how many dummy
cycles are used during various READ modes. The wrap selection bits (P2, P1, P0) define burst length with wrap
around.
The SET READ PARAMETERS Operation (SRP, C0h) is used to set all the Read Register bits, and can thereby
define the output driver strength, number of dummy cycles used during READ modes, burst length with wrap
around.
Table 6.7 Read Parameter Table
P7
P6
P5
P4
P3
P2
P1
P0
ODS2
ODS1
ODS0
Dummy
Cycles
Dummy
Cycles
Wrap
Enable
Burst
Length
Burst
Length
Default (Volatile)
1
1
1
0
0
0
0
0
Table 6.8 Burst Length Data
P1
P0
8 bytes
0
0
16 bytes
0
1
32 bytes
1
0
64 bytes
1
1
Table 6.9 Wrap Function
Wrap around boundary
P2
Whole array regardless of P1 and P0 value
0
Burst Length set by P1 and P0
1
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 20
Rev. A12
04/15/2019
Table 6.10 Read Dummy Cycles vs Max Frequency
Read Modes
P4,P3 = 00
(Default)
P4,P3 = 01
P4,P3 = 10
P4,P3 = 11
Remark
Mode
Normal Read
03h
0
0
0
0
Max. 50MHz
SPI
Fast Read (2)
0Bh
8
8
8
8
Max. 133MHz(1)
SPI
6
(104MHz)
4
(84MHz)
8(1)
(133MHz)
10(1)
(133MHz)
QPI
Fast Read DTR
0Dh
4
4
4
4
Max.66MHz
SPI
3
(51MHz)
2
(38MHz)
4
(64MHz)
5
(66MHz)
QPI
Fast Read Dual Output
3Bh
8
8
8
8
Max. 133MHz(1)
SPI
Fast Read Dual IO
BBh
4
(104MHz)
4
(104MHz)
8(1)
(133MHz)
8(1)
(133MHz)
SPI
Fast Read Dual IO DTR
BDh
2
(52MHz)
2
(52MHz)
4
(66MHz)
4
(66MHz)
SPI
Fast Read Quad Output
6Bh
8
8
8
8
Max. 133MHz(1)
SPI
Fast Read Quad IO
EBh
6
(104MHz)
4
(84MHz)
8(1)
(133MHz)
10(1)
(133MHz)
SPI , QPI
Fast Read Quad IO DTR
EDh
3
(51MHz)
2
(38MHz)
4
(64MHz)
5
(66MHz)
SPI , QPI
Notes:
1. Max frequency is 133 MHz at Vcc=2.7V~3.6V and 104MHz at Vcc=2.3V~3.6V.
2. RDUID, RDSFDP, IRRD instructions are also applied.
3. Dummy cycles in the table are including Mode bit cycles.
4. Must satisfy bus I/O contention. For instance, if the number of dummy cycles and AX bit cycles are same, then X
must be Hi-Z.
Table 6.11 Driver Strength Table
ODS2
ODS1
ODS0
Description
Remark
0
0
0
Reserved
0
0
1
12.50%
0
1
0
25%
0
1
1
37.50%
1
0
0
Reserved
1
0
1
75%
1
1
0
100%
1
1
1
50%
Default
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 21
Rev. A12
04/15/2019
7. PROTECTION MODE
The IS25LP064A supports hardware and software write-protection mechanisms.
7.1 HARDWARE WRITE PROTECTION
The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD,
and QE in the Status Register. Refer to the section 6.1 STATUS REGISTER.
Write inhibit voltage (VWI) is specified in the section 9.8 POWER-UP AND POWER-DOWN. All write sequence will
be ignored when Vcc drops to VWI.
Table 7.1 Hardware Write Protection on Status Register
SRWD
WP#
Status Register
0
Low
Writable
1
Low
Protected
0
High
Writable
1
High
Writable
Note: Before the execution of any program, erase or write Status/Function Register instruction, the Write Enable
Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled,
the program, erase or write register instruction will be ignored.
7.2 SOFTWARE WRITE PROTECTION
The IS25LP064A also provides a software write protection feature. The Block Protection (TBS, BP3, BP2, BP1,
BP0) bits allow part or the whole memory area to be write-protected.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 22
Rev. A12
04/15/2019
8. DEVICE OPERATION
The IS25LP064A utilizes an 8-bit instruction register. Refer to Table 8.1. Instruction Set for details on instructions
and instruction codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first
on Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3). The input data on SI or IOs is latched on the
rising edge of Serial Clock (SCK) for normal mode and both of rising and falling edges for DTR mode after Chip
Enable (CE#) is driven low (VIL). Every instruction sequence starts with a one-byte instruction code and is followed
by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. CE#
must be driven high (VIH) after the last bit of the instruction sequence has been shifted in to end the operation.
Table 8.1 Instruction Set
Instructio
n
Name
Operation
Mode
Byte0
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
NORD
Normal Read
Mode
SPI
03h
A
<23:16>
A
<15:8>
A
<7:0>
Data out
FRD
Fast Read
Mode
SPI
QPI
0Bh
A
<23:16>
A
<15:8>
A
<7:0>
Dummy(1)
Byte
Data out
FRDIO
Fast Read
Dual I/O
SPI
BBh
A
<23:16>
Dual
A
<15:8>
Dual
A
<7:0>
Dual
AXh(1),(2)
Dual
Dual
Data out
FRDO
Fast Read
Dual Output
SPI
3Bh
A
<23:16>
A
<15:8>
A
<7:0>
Dummy(1)
Byte
Dual
Data out
FRQIO
Fast Read
Quad I/O
SPI
QPI
EBh
A
<23:16>
Quad
A
<15:8>
Quad
A
<7:0>
Quad
AXh(1), (2)
Quad
Quad
Data out
FRQO
Fast Read
Quad Output
SPI
6Bh
A
<23:16>
A
<15:8>
A
<7:0>
Dummy(1)
Byte
Quad
Data out
FRDTR
Fast Read
DTR Mode
SPI
QPI
0Dh
A
<23:16>
A
<15:8>
A
<7:0>
Dummy(1)
Byte
Dual
Data out
FRDDTR
Fast Read
Dual I/O DTR
SPI
BDh
A
<23:16>
Dual
A
<15:8>
Dual
A
<7:0>
Dual
AXh(1), (2)
Dual
Dual
Data out
FRQDTR
Fast Read
Quad I/O DTR
SPI
QPI
EDh
A
<23:16>
A
<15:8>
A
<7:0>
AXh(1), (2)
Quad
Quad
Data out
PP
Input Page
Program
SPI
QPI
02h
A
<23:16>
A
<15:8>
A
<7:0>
PD
(256byte)
PPQ
Quad Input
Page Program
SPI
32h
38h
A
<23:16>
A
<15:8>
A
<7:0>
Quad PD
(256byte)
SER
Sector Erase
SPI
QPI
D7h
20h
A
<23:16>
A
<15:8>
A
<7:0>
BER32
(32Kb)
Block Erase
32K
SPI
QPI
52h
A
<23:16>
A
<15:8>
A
<7:0>
BER64
(64Kb)
Block Erase
64K
SPI
QPI
D8h
A
<23:16>
A
<15:8>
A
<7:0>
CER
Chip Erase
SPI
QPI
C7h
60h
WREN
Write Enable
SPI
QPI
06h
WRDI
Write Disable
SPI
QPI
04h
RDSR
Read Status
Register
SPI
QPI
05h
SR
WRSR
Write Status
Register
SPI
QPI
01h
WSR
Data
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 23
Rev. A12
04/15/2019
Instructio
n
Name
Operation
Mode
Byte0
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
RDFR
Read Function
Register
SPI
QPI
48h
Data
out
WRFR
Write Function
Register
SPI
QPI
42h
WFR
Data
QPIEN
Enter
QPI mode
SPI
35h
QPIDI
Exit
QPI mode
QPI
F5h
PERSUS
Suspend during
program/erase
SPI
QPI
75h
B0h
PERRSM
Resume
program/erase
SPI
QPI
7Ah
30h
DP
Deep Power
Down
SPI
QPI
B9h
RDID,
RDPD
Read ID /
Release
Power Down
SPI
QPI
ABh
XXh(3)
XXh(3)
XXh(3)
ID7-ID0
SRP
Set Read
Parameters
SPI
QPI
C0h
Data in
RDJDID
Read JEDEC
ID Command
SPI
QPI
9Fh
MF7-MF0
ID15-ID8
ID7-ID0
RDMDID
Read
Manufacturer
& Device ID
SPI
QPI
90h
XXh(3)
XXh(3)
00h
MF7-MF0
ID7-ID0
01h
ID7-ID0
MF7-MF0
RDJDIDQ
Read JEDEC
ID
QPI mode
QPI
AFh
MF7-MF0
ID15-ID8
ID7-ID0
RDUID
Read
Unique ID
SPI
QPI
4Bh
A(4)
<23:16>
A(4)
<15:8>
A(4)
<7:0>
Dummy
Byte
Data out
RDSFDP
SFDP Read
SPI
QPI
5Ah
A
<23:16>
A
<15:8>
A
<7:0>
Dummy
Byte
Data out
NOP
No Operation
SPI
QPI
00h
RSTEN
Software
Reset
Enable
SPI
QPI
66h
RST
Software Reset
SPI
QPI
99h
IRER
Erase
Information
Row
SPI
QPI
64h
A
<23:16>
A
<15:8>
A
<7:0>
IRP
Program
Information
Row
SPI
QPI
62h
A
<23:16>
A
<15:8>
A
<7:0>
PD
(256byte)
IRRD
Read
Information
Row
SPI
QPI
68h
A
<23:16>
A
<15:8>
A
<7:0>
Dummy
Byte
Data out
SECUN-
LOCK
Sector Unlock
SPI
QPI
26h
A
<23:16>
A
<15:8>
A
<7:0>
SECLOCK
Sector Lock
SPI
QPI
24h
Notes:
1. The number of dummy cycles depends on the value setting in the Table 6.10 Read Dummy Cycles.
2. AXh has to be counted as a part of dummy cycles. X means “don’t care”.
3. XX means “don’t care”.
4. A<23:9> are “don’t care” and A<8:4> are always “0”.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 24
Rev. A12
04/15/2019
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 25
Rev. A12
04/15/2019
8.1 NORMAL READ OPERATION (NORD, 03h)
The NORMAL READ (NORD) instruction is used to read memory contents of the IS25LP064A at a maximum
frequency of 50MHz.
The NORD instruction code is transmitted via the SI line, followed by three address bytes (A23 - A0) of the first
memory location to be read. A total of 24 address bits are shifted in, but only AMSB (most significant bit) - A0 are
decoded. The remaining bits (A23 AMSB+1) are ignored. The first byte addressed can be at any memory location.
Upon completion, any data on the SI will be ignored. Refer to Table 8.2 for the related Address Key.
The first byte data (D7 - D0) is shifted out on the SO line, MSB first. A single byte of data, or up to the whole
memory array, can be read out in one NORMAL READ instruction. The address is automatically incremented by
one after each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high
(VIH) after the data comes out. When the highest address of the device is reached, the address counter will roll
over to the 000000h address, allowing the entire memory to be read in one continuous READ instruction.
If the NORMAL READ instruction is issued while an Erase, Program or Write operation is in process (WIP=1) the
instruction is ignored and will not have any effects on the current operation.
Table 8.2 Address Key
Address
IS25LP064A
AMSB A0
A23 - A0 (A23=X)
X=Don’t Care
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 26
Rev. A12
04/15/2019
Figure 8.1 Normal Read Sequence
7 6
CE#
SCK
SI
532
SO 410
Data Out 1
Instruction = 03h23
CE#
SCK
SI 32
SO
1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 78 9 10 ... 28 29 30 31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Mode 3
Mode 0
...
76 5 324 10
tV
Data Out 2
...
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 27
Rev. A12
04/15/2019
8.2 FAST READ OPERATION (FRD, 0Bh)
The FAST READ (FRD) instruction is used to read memory data at up to a 133MHz clock.
The FAST READ instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte from the
address is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling edge
of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FAST READ instruction. The FAST READ
instruction is terminated by driving CE# high (VIH).
If the FAST READ instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction
is ignored without affecting the current cycle.
Figure 8.2 Fast Read Sequence
Instruction = 0Bh
3-byte Address
28 29 30 31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 ...
7 6
CE#
SCK
SI
532
SO 41
Data Out
31
CE#
SCK
SI 32
SO
1 0
High Impedance
30 29 ...
0 1 2 3 4 5 6 78 9 10 ...
Mode 3
Mode 0
tV
Dummy Cycles
0...
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 28
Rev. A12
04/15/2019
FAST READ QPI OPERATION (FRD QPI, 0Bh)
The FAST READ QPI (FRD QPI) instruction is used to read memory data at up to a 133MHz clock.
The FAST READ QPI instruction code (2 clocks) is followed by three address bytes (A23-A06clocks) and 6
dummy cycles (configurable, default is 6 clocks), transmitted via the IO3, IO2, IO1 and IO0 lines, with each bit
latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the IO3, IO2, IO1
and IO0 lines, with each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FAST READ QPI instruction. The FAST
READ QPI instruction is terminated by driving CE# high (VIH).
If the FAST READ QPI instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored without affecting the current cycle.
Table 8.3 Instructions that Fast Read QPI sequence is applied to
Instruction Name
Operation
Hex Code
FRQIO
Fast Read Quad I/O
EBh
RDUID
Read Unique ID
4Bh
RDSFDP
SFDP Read
5Ah
IRRD
Read Information Row
68h
Figure 8.3 Fast Read QPI Sequence
0Bh
CE#
SCK
IO[3:0]
6 Dummy Cycles
3-byte Address
0 1 2 3 4 5 6 78 9 ... 13 14 15 16 17
Mode 3
Mode 0
23:20 7:4 3:0 7:4 3:0
Data 1 Data 2
19:16 15:12 11:8 7:4 3:0
...
tV
...
Instruction
Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.10 Read Dummy
Cycles.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 29
Rev. A12
04/15/2019
8.3 HOLD OPERATION
HOLD# is used in conjunction with CE# to select the IS25LP064A. When the device is selected and a serial
sequence is underway, HOLD# can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial
communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs
to SI will be ignored while SO is in the high impedance state, during HOLD.
Note: HOLD is not supported in DTR mode or with QE=1 or for the specific parts that do not have HOLD# pin.
Timing graph can be referenced in AC Parameters Figure 9.4
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh)
The FRDIO allows the address bits to be input two bits at a time. This may allow for code to be executed directly
from the SPI in some applications.
The FRDIO instruction code is followed by three address bytes (A23 A0) and dummy cycles (configurable,
default is 4 clocks), transmitted via the IO1 and IO0 lines, with each pair of bits latched-in during the rising edge
of SCK. The address MSB is input on IO1, the next bit on IO0, and this shift pattern continues to alternate between
the two lines. Depending on the usage of AX read operation mode, a mode byte may be located after address
input.
The first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum
frequency fCT, during the falling edge of SCK. The MSB is output on IO1, while simultaneously the second bit is
output on IO0. Figure 8.4 illustrates the timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is
terminated by driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8
bits, such as M7 to M0. Four cycles after address input are reserved for Mode bits in FRDIO execution. M7 to M4
are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it
enables the AX read operation and subsequent FRDIO execution skips command code. It saves cycles as
described in Figure 8.5. When the code is different from AXh (where X is don’t care), the device exits the AX read
operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI mode
configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy cycle in
Table 6.10 includes number of mode bit cycles. If dummy cycles is configured as 4 cycles, data output will starts
right after mode bit applied.
If the FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not affect the current cycle.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 30
Rev. A12
04/15/2019
Figure 8.4 Fast Read Dual I/O Sequence (with command decode cycles)
7 5 3 751 31
Data Out 1
Instruction = BBh22
CE#
SCK
20 6 4
3-byte Address
High Impedance
20 18 ...
0 1 2 3 4 5 6 78 9 10 ... 18 19 20 21
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Mode 3
Mode 0
...
tV
23 31 7 5
21 19 ...
IO0
IO1
3 1
2 0 6 4 2 640 20
4 Dummy Cycles
7531
6420
75...
64...
CE#
SCK
IO0
IO1
Data Out 2 Data Out 3
Mode Bits
Mode Bits
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10. Read Dummy Cycles.
3. Since the number of dummy cycles and AX bit cycles are same in the above Figure, X should be Hi-Z to avoid I/O
contention.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 31
Rev. A12
04/15/2019
Figure 8.5 Fast Read Dual I/O AX Read Sequence (without command decode cycles)
22
CE#
SCK
20
3-byte Address
20 18 ...
0 1 2 3 ... 11 12 13 14 15 16 17 18 19 20 21
Mode 3
Mode 0
23 31
21 19 ...
IO0
IO1
4 Dummy Cycles
6
7
64
75
20
31
Data Out 1
tV
64
75
20
31
4
5
Mode Bits
...
...
Data Out 2
...
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
3. Since the number of dummy cycles and AX bit cycles are same in the above Figure, X should be Hi-Z to avoid I/O
contention.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 32
Rev. A12
04/15/2019
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)
The FRDO instruction is used to read memory data on two output pins each at up to a 133MHz clock.
The FRDO instruction code is followed by three address bytes (A23 A0) and a dummy byte (8 clocks),
transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the first data byte
addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum frequency fCT,
during the falling edge of SCK. The first bit (MSB) is output on IO1. Simultaneously the second bit is output on
IO0.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDO instruction. The FRDO instruction is
terminated by driving CE# high (VIH).
If the FRDO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is
ignored and will not have any effects on the current cycle.
Figure 8.6 Fast Read Dual Output Sequence
CE#
SCK
75
Data Out 1
Instruction = 3Bh 23
CE#
SCK
32 1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 78 9 10 ... 28 29 30 31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Mode 3
Mode 0
...
tV
IO0
IO1
64
3175
2064
31...
20...
Data Out 2
IO0
IO1
8 Dummy Cycles
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 33
Rev. A12
04/15/2019
8.6 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh)
The FRQO instruction is used to read memory data on four output pins each at up to a 133 MHz clock.
A
Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad Output instruction.
The FRQO instruction code is followed by three address bytes (A23 A0) and a dummy byte (8 clocks),
transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK. Then the first data byte
addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted out at a maximum
frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while simultaneously the
second bit is output on IO2, the third bit is output on IO1, etc.
The first byte addressed can be at any memory location. The address is automatically incremented after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRQO instruction. FRQO instruction is
terminated by driving CE# high (VIH).
If a FRQO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction
is ignored and will not have any effects on the current cycle.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 34
Rev. A12
04/15/2019
Figure 8.7 Fast Read Quad Output Sequence
CE#
SCK
51
Data Out 1
Instruction = 6Bh 23
CE#
SCK
32 1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 78 9 10 ... 28 29 30 31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Mode 3
Mode 0
...
tV
IO0
IO1
40
5151
4040
51...
40...
IO0
IO1
8 Dummy Cycles
High Impedance
IO2
High Impedance
IO3
73
62
7373
6262
73...
62...
IO2
IO3
Data Out 2 Data Out 3 Data Out 4
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 35
Rev. A12
04/15/2019
8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh)
The FRQIO instruction allows the address bits to be input four bits at a time. This may allow for code to be
executed directly from the SPI in some applications.
A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad I/O instruction.
The FRQIO instruction code is followed by three address bytes (A23 A0) and dummy cycles (configurable,
default is 6 clocks), transmitted via the IO3, IO2, IO1 and IO0 lines, with each group of four bits latched-in during
the rising edge of SCK. The address of MSB inputs on IO3, the next bit on IO2, the next bit on IO1, the next bit
on IO0, and continue to shift in alternating on the four. Depending on the usage of AX read operation mode, a
mode byte may be located after address input.
The first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted
out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while
simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 8.8 illustrates the timing
sequence.
The first byte addressed can be at any memory location. The address is automatically incremented after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is terminated
by driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consists of 8
bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO execution. M7 to M4
are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it
enables the AX read operation and subsequent FRQIO execution skips command code. It saves cycles as
described in Figure 8.9. When the code is different from AXh (where X is don’t care), the device exits the AX read
operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI mode
configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy cycle in
Table 6.10 includes number of mode bit cycles. If dummy cycles is configured as 6 cycles, data output will starts
right after mode bits and 4 additional dummy cycles are applied.
If the FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 36
Rev. A12
04/15/2019
Figure 8.8 Fast Read Quad I/O Sequence (with command decode cycles)
CE#
SCK
51
Data Out 1
Instruction = EBh 20
CE#
SCK
40 4 0
3-byte Address
High Impedance
16 12 8
0 1 2 3 4 5 6 78 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Mode 3
Mode 0
...
tV
IO0
IO1
40
5151
4040
51
40
IO0
IO1
21 51 5 1
17 13 9
22 62 6 2
18 14 10
23 73 7 3
19 15 11
Mode Bits
IO2
IO3
62626262
73737373
Data Out 2 Data Out 3 Data Out 4
IO2
IO3
1
0
51...
40...
262...
373...
5
4
6
7
6 Dummy Cycles Data Out 5 Data Out 6
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 37
Rev. A12
04/15/2019
Figure 8.9 Fast Read Quad I/O AX Read Sequence (without command decode cycles)
20
CE#
SCK
40 4 0
3-byte Address
16 12 8
0 1 2 3 4 5 6 78 9 10 11 12 13 14 15
Mode 3
Mode 0
IO0
IO121 51 5 1
17 13 9
22 62 6 2
18 14 10
23 73 7 3
19 15 11
Mode Bits
IO2
IO3
51
40
51
40
6262
7373
...
...
...
...
Data Out 1 Data Out 2
...
tV
6 Dummy Cycles
Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When
the mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 38
Rev. A12
04/15/2019
FAST READ QUAD I/O OPERATION IN QPI MODE (FRQIO, EBh)
The FRQIO instruction in QPI mode is used to read memory data.
It is not required to set QE bit to “1”.before Fast Read Quad I/O instruction in QPI mode.
The FRQIO instruction in QPI mode utilizes all four IO lines to input the instruction code so that only two clocks
are required, while the FRQIO instruction in SPI mode requires that the byte-long instruction code is shifted into
the device only via IO0 line in eight clocks. As a result, 6 command cycles will be reduced by the FRQIO instruction
in QPI mode. In addition, subsequent address and data out are shifted in/out via all four IO lines. In fact, except
for the command cycle, the FRQIO operation in QPI mode is exactly same as the FRQIO operation in SPI mode.
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8
bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO execution. M7 to M4
are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it
enables the AX read operation and subsequent FRQIO execution skips command code. It saves cycles as
described in Figure 8.9. When the code is different from AXh (where X is don’t care), the device exits the AX read
operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI mode
configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy cycles
in Table 6.10 includes number of mode bit cycles. If dummy cycles are configured as 6 cycles, data output will
start right after mode bits and 4 additional dummy cycles are applied.
If the FRQIO instruction in QPI mode is issued while an Erase, Program or Write cycle is in process (WIP=1) the
instruction is ignored and will not have any effects on the current cycle.
Figure 8.10 Fast Read Quad I/O Sequence In QPI Mode
EBh
CE#
SCK
IO[3:0]
6 Dummy Cycles
3-byte Address
0 1 2 3 4 5 6 78 9
...
13 14 15 16 17
Mode 3
Mode 0
23:20 7:4 3:0 7:4 3:0
Data 1 Data 2
19:16 15:12 11:8 7:4 3:0
...
tV
Instruction
Mode Bits
7:4 3:0
...
Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.10 Read Dummy
Cycles.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 39
Rev. A12
04/15/2019
8.8 PAGE PROGRAM OPERATION (PP, 02h)
The Page Program (PP) instruction allows up to 256 bytes data to be programmed into memory in a single
operation. The destination of the memory to be programmed must be outside the protected memory area set by
the Block Protection (BP3, BP2, BP1, BP0) bits. A PP instruction which attempts to program into a page that is
write-protected will be ignored. Before the execution of PP instruction, the Write Enable Latch (WEL) must be
enabled through a Write Enable (WREN) instruction.
The PP instruction code, three address bytes and program data (1 to 256 bytes) are input via the Sl line. Program
operation will start immediately after the CE# is brought high, otherwise the PP instruction will not be executed.
The internal control logic automatically handles the programming voltages and timing. The progress or completion
of the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If
the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around
to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other
bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 40
Rev. A12
04/15/2019
Figure 8.11 Page Program Sequence
Instruction = 02h 23
CE#
SCK
SI 76
SO
7
3-byte Address
High Impedance
22 ... 0
Data In 1 Data In 256
0 1 ... 7 8 9 ... 31 32 33 ... 39 ...
2072
...
2079
Mode 3
Mode 0
... 0... ... 0
Figure 8.12 Page Program QPI Sequence
02h
CE#
SCK
IO[3:0]
3-byte Address
0 1 2 3 4 5 6 78 9 10 11 12 13 14 15
Mode 3
Mode 0
23:20 7:4 3:0 7:4 3:0
Data In 1 Data In 2
19:16 15:12 11:8 7:4 3:0 7:4 3:0 7:4 3:0
Data In 3 Data In 4
...
...
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 41
Rev. A12
04/15/2019
8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h)
The Quad Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a single
operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must be
outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Quad Input Page
Program instruction which attempts to program into a page that is write-protected will be ignored.
Before the execution of Quad Input Page Program instruction, the QE bit in the Status Register must be set to 1
and the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction.
Program operation will start immediately after the CE# is brought high, otherwise the Quad Input Page Program
instruction will not be executed. The internal control logic automatically handles the programming voltages and
timing. The progress or completion of the program operation can be determined by reading the WIP bit in Status
Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the
program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap
around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all
other bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
Figure 8.13 Quad Input Page Program Sequence
Instruction = 32h/38h23
CE#
SCK
40 4 0
3-byte Address
High Impedance
22 ... 0
0 1 2 3 4 5 6 78 9 31 32 33 34 35
Mode 3
Mode 0
IO0
IO151 5 1
62 6 2
73 7 3
Data In 2
IO2
IO3
...
Data In 1
...
...
...
...
...
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 42
Rev. A12
04/15/2019
8.10 ERASE OPERATION
The memory array of the IS25LP064A is organized into uniform 4 Kbyte sectors or 32/64 Kbyte uniform blocks (a
block consists of eight/sixteen adjacent sectors respectively).
Before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to
“1”). In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase
(BER) and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without affecting
the data in other sectors. A block erase operation erases any individual block. A chip erase operation erases the
whole memory array of a device. A sector erase, block erase, or chip erase operation can be executed prior to
any programming operation.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 43
Rev. A12
04/15/2019
8.11 SECTOR ERASE OPERATION (SER, D7h/20h)
A Sector Erase (SER) instruction erases a 4 Kbyte sector before the execution of a SER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is automatically reset after
the completion of Sector Erase operation.
A SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire instruction
sequence The SER instruction code, and three address bytes are input via SI. Erase operation will start
immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and timing.
The progress or completion of the erase operation can be determined by reading the WIP bit in the Status Register
using a RDSR instruction.
If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase operation has been
completed.
Figure 8.14 Sector Erase Sequence
Instruction = D7h/20h23
CE#
SCK
SI 32
SO
1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 78 9 10 ... 28 29 30 31
Mode 3
Mode 0
Figure 8.15 Sector Erase QPI Sequence
D7h/20h
CE#
SCK
IO[3:0]
3-byte Address
0 1 2 3 4 5 6 7
Mode 3
Mode 0
23:20 19:16 15:12 11:8 7:4 3:0
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 44
Rev. A12
04/15/2019
8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h)
A Block Erase (BER) instruction erases a 32/64 Kbyte block. Before the execution of a BER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the
completion of a block erase operation.
The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic automatically
handles the erase voltage and timing.
Figure 8.16 Block Erase (64K) Sequence
Instruction = D8h 23
CE#
SCK
SI 32
SO
1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 78 9 10 ... 28 29 30 31
Mode 3
Mode 0
Figure 8.17 Block Erase (64K) QPI Sequence
D8h
CE#
SCK
IO[3:0]
3-byte Address
0 1 2 3 4 5 6 7
Mode 3
Mode 0
23:20 19:16 15:12 11:8 7:4 3:0
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 45
Rev. A12
04/15/2019
Figure 8.18 Block Erase (32K) Sequence
Instruction = 52h23
CE#
SCK
SI 32
SO
1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 78 9 10 ... 28 29 30 31
Mode 3
Mode 0
Figure 8.19 Block Erase (32K) QPI Sequence
52h
CE#
SCK
IO[3:0]
3-byte Address
0 1 2 3 4 5 6 7
Mode 3
Mode 0
23:20 19:16 15:12 11:8 7:4 3:0
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 46
Rev. A12
04/15/2019
8.13 CHIP ERASE OPERATION (CER, C7h/60h)
A Chip Erase (CER) instruction erases the entire memory array. Before the execution of CER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is automatically reset after
completion of a chip erase operation.
The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,
otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase
voltage and timing.
Figure 8.20 Chip Erase Sequence
Instruction = C7h/60h
CE#
SCK
SI
0 1 2 3 4 5 6 7
Mode 3
Mode 0
SO High Impedance
Figure 8.21 Chip Erase QPI Sequence
C7h/60h
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 47
Rev. A12
04/15/2019
8.14 WRITE ENABLE OPERATION (WREN, 06h)
The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit is reset to the
write-protected state after power-up. The WEL bit must be write enabled before any write operation, including
Sector Erase, Block Erase, Chip Erase, Page Program, Program Information Row, Write Status Register, and
Write Function Register operations. The WEL bit will be reset to the write-protected state automatically upon
completion of a write operation. The WREN instruction is required before any above operation is executed.
Figure 8.22 Write Enable Sequence
Instruction = 06h
CE#
SCK
SI
0 1 2 3 4 5 6 7
Mode 3
Mode 0
SO High Impedance
Figure 8.23 Write Enable QPI Sequence
06h
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 48
Rev. A12
04/15/2019
8.15 WRITE DISABLE OPERATION (WRDI, 04h)
The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI instruction
is not required after the execution of a write instruction, since the WEL bit is automatically reset.
Figure 8.24 Write Disable Sequence
Instruction = 04h
CE#
SCK
SI
0 1 2 3 4 5 6 7
Mode 3
Mode 0
SO High Impedance
Figure 8.25 Write Disable QPI Sequence
04h
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 49
Rev. A12
04/15/2019
8.16 READ STATUS REGISTER OPERATION (RDSR, 05h)
The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a
program, erase or write Status Register operation, RDSR instruction can be used to check the progress or
completion of an operation by reading the WIP bit of Status Register.
Figure 8.26 Read Status Register Sequence
Instruction = 05h
7
CE#
SCK
SI
32
SO 1 0
Data Out
6 5
0 1 2 3 4 5 6 78 9 10 11 12 13 14 15
Mode 3
Mode 0
4
tV
Figure 8.27 Read Status Register QPI Sequence
05h
0 1
Mode 3
Mode 0
2 3
7:4 3:0
CE#
SCK
IO[3:0]
tV
Data Out
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 50
Rev. A12
04/15/2019
8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h)
The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and Status
Register write protection features by writing 0”s or “1”s into the non-volatile BP3, BP2, BP1, BP0, and SRWD
bits. Also WRSR instruction allows the user to disable or enable quad operation by writing “0” or “1” into the non-
volatile QE bit.
Figure 8.28 Write Status Register Sequence
Instruction = 01h
CE#
SCK
SI
SO
Data In
0 1 2 3 4 5 6 78 9 10 11 12 13 14 15
Mode 3
Mode 0
732 1 0
6 5 4
High Impedence
Figure 8.29 Write Status Register QPI Sequence
01h
0 1
Mode 3
Mode 0
2 3
7:4 3:0
CE#
SCK
IO[3:0]
Data In
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 51
Rev. A12
04/15/2019
8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h)
The Read Function Register (RDFR) instruction provides access to the Function Register. Refer to Table 6.6
Function Register Bit Definition for more detail.
Figure 8.30 Read Function Register Sequence
Instruction = 48h
7
CE#
SCK
SI
32
SO 1 0
Data Out
6 5
0 1 2 3 4 5 6 78 9 10 11 12 13 14 15
Mode 3
Mode 0
4
tV
Figure 8.31 Read Function Register QPI Sequence
48h
0 1
Mode 3
Mode 0
2 3
7:4 3:0
CE#
SCK
IO[3:0]
tV
Data Out
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 52
Rev. A12
04/15/2019
8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)
The Write Function Register (WRFR) instruction allows the user to change from top block area (default) to bottom
block area by setting TBS bit to “1”.
Also Information Row Lock bits (IRL3~IRL0) can be set to 1” individually by WRFR instruction in order to lock
Information Row. Since TBS bit and IRL bits are OTP, once it is set to “1”, it cannot be set back to “0” again.
Figure 8.32 Write Function Register Sequence
Instruction = 42h
CE#
SCK
SI
SO
Data In
0 1 2 3 4 5 6 78 9 10 11 12 13 14 15
Mode 3
Mode 0
732 1 0
6 5 4
High Impedence
Figure 8.33 Write Function Register QPI Sequence
42h
0 1
Mode 3
Mode 0
2 3
7:4 3:0
CE#
SCK
IO[3:0]
Data In
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 53
Rev. A12
04/15/2019
8.20 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN, 35h; QPIDI, F5h)
The Enter Quad Peripheral Interface (QPIEN) instruction, 35h, enables the Flash device for QPI mode operation.
Upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a power
cycle or an Exit Quad Peripheral Interface (QPIDI) instruction is sent to device.
The Exit Quad Peripheral Interface (QPIDI) instruction, F5h, resets the device to 1-bit SPI protocol operation. To
execute a QPIDI instruction, the host drives CE# low, sends the QPIDI command cycle, then drives CE# high.
The device just accepts QPI (2 clocks) command cycles.
Figure 8.34 Enter Quad Peripheral Interface (QPI) Mode Sequence
Instruction = 35h
CE#
SCK
SI
0 1 2 3 4 5 6 7
Mode 3
Mode 0
SO High Impedance
Figure 8.35 Exit Quad Peripheral Interface (QPI) Mode Sequence
F5h
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 54
Rev. A12
04/15/2019
8.21 PROGRAM/ERASE SUSPEND & RESUME
The device allows the interruption of Sector-Erase, Block-Erase or Page-Program operations to conduct other
operations. 75h/B0h command for suspend and 7Ah/30h for resume will be used. (SPI/QPI all acceptable)
Function Register bit2 (PSUS) and bit3 (ESUS) are used to check whether or not the device is in suspend mode.
Suspend to read ready timing (tSUS): 100µs (TYP)
Resume to another suspend timing (tRS): 400µs (TYP)
SUSPEND DURING SECTOR-ERASE OR BLOCK-ERASE (PERSUS 75h/B0h)
The Suspend command allows the interruption of Sector Erase and Block Erase operations. But Suspend
command will be ignored during Chip Erase operation. After the Suspend command, other commands include
array read operation can be accepted.
But Write Status Register command (01h) and Erase instructions are not allowed during Erase Suspend. Also,
array read for being erased sector/block is not allowed.
To execute Erase Suspend operation, the host drives CE# low, sends the Suspend command cycle (75h/B0h),
then drives CE# high. The Function Register indicates that the Erase has been suspended by setting the ESUS
bit from “0” to “1”, but the device will not accept another command until it is ready. To determine when the device
will accept a new command, poll the WIP bit or wait the specified time tSUS. When ESUS bit is set to 1”, the Write
Enable Latch (WEL) bit clears to “0”.
SUSPEND DURING PAGE PROGRAMMING (PERSUS 75h/B0h)
The Suspend command also allows the interruption of all array Program operations. After the Suspend command,
other commands include array read operation can be accepted can be accepted.
But Write Status Register instruction (01h) and Program instructions are not allowed during Program Suspend.
Also, array read for being programmed page is not allowed.
To execute the Program Suspend operation, the host drives CE# low, sends the Suspend command cycle
(75h/B0h), then drives CE# high. The Function Register indicates that the programming has been suspended by
setting the PSUS bit from “0” to “1”, but the device will not accept another command until it is ready. To determine
when the device will accept a new command, poll the WIP bit or wait the specified time tSUS. When PSUS bit is
set to “1”, the Write Enable Latch (WEL) bit clears to “0”.
PROGRAM/ERASE RESUME (PERRSM 7Ah/30h)
The Program/Erase Resume restarts the Program or Erase command that was suspended, and clears the
suspend status bit in the Function Register (ESUS or PSUS bits) to “0”. To execute the Program/Erase Resume
operation, the host drives CE# low, sends the Program/Erase Resume command cycle (7Ah/30h), then drives
CE# high. A cycle is two nibbles long, most significant nibble first. To issue another Erase Suspend operation
after Erase Resume operation, Erase Resume to another Erase Suspend delay (400us) is required, but it could
require longer Erase time to complete Erase operation.
To determine if the internal, self-timed Write operation completed, poll the WIP bit.
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 55
Rev. A12
04/15/2019
Table 8.4 Instructions accepted during Suspend
Operation
Suspended
Instruction Allowed
Name
Hex Code
Operation
Program or Erase
NORD
03h
Read Data Bytes from Memory at Normal Read Mode
Program or Erase
FRD
0Bh
Read Data Bytes from Memory at Fast Read Mode
Program or Erase
FRDIO
BBh
Fast Read Dual I/O
Program or Erase
FRDO
3Bh
Fast Read Dual Output
Program or Erase
FRQIO
EBh
Fast Read Quad I/O
Program or Erase
FRQO
6Bh
Fast Read Quad Output
Program or Erase
FRDTR
0Dh
Fast Read DTR Mode
Program or Erase
FRDDTR
BDh
Fast Read Dual I/O DTR
Program or Erase
FRQDTR
EDh
Fast Read Quad I/O DTR
Program or Erase
RDSR
05h
Read Status Register
Program or Erase
RDFR
48h
Read Function Register
Program or Erase
PERRSM
7Ah/30h
Resume program/erase
Program or Erase
RDID
ABh
Read Manufacturer and Product ID
Program or Erase
SRP
C0
Set Read Parameters (Volatile)
Program or Erase
RDJDID
9Fh
Read Manufacturer and Product ID by JEDEC ID Command
Program or Erase
RDMDID
90h
Read Manufacturer and Device ID
Program or Erase
RDJDIDQ
AFh
Read JEDEC ID QPI mode
Program or Erase
RDUID
4Bh
Read Unique ID Number
Program or Erase
RDSFDP
5Ah
SFDP Read
Program or Erase
NOP
00h
No Operation
Program or Erase
RSTEN
66h
Software reset enable
Program or Erase
RST
99h
Reset (Only along with 66h)
Program or Erase
IRRD
68h
Read Information Row
IS25LP064A
Integrated Silicon Solution, Inc.- www.issi.com 56
Rev. A12
04/15/2019
8.22 ENTER DEEP POWER DOWN (DP, B9h)
The Enter Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption
(enter into Power-down mode). During this mode, standby current is reduced from Isb1 to Isb2