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ADP7182 Datasheet

Analog Devices Inc.

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Datasheet

–28 V, −200 mA, Low Noise,
Linear Regulator
Data Sheet ADP7182
Rev. J Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Low noise: 18 μV rms
Power supply rejection ratio (PSRR): 66 dB at 10 kHz at VOUT = −3 V
Positive or negative enable logic
Stable with small 2.2 μF ceramic output capacitor
Input voltage range: −2.7 V to −28 V
Maximum output current: −200 mA
Low dropout voltage: −185 mV at −200 mA load
Initial accuracy: ±1%
Accuracy over line, load, and temperature
+2% maximum/−3% minimum
Low quiescent current, IGND = −650 μA with −200 mA load
Low shutdown current: −2 μA
Adjustable output from −1.22 V to −VIN + VDO
Current-limit and thermal overload protection
6- and 8-lead LFCSP and 5-lead TSOT
Supported by ADIsimPower tool
APPLICATIONS
Regulation to noise sensitive applications
Analog-to-digital converter (ADC) and digital-to-analog
converter (DAC) circuits, precision amplifiers
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
TYPICAL APPLICATION CIRCUITS
GND
EN NC
VIN VOUT
ADP7182
ON
ON
–2V
OFF 0V
2V
V
IN
= –8V V
OUT
= –5V
C
OUT
2.2µF
C
IN
2.2µF
10703-001
Figure 1. ADP7182 with Fixed Output Voltage, VOUT = −5 V
13k
40.2k
GND
EN ADJ
VIN VOUT
ADP7182
ON
ON
–2V
OFF 0V
2V
V
IN
= –8V V
OUT
= –5V
C
OUT
2.2µF
C
IN
2.2µF
10703-002
Figure 2. ADP7182 with Adjustable Output Voltage, VOUT = −5 V
GENERAL DESCRIPTION
The ADP7182 is a CMOS, low dropout (LDO) linear regulator
that operates from −2.7 V to −28 V and provides up to −200 mA
of output current. This high input voltage LDO is ideal for
regulation of high performance analog and mixed signal circuits
operating from −27 V down to −1.2 V rails. Using an advanced
proprietary architecture, it provides high power supply rejection
and low noise, and achieves excellent line and load transient
response with a small 2.2 μF ceramic output capacitor.
The ADP7182 is available in fixed output voltage and an
adjustable version that allows the output voltage to range from
−1.22 V to −VIN + VDO via an external feedback divider.
The following fixed output voltages are available from stock: −5 V
(3 mm × 3 mm LFCSP), −1.8 V, −2.5 V, −3 V, −5 V (TSOT), −1.2 V,
−1.5 V, −2.5 V, −5 V (2 mm × 2 mm LFCSP). Additional voltages
are available by special order.
The ADP7182 regulator output noise is 18 μV rms independent
of the output voltage. The enable logic is capable of interfacing
with positive or negative logic levels for maximum flexibility.
The ADP7182 is available in 5-lead TSOT, 6- and 8-lead LFCSP
packages for a small, low profile footprint.
ADP7182 Data Sheet
Rev. J | Page 2 of 31
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuits ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Input and Output Capacitance, Recommended
Specifications ................................................................................ 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 21
Adjustable Mode Operation ..................................................... 21
Applications Information .............................................................. 22
ADIsimPower Design Tool ....................................................... 22
Capacitor Selection .................................................................... 22
Enable Pin Operation ................................................................ 23
Soft Start ...................................................................................... 23
Noise Reduction of the Adjustable ADP7182 ............................ 24
Current-Limit and Thermal Overload Protection ................. 24
Thermal Considerations ............................................................ 25
PCB Layout Considerations ...................................................... 28
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 31
REVISION HISTORY
3/2017Rev. I to Rev. J
Changes to Specifications Section .................................................. 3
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 31
12/2016Rev. H to Rev. I
Changes to Figure 77 ................................................................................. 21
Moved Theory of Operation/Enable Pin Operation Section.... 23
Changes to Enable Pin Operation Section .................................. 23
11/2016Rev. G to Rev. H
Change to Thermal Considerations Section ............................... 25
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 31
6/2016Rev. F to Rev. G
Changes to Figure 101 .................................................................... 28
3/2016Rev. E to Rev. F
Changes to Figure 62 ...................................................................... 17
9/2014Rev. D to Rev. E
Changes to Features and General Description Sections .............. 1
Changes to Figure 101 .................................................................... 28
Added Table 11 ............................................................................... 29
Changes to Ordering Guide .......................................................... 31
7/2014Rev. C to Rev. D
Added 6-Lead LFCSP (Throughout) ............................................. 1
Added 6-Lead LFCSP Thermal Resistance Parameters............... 5
Added Figure 7, Figure 8, and Table 7 ............................................ 8
Added 6-Lead LFCSP θJA Values to Table 8; Added 6-Lead
LFCSP ΨJB Value to Table 10 ......................................................... 25
Added Figure 92, Figure 93, and Figure 94 ................................. 26
Changes to Thermal Characterization Parameter, ΨJB Section
and Added Figure 99 ...................................................................... 27
Added Figure 101 ........................................................................... 28
Added Figure 104, Outline Dimensions ...................................... 29
Changes to Ordering Guide .......................................................... 30
9/2013Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 28
6/2013Rev. A to Rev. B
Changes to General Description ..................................................... 1
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
5/2013Rev. 0 to Rev. A
Changed Start-Up Time VOUT = −5 V from 450 µs to 550 µs ...... 3
Changes to Figure 9 and Figure 12 .................................................. 8
Changes to Figure 13 ......................................................................... 9
Changes to Figure 19 and Figure 22 ............................................ 10
Changes to Figure 28 ...................................................................... 11
Changes to Figure 31 and Figure 34 ............................................ 12
Changes to Figure 37 and Figure 40 ............................................ 13
Changes to Figure 43 ...................................................................... 14
Added ADIsimPower Design Tool Section ................................. 21
4/2013—Revision 0: Initial Version
Data Sheet ADP7182
Rev. J | Page 3 of 31
SPECIFICATIONS
VIN = (VOUT0.5 V) or −2.7 V (whichever is more negative), EN = VIN, IOUT = −10 mA, CIN = COUT = 2.2 µF, TJ = −40°C to +125°C for
minimum/maximum specifications, TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE
V
IN
2.7
28
V
OPERATING SUPPLY CURRENT IGND IOUT = 0 µA 33 53 µA
IOUT = 10 mA 100 150 µA
IOUT = 200 mA −650 850 µA
SHUTDOWN CURRENT IGND-SD EN = GND −2 µA
EN = GND, VIN = −2.7 V to28 V −8 µA
OUTPUT VOLTAGE ACCURACY
Fixed Output Voltage Accuracy VOUT IOUT = 10 mA, TA = 25°C –1 +1 %
1 mA < I
OUT
< 200 mA, V
IN
= (V
OUT
0.5 V) to 28 V
–3
+2
%
Adjustable Output Voltage
Accuracy
VADJ IOUT = 10 mA 1.208 1.22 1.232 V
1 mA < IOUT < 200 mA, VIN = (VOUT 0.5 V) to 28 V 1.184 1.244 V
LINE REGULATION ∆VOUT/∆VIN VIN = (VOUT0.5 V) to 28 V 0.01 +0.01 %/V
LOAD REGULATION1 ∆VOUT/∆IOUT IOUT = 1 mA to 200 mA 0.001 0.006 %/mA
ADJ INPUT BIAS CURRENT ADJI-BIAS 1 mA < IOUT < 200 mA, VIN = (VOUT 0.5 V) to 28 V 10 nA
DROPOUT VOLTAGE2 VDO IOUT = 10 mA 25 70 mV
IOUT = 50 mA 46 90 mV
IOUT = 200 mA −185 360 mV
START-UP TIME3 tSTART-UP VOUT = −5 V 550 µs
VOUT = −2.8 V 375 µs
CURRENT-LIMIT THRESHOLD4 ILIMIT 230 350 500 mA
THERMAL SHUTDOWN
Thermal Shutdown Threshold
TS
SD
T
J
rising
150
°C
Thermal Shutdown Hysteresis TSSD-HYS 15 °C
EN THRESHOLD
Positive Rise VEN-POS-RISE VOUT = off to on (positive) 1.2 V
Negative Rise VEN-NEG-RISE VOUT = off to on (negative) 2.0 V
Positive Fall VEN-POS-FALL VOUT = on to off (positive) 0.3 V
Negative Fall VEN-NEG-FALL VOUT = on to off (negative) 0.55 V
INPUT VOLTAGE LOCKOUT
Start Threshold VSTART 2.695 2.49 V
Shutdown Threshold VSHUTDOWN 2.34 2.1 V
Hysteresis 150 mV
OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VOUT = −1.5 V, VOUT = −3 V, and
VOUT = −5 V
18 µV rms
10 Hz to 100 kHz, VOUT = −5 V, adjustable mode,
CNR = open, RNR = open, RFB1 = 147 kΩ, RFB2 = 13 kΩ
150 µV rms
10 Hz to 100 kHz, VOUT = −5 V, adjustable mode,
CNR = 100 nF, RNR = 13 kΩ, RFB1 = 147 kΩ, RFB2 = 13 kΩ
33 µV rms
ADP7182 Data Sheet
Rev. J | Page 4 of 31
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY REJECTION RATIO PSRR 1 MHz, VIN = −4.3 V, VOUT = −3 V 45 dB
1 MHz, VIN = −6 V, VOUT = −5 V 32 dB
100 kHz, VIN = 4.3 V, VOUT = −3 V 45 dB
100 kHz, VIN = −6 V, VOUT = −5 V 45 dB
10 kHz, V
IN
= 4.3 V, V
OUT
= −3 V
66
dB
10 kHz, VIN = −6 V, VOUT = −5 V 66 dB
1 MHz, VIN = −16 V, VOUT = −15 V, adjustable mode,
CNR = 100 nF, RNR = 13 kΩ, RFB1 = 13 kΩ, RFB2 = 147 kΩ
45 dB
100 kHz, VIN = −16 V, VOUT = −15 V, adjustable mode,
CNR = 100 nF, RNR = 13 kΩ, RFB1 = 13 kΩ, RFB2 = 147 kΩ
45 dB
10 kHz, VIN = −16 V, VOUT = −15 V, adjustable mode,
CNR = 100 nF, RNR = 13 kΩ, RFB1 = 13 kΩ, RFB2 = 147 kΩ
66 dB
1 Based on an endpoint calculation using −1 mA and −200 mA loads. See Figure 10 for the typical load regulation performance for loads less than 1 mA.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages below −3 V.
3 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of the nominal value.
4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5 V
output voltage is defined as the current that causes the output voltage to drop to 90% of −5 V, or 4.5 V.
INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT AND OUTPUT CAPACITANCE
Minimum Capacitance
1
MIN
T
A
= −40°C to +125°C
1.5
2.2
µF
Capacitor Effective Series Resistance (ESR) RESR TA = −40°C to +125°C 0.001 0.2
1 The minimum input and output capacitance must be greater than 1.5 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Data Sheet ADP7182
Rev. J | Page 5 of 31
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND +0.3 V to 30 V
VOUT to GND 0.3 V to VIN
EN to GND 5 V to VIN
EN to VIN +30 V to 0.3 V
ADJ to GND +0.3 V to VOUT
Storage Temperature Range 65°C to +150°C
Operating Junction Temperature Range 40°C to +125°C
Operating Ambient Temperature Range
40°C to +85°C
Soldering Conditions JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP7182 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that junction temperature (TJ) is within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated.
In applications with moderate power dissipation and low printed
circuit board (PCB) thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The TJ of the device is
dependent on the ambient temperature (TA), the power dissipation
of the device (PD), and the junction-to-ambient thermal resistance
of the package (θJA).
Maximum TJ is calculated from the TA and PD using the formula
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout.
In applications where high maximum power dissipation exists,
close attention to thermal board design is required. The value of
θJA can vary, depending on PCB material, layout, and
environmental conditions. The specified values of θJA are based
on a 4-layer, 4 in. × 3 in. circuit board. See JESD51-7 and
JESD51-9 for detailed information on the board construction. For
additional information, see the AN-617 Application Note,
MicroCSP Wafer Level Chip Scale Package.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information, states
that thermal characterization parameters are not the same as
thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make ΨJB more useful in real-world
applications. Maximum junction temperature is calculated from
the board temperature (TB) and power dissipation using the
formula
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θJC ΨJB Unit
8-Lead LFCSP 50.2 31.7 18.2 °C/W
6-Lead LFCSP 68.9 42.29 44.1 °C/W
5-Lead TSOT 170 Not applicable 43 °C/W
ESD CAUTION
ADP7182 Data Sheet
Rev. J | Page 6 of 31
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADP7182
TOP VIEW
(Not to Scale)
1
GND
2
VIN
3
EN
5
VOUT
4
NC
NOTES
1. NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
10703-003
Figure 3. 5-Lead TSOT Pin Configuration, Fixed Output Voltage
ADP7182
TOP VIEW
(Not to Scale)
1
GND
2
VIN
3
EN
5
VOUT
4
ADJ
10703-004
Figure 4. 5-Lead TSOT Pin Configuration, Adjustable Output Voltage
Table 5. 5-Lead TSOT Pin Function Descriptions
TSOT Pin No.
Fixed Output Voltage Adjustable Output Voltage Mnemonic Description
1 1 GND Ground.
2 2 VIN
Regulator Input Supply. Bypass VIN to GND with a 2.2 μF or greater
capacitor.
3 3 EN
Drive EN 2 V above or below ground to enable the regulator, or
drive EN to ground to turn off the regulator. For automatic startup,
connect EN to VIN.
4 Not applicable NC No Connect. Do not connect to this pin.
Not applicable 4 ADJ Adjustable Input. An external resistor divider sets the output voltage.
5 5 VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 2.2 μF or
greater capacitor.
Data Sheet ADP7182
Rev. J | Page 7 of 31
10703-005
3NC
4EN
1VOUT
2VOUT
6GND
5NC
8 VIN
7 VIN
ADP7182
TOP VIEW
(Not to Scale)
EXPOSED PAD
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO VIN
INSIDE THE PACKAGE. THE EXPOSED PAD MUST BE CONNECTED TO THE
VIN PLANE ON THE BOARD FOR PROPER OPERATION. BECAUSE THIS IS A
NEGATIVE VOLTAGE REGULATOR, VIN IS THE MOST NEGATIVE POTENTIAL
IN THE CIRCUIT.
Figure 5. 8-Lead LFCSP Pin Configuration, Fixed Output Voltage
10703-006
3ADJ
4EN
1VOUT
2VOUT
6GND
5NC
8 VIN
7 VIN
ADP7182
TOP VIEW
(Not to Scale)
EXPOSED PAD
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO VIN
INSIDE THE PACKAGE. THE EXPOSED PAD MUST BE CONNECTED TO THE
VIN PLANE ON THE BOARD FOR PROPER OPERATION. BECAUSE THIS IS A
NEGATIVE VOLTAGE REGULATOR, VIN IS THE MOST NEGATIVE POTENTIAL
IN THE CIRCUIT.
Figure 6. 8-Lead LFCSP Pin Configuration, Adjustable Output Voltage
Table 6. 8-Lead LFCSP Pin Function Descriptions
LFCSP Pin No.
Fixed Output Voltage Adjustable Output Voltage Mnemonic Description
1, 2 1, 2 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 2.2 µF or
greater capacitor.
Not applicable 3 ADJ Adjustable Input. An external resistor divider sets the output voltage.
3 Not applicable NC No Connect. Do not connect to this pin.
4
4
EN
Drive EN 2 V above or below ground to enable the regulator, or drive
EN to ground to turn off the regulator. For automatic startup,
connect EN to VIN.
5 5 NC No Connect. Do not connect to this pin.
6 6 GND Ground.
7, 8 7, 8 VIN Regulator Input Supply. Bypass VIN to GND with a 2.2 µF or greater
capacitor.
9 9 EPAD Exposed pad. The exposed pad on the bottom of the LFCSP package
enhances thermal performance and is electrically connected to VIN
inside the package. The exposed pad must be connected to the VIN
plane on the board for proper operation. Because this is a negative
voltage regulator, VIN is the most negative potential in the circuit.
ADP7182 Data Sheet
Rev. J | Page 8 of 31
3EN
1VOUT
2NC
4NC
6 VIN
5GND
10703-107
ADP7182
TOP VIEW
(Not to Scale)
EXPOSED PAD
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO VIN
INSIDE THE PACKAGE. THE EXPOSED PAD MUST BE CONNECTED TO THE
VIN PLANE ON THE BOARD FOR PROPER OPERATION. BECAUSE THIS IS A
NEGATIVE VOLTAGE REGULATOR, VIN IS THE MOST NEGATIVE POTENTIAL
IN THE CIRCUIT.
3EN
1VOUT
2ADJ
4NC
6 VIN
5GND
10703-106
ADP7182
TOP VIEW
(Not to Scale)
EXPOSED PAD
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO VIN
INSIDE THE PACKAGE. THE EXPOSED PAD MUST BE CONNECTED TO THE
VIN PLANE ON THE BOARD FOR PROPER OPERATION. BECAUSE THIS IS A
NEGATIVE VOLTAGE REGULATOR, VIN IS THE MOST NEGATIVE POTENTIAL
IN THE CIRCUIT.
Figure 7. 6-Lead LFCSP Pin Configuration, Fixed Output Voltage Figure 8. 6-Lead LFCSP Pin Configuration, Adjustable Output Voltage
Table 7. 6-Lead LFCSP Pin Function Descriptions
LFCSP Pin No.
Mnemonic Description
Fixed Output Voltage Adjustable Output Voltage
1 1 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 2.2 µF or
greater capacitor.
Not applicable 2 ADJ Adjustable Input. An external resistor divider sets the output voltage.
3 3 EN
Drive EN 2 V above or below ground to enable the regulator, or drive
EN to ground to turn off the regulator. For automatic startup,
connect EN to VIN.
2, 4 4 NC No Connect. Do not connect to this pin.
5 5 GND Ground.
6 6 VIN Regulator Input Supply. Bypass VIN to GND with a 2.2 µF or greater
capacitor.
7 7 EPAD Exposed pad. The exposed pad on the bottom of the LFCSP package
enhances thermal performance and is electrically connected to VIN
inside the package. The exposed pad must be connected to the VIN
plane on the board for proper operation. Because this is a negative
voltage regulator, VIN is the most negative potential in the circuit.
Data Sheet ADP7182
Rev. J | Page 9 of 31
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = −3.5 V, VOUT = −3 V, IOUT = −10 mA, CIN = COUT = 2.2 µF, TA = 25°C, unless otherwise noted.
–2.970
–3.020
–3.015
–3.010
–3.005
–3.000
–2.995
–2.990
–2.985
–2.980
–2.975
–40 –5 25 85 125
VOUT (V)
JUNCTION TEMPERATURE (°C)
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
10703-007
Figure 9. Output Voltage (VOUT) vs. Junction Temperature (TJ)
–2.95
–3.05
–3.04
–3.03
–3.02
–3.01
–3.00
–2.99
–2.98
–2.97
–2.96
–200 –150 –50–100 050
V
OUT
(V)
I
LOAD
(mA)
10703-008
Figure 10. Output Voltage (VOUT) vs. Load Current (ILOAD)
–2.90
–2.95
–3.00
–3.05
–3.10
–30 –20 –10–25 –15 –5 0
V
OUT
(V)
V
IN
(V)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-009
Figure 11. Output Voltage (VOUT) vs. Input Voltage (VIN)
0
–800
–700
–600
–500
–400
–300
–200
–100
–40 –5 25 85 125
GROUND CURRENT (µA)
JUNCTION TEMPERATURE (°C)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-010
Figure 12. Ground Current vs. Junction Temperature (TJ)
–250 –200 –150 –50–100 050
GROUND CURRENT (µA)
I
LOAD
(mA)
0
–800
–700
–600
–500
–400
–300
–200
–100
10703-011
Figure 13. Ground Current vs. Load Current (ILOAD)
0
–800
–700
–600
–500
–400
–300
–200
–100
–30 –20 –10–25 –15 –5 0
GROUND CURRENT (µA)
V
IN
(V)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-012
Figure 14. Ground Current vs. Input Voltage (VIN)
ADP7182 Data Sheet
Rev. J | Page 10 of 31
0
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
–50 –25 0 25 50 75 100 125
SHUTDOWN CURRENT (µA)
TEMPERATUREC)
V
IN
= –2.7V
V
IN
= –3.0V
V
IN
= –4.0V
V
IN
= –5.0V
V
IN
= –8.0V
V
IN
= –28.0V
10703-013
Figure 15. Shutdown Current vs. Temperature at Various Input Voltages
0
–200
–180
–160
–140
–120
–100
–80
–60
–40
–20
1 10 100 1000
DROPOUT VOLTAGE (mV)
I
LOAD
(mA)
10703-014
Figure 16. Dropout Voltage vs. Load Current (ILOAD)
2.55
–3.05
–3.00
–2.95
–2.90
–2.85
–2.80
–2.75
–2.70
–2.65
–2.60
–3.4 –3.2 –3.0 –2.8
V
OUT
(V)
V
IN
(V)
I
LOAD
= –5mA
I
LOAD
= –10mA
I
LOAD
= –25mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-015
Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout
0
–1200
–1000
–800
–600
–400
–200
–3.4 –3.2 –3.0 –2.8
GROUND CURRENT (µA)
V
IN
(V)
I
LOAD
= –5mA
I
LOAD
= –10mA
I
LOAD
= –25mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-016
Figure 18. Ground Current vs. Input Voltage (VIN) in Dropout
4.90
–5.10
–5.08
–5.06
–5.04
–5.02
–5.00
–4.98
–4.96
–4.94
–4.92
–40 –5 25 85 125
V
OUT
(V)
JUNCTION TEMPERATURE (°C)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-017
Figure 19. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = −5 V
5.000
–5.005
–5.010
–5.015
–5.020
–5.025
–5.030
–5.035
–5.040
–5.045
–5.050
–200 –150 –100 –50 0
V
OUT
(V)
I
LOAD
(mA)
10703-018
Figure 20. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −5 V
Data Sheet ADP7182
Rev. J | Page 11 of 31
4.97
–4.98
–4.99
–5.00
–5.01
–5.02
–5.03
–30 –20 –10–25 –15 –5 0
V
OUT
(V)
V
IN
(V)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-019
Figure 21. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −5 V
4052585125
JUNCTION TEMPERATURE (°C)
0
–800
–700
–600
–500
–400
–300
–200
–100
GROUND CURRENT (µA)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-020
Figure 22. Ground Current vs. Junction Temperature (TJ), VOUT = −5 V
0
–800
–700
–600
–500
–400
–300
–200
–100
–200 –150 –100 –50 0
GROUND CURRENT (µA)
I
LOAD
(mA)
10703-021
Figure 23. Ground Current vs. Load Current (ILOAD), VOUT = −5 V
–30 –20 –10–25 –15 –5 0
V
IN
(V)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
0
–800
–700
–600
–500
–400
–300
–200
–100
GROUND CURRENT (µA)
10703-022
Figure 24. Ground Current vs. Input Voltage (VIN), VOUT = −5 V
0
–160
–140
–120
–100
–80
–60
–40
–20
1 10 100 1000
DROPOUT VOLTAGE (mV)
I
LOAD
(mA)
10703-023
Figure 25. Dropout Voltage vs. Load Current (ILOAD), VOUT = −5 V
4.60
–4.65
–4.70
–4.75
–4.80
–4.85
–4.90
–4.95
–5.05
–5.00
–5.4 –5.2 –5.0 –4.8
V
OUT
(V)
V
IN
(V)
I
LOAD
= –5mA
I
LOAD
= –10mA
I
LOAD
= –25mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-024
Figure 26. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = −5 V
ADP7182 Data Sheet
Rev. J | Page 12 of 31
0
–200
–400
–600
–800
–1000
–1200
–1600
–1400
–5.4 –5.2 –5.0 –4.8
GROUND CURRENT (µA)
V
IN
(V)
I
LOAD
= –5mA
I
LOAD
= –10mA
I
LOAD
= –25mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-025
Figure 27. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = −5 V
1.770
–1.775
–1.780
–1.785
–1.790
–1.795
–1.800
–1.805
–1.810
–40 –5 25 85 125
VOUT (V)
JUNCTION TEMPERATURE (°C)
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
10703-026
Figure 28. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = −1.8 V
1.790
–1.795
–1.800
–1.805
–1.810
–200 –150 –100 –50 0
V
OUT
(V)
I
LOAD
(mA)
10703-027
Figure 29. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −1.8 V
1.780
–1.785
–1.790
–1.795
–1.800
–1.805
–1.810
–30 –25 –20 –15 –10 –5 0
V
OUT
(V)
V
IN
(V)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-028
Figure 30. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −1.8 V
0
–100
–200
–300
–400
–500
–600
–700
–40 –5 25 85 125
GROUND CURRENT (µA)
JUNCTION TEMPERATURE (°C)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-029
Figure 31. Ground Current vs. Junction Temperature (TJ), VOUT = −1.8 V
0
–100
–300
–500
–200
–400
–600
–700
–200 –150 –100 –50 0
GROUND CURRENT (µA)
I
LOAD
(mA)
10703-030
Figure 32. Ground Current vs. Load Current (ILOAD), VOUT = −1.8 V
Data Sheet ADP7182
Rev. J | Page 13 of 31
0
–700
–600
–500
–400
–300
–200
–100
–30 –25 –20 –15 –10 –5 0
GROUND CURRENT (µA)
V
IN
(V)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-031
Figure 33. Ground Current vs. Input Voltage (VIN), VOUT = −1.8 V
1.20
–1.21
–1.22
–1.23
–1.24
–1.25
–40 –5 25 85 125
V
OUT
(V)
JUNCTION TEMPERATURE (°C)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-032
Figure 34. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = −1.22 V
1.20
–1.25
–1.24
–1.23
–1.22
–1.21
–200 –150 –100 –50 0
V
OUT
(V)
I
LOAD
(mA)
10703-033
Figure 35. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −1.22 V
1.20
–1.22
–1.21
–1.23
–1.24
–1.25
–30 –25 –20 –15 –10 –5 0
V
OUT
(V)
V
IN
(V)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-034
Figure 36. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −1.22 V
0
–700
–600
–500
–400
–300
–200
–100
–40 –5 25 85 125
GROUND CURRENTA)
JUNCTION TEMPERATURE (°C)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-035
Figure 37. Ground Current vs. Junction Temperature (TJ), VOUT = −1.22 V
0
–700
–400
–500
–600
–300
–200
–100
–200 –150 –100 –50 0
GROUND CURRENT (µA)
I
LOAD
(mA)
10703-036
Figure 38. Ground Current vs. Load Current (ILOAD), VOUT = −1.22 V
ADP7182 Data Sheet
Rev. J | Page 14 of 31
0
–700
–600
–500
–400
–300
–200
–100
–30 –25 –20 –15 –10 –5 0
GROUND CURRENT (µA)
V
IN
(V)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-037
Figure 39. Ground Current vs. Input Voltage (VIN), VOUT = −1.22 V
14.80
–15.30
–15.25
–15.20
–15.15
–15.10
–15.05
–15.00
–14.90
–14.95
–14.85
–40 –5 25 85 125
V
OUT
(V)
JUNCTION TEMPERATURE (°C)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-038
Figure 40. Output Voltage (VOUT) vs. Junction Temperature (TJ),
Adjustable Output Voltage, VOUT = −15 V
14.80
–15.30
–15.25
–15.20
–15.15
–15.10
–15.05
–15.00
–14.90
–14.95
–14.85
V
OUT
(V)
I
LOAD
(mA)
–200 –150 –100 –50 0
10703-039
Figure 41. Output Voltage (VOUT) vs. Load Current (ILOAD),
Adjustable Output Voltage, VOUT = −15 V
14.80
–15.30
–15.25
–15.20
–15.15
–15.10
–15.05
–15.00
–14.90
–14.95
–14.85
–30 –25 –20 –15
V
OUT
(V)
V
IN
(V)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-040
Figure 42. Output Voltage (VOUT) vs. Input Voltage (VIN),
Adjustable Output Voltage, VOUT = −15 V
0
–800
–700
–600
–500
–400
–300
–200
–100
–40 –5 25 85 125
GROUND CURRENT (µA)
JUNCTION TEMPERATURE (°C)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-041
Figure 43. Ground Current vs. Junction Temperature (TJ),
Adjustable Output Voltage, VOUT = −15 V
GROUND CURRENT (µA)
I
LOAD
(mA)
–200 –150 –100 –50 0
0
–800
–700
–600
–500
–400
–300
–200
–100
10703-042
Figure 44. Ground Current vs. Load Current (ILOAD),
Adjustable Output Voltage, VOUT = −15 V
Data Sheet ADP7182
Rev. J | Page 15 of 31
0
–800
–700
–600
–500
–400
–300
–200
–100
–30 –25 –20 –15
GROUND CURRENTA)
V
IN
(V)
I
LOAD
= –100µA
I
LOAD
= –1mA
I
LOAD
= –10mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-043
Figure 45. Ground Current vs. Input Voltage (VIN),
Adjustable Output Voltage, VOUT = −15 V
0
–140
–120
–100
–80
–60
–40
–20
1101001000
DROPOUT VOLTAGE (mV)
I
LOAD
(mA)
10703-044
Figure 46. Dropout Voltage vs. Load Current (ILOAD),
Adjustable Output Voltage, VOUT = −15 V
14.60
–14.65
–14.70
–14.75
–14.80
–14.85
–14.90
–14.95
–15.00
–15.05
–15.10
–15.0 –14.5–14.6–14.7–14.8–14.9
V
OUT
(V)
V
IN
(V)
I
LOAD
= –10mA
I
LOAD
= –10mA
I
LOAD
= –25mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-045
Figure 47. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,
Adjustable Output Voltage, VOUT = −15 V
0
–1600
–1400
–1200
–1000
–800
–600
–400
–200
–15.0 –14.0–14.2–14.4–14.6–14.8
GROUND CURRENTA)
V
IN
(V)
I
LOAD
= –5mA
I
LOAD
= –10mA
I
LOAD
= –25mA
I
LOAD
= –50mA
I
LOAD
= –100mA
I
LOAD
= –200mA
10703-046
Figure 48. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = −15 V
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
I
LOAD
= –200mA
I
LOAD
= –100mA
I
LOAD
= –10mA
I
LOAD
= –1mA
10703-047
Figure 49. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −1.22 V vs. Different Load Currents (ILOAD), VIN = −2.7 V
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
I
LOAD
= –200mA
I
LOAD
= –100mA
I
LOAD
= –10mA
I
LOAD
= –1mA
10703-048
Figure 50. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −1.22 V vs. Different Load Currents (ILOAD), VIN = −5.7 V
ADP7182 Data Sheet
Rev. J | Page 16 of 31
0
–80
–70
–60
–50
–40
–30
–20
–10
1.0 5.04.54.03.53.02.52.01.5
PSRR (dB)
HEADROOM VOLTAGE (V)
FREQUENCY = 100Hz
FREQUENCY = 1kHz
FREQUENCY = 10kHz
FREQUENCY = 100kHz
FREQUENCY = 1MHz
FREQUENCY = 10MHz
10703-049
Figure 51. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = −1.22 V, Load Current (ILOAD) = 200 mA
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
I
LOAD
= –200mA
I
LOAD
= –100mA
I
LOAD
= –10mA
I
LOAD
= –1mA
10703-050
Figure 52. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −1.8 V vs. Different Load Currents (ILOAD), VIN = −2.8 V
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
I
LOAD
= –200mA
I
LOAD
= –100mA
I
LOAD
= –10mA
I
LOAD
= –1mA
10703-051
Figure 53. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −1.8 V vs. Different Load Currents (ILOAD), VIN = −5.5 V
0
–80
–70
–60
–50
–40
–30
–20
–10
1.0 4.03.53.02.52.01.5
PSRR (dB)
HEADROOM VOLTAGE (V)
FREQUENCY = 100Hz
FREQUENCY = 1kHz
FREQUENCY = 10kHz
FREQUENCY = 100kHz
FREQUENCY = 1MHz
FREQUENCY = 10MHz
10703-052
Figure 54. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = −1.8 V, Load Current (ILOAD) = 200 mA
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
I
LOAD
= –200mA
I
LOAD
= –100mA
I
LOAD
= –10mA
I
LOAD
= –1mA
10703-053
Figure 55. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −3 V vs. Different Load Currents (ILOAD), VIN = −4.0 V
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
I
LOAD
= –200mA
I
LOAD
= –100mA
I
LOAD
= –10mA
I
LOAD
= –1mA
10703-054
Figure 56. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −3 V vs. Different Load Currents (ILOAD), VIN = −5.5 V
Data Sheet ADP7182
Rev. J | Page 17 of 31
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
04.03.53.02.52.01.51.00.5
PSRR (dB)
HEADROOM VOLTAGE (V)
FREQUENCY = 100Hz
FREQUENCY = 1kHz
FREQUENCY = 10kHz
FREQUENCY = 100kHz
FREQUENCY = 1MHz
FREQUENCY = 10MHz
10703-055
Figure 57. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = −3 V, Load Current (ILOAD) = −200 mA
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
ILOAD = –200mA
ILOAD = –100mA
ILOAD = –10mA
ILOAD = –1mA
10703-056
Figure 58. Power Supply Rejection Ratio (PSRR) vs. Frequency,
Adjustable Output Voltage, VOUT = −15 V vs. Different Load Currents (ILOAD),
VIN = −15.5 V with Noise Reduction Network
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
I
LOAD
= –200mA
I
LOAD
= –100mA
I
LOAD
= –10mA
I
LOAD
= –1mA
10703-057
Figure 59. Power Supply Rejection Ratio (PSRR) vs. Frequency,
Adjustable Output Voltage, VOUT = −15 V vs. Different Load Currents (ILOAD),
VIN = −16.5 V with Noise Reduction Network
0
–80
–70
–60
–50
–40
–30
–20
–10
02.001.751.501.251.000.750.500.25
PSRR (dB)
HEADROOM VOLTAGE (V)
FREQUENCY = 100Hz
FREQUENCY = 1kHz
FREQUENCY = 10kHz
FREQUENCY = 100kHz
FREQUENCY = 1MHz
FREQUENCY = 10MHz
10703-058
Figure 60. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
Adjustable Output Voltage, VOUT = −15 V with Noise Reduction Network,
Load Current (ILOAD) = −200 mA
1000
1
10
100
0.001 0.01 0.1 1 10 100 1000
NOISE (µV rms)
LOAD CURRENT (mA)
V
OUT
= –5V
V
OUT
= –1.8V
V
OUT
= –15V ADJ NR
V
OUT
= –3V
V
OUT
= –1.2V
V
OUT
= –15V ADJ
10703-059
Figure 61. RMS Noise vs. Load Current (ILOAD), Various Output Voltages
100k
1
10
100
1k
10k
1 100M10M1M100k10k1k10010
NOISE SPECTRAL DENSITY (nV Hz)
FREQUENCY (Hz)
10703-060
V
OUT
= –5V
V
OUT
= –1.8V
V
OUT
= –15V ADJ NR
V
OUT
= –3V
V
OUT
= –1.2V
V
OUT
= –15V ADJ
Figure 62. Noise Spectral Density, Various Output Voltages
ADP7182 Data Sheet
Rev. J | Page 18 of 31
CH1 500mV
BW
CH2 2mV
BW
M10µs A CH3 2.52V
T 10.00%
1
2
T
10703-061
V
OUT
V
IN
Figure 63. Line Transient Response, 500 mV Step, VOUT = −1.22 V, ILOAD = −200 mA
CH1 500mV
BW
CH2 1mV
BW
M10µs A CH3 2.52V
T 10.00%
1
2
T
10703-062
V
OUT
V
IN
Figure 64. Line Transient Response, 500 mV Step, VOUT = −1.22 V, ILOAD = −10 mA
CH1 500mV
BW
CH2 5mV
BW
M2µs A CH3 1.60V
T 10.00%
1
2
T
10703-063
V
OUT
V
IN
Figure 65. Line Transient Response, 500 mV Step, VOUT = −1.8 V, ILOAD = −200 mA
CH1 500mV
BW
CH2 5mV
BW
M2µs A CH3 1.60V
T 10.00%
1
2
T
10703-064
V
OUT
V
IN
Figure 66. Line Transient Response, 500 mV Step, VOUT = −1.8 V, ILOAD = −10 mA
CH1 1V
BW
CH2 5mV
BW
M4µs A CH3 1.60V
T 10.00%
1
2
T
10703-065
V
OUT
V
IN
Figure 67. Line Transient Response, 500 mV Step, VOUT = −3 V, ILOAD = −200 mA
CH1 1V
BW
CH2 5mV
BW
M4µs A CH3 1.60V
T 10.00%
1
2
T
10703-066
V
OUT
V
IN
Figure 68. Line Transient Response, 500 mV Step, VOUT = −3 V, ILOAD = −10 mA
Data Sheet ADP7182
Rev. J | Page 19 of 31
CH1 1V
BW
CH2 10mV
BW
M2µs A CH3 2.02V
T 10.00%
1
2
T
10703-067
V
OUT
V
IN
Figure 69. Line Transient Response, 500 mV Step, VOUT = −5 V, ILOAD = 200 mA
CH1 1V
BW
CH2 5mV
BW
M2µs A CH3 2.02V
T 10.00%
1
2
T
10703-068
V
OUT
V
IN
Figure 70. Line Transient Response, 500 mV Step, VOUT = −5 V, ILOAD = 10 mA
CH1 1V
BW
CH2 2mV
BW
M4µs A CH3 2.52V
T 10.00%
1
2
T
10703-069
V
OUT
V
IN
Figure 71. Line Transient Response, 500 mV Step, VOUT = −15 V,
Noise Reduction Network, ILOAD = 200 mA
CH1 1V
BW
CH2 2mV
BW
M10µs A CH3 2.52V
T 10.00%
1
2
T
10703-070
V
OUT
V
IN
Figure 72. Line Transient Response, 500 mV Step, VOUT = −15 V,
Noise Reduction Network, ILOAD = 10 mA
CH1 100mA
BW
CH2 50mV
BW
M40µs A CH1 –122mA
T 10.40%
1
2
T
10703-071
V
OUT
LOAD CURRENT
Figure 73. Load Transient Response, VOUT = −1.22 V, ILOAD = 1 mA to 200 mA,
Load Step = 1 A/µs
CH1 100mA
BW
CH2 50mV
BW
M40µs A CH1 –122mA
T 10.60%
1
2
T
10703-072
V
OUT
LOAD CURRENT
Figure 74. Load Transient Response, VOUT = −3 V, ILOAD = 1 mA to 200 mA,
Load Step = 1 A/µs
ADP7182 Data Sheet
Rev. J | Page 20 of 31
CH1 100mA
BW
CH2 50mV
BW
M10µs A CH1 –122mA
T 10.00%
1
2
T
10703-073
V
OUT
LOAD CURRENT
Figure 75. Load Transient Response, VOUT = −5 V, ILOAD = 1 mA to 200 mA,
Load Step = 1 A/µs
CH1 100mA BWCH2 50mV BWM40µs A CH1 –122mA
T 10.00%
1
2
T
10703-074
VOUT
LOAD CURRENT
Figure 76. Load Transient Response, VOUT = −15 V, ILOAD = −1 mA to 200 mA,
Load Step = 1 A/µs, Noise Reduction Network
Data Sheet ADP7182
Rev. J | Page 21 of 31
THEORY OF OPERATION
The ADP7182 is a low quiescent current, LDO linear regulator
that operates from −2.7 V to −28 V and can provide up to −200 mA
of output current. Drawing a low −650 μA of quiescent current
(typical) at full load makes the ADP7182 ideal for battery-powered
portable equipment. Maximum shutdown current consumption
is −8 μA at room temperature.
Optimized for use with small 2.2 μF ceramic capacitors, the
ADP7182 provides excellent transient performance.
VOUT
GND
EN
VIN
REFERENCE
SHUTDOWN
SHORT
CIRCUIT
THERMAL
PROTECT
VREG
10703-075
Figure 77. Fixed Output Voltage Internal Block Diagram
VOUT
ADJ
GND
EN
VIN
–1.22V
REFERENCE
SHUTDOWN
SHORT
CIRCUIT
THERMAL
PROTECT
VREG
10703-076
Figure 78. Adjustable Output Voltage Internal Block Diagram
Internally, the ADP7182 consists of a reference, an error amplifier,
a feedback voltage divider, and an NMOS pass transistor. Output
current is delivered via the NMOS pass transistor, which is
controlled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is more positive
than the reference voltage, the gate of the NMOS transistor is
pulled toward GND, allowing more current to pass and increasing
the output voltage. If the feedback voltage is more negative than
the reference voltage, the gate of the NMOS transistor is pulled
toward −VIN, allowing less current to pass and decreasing the
output voltage.
The ESD protection devices are shown in the block diagram as
Zener diodes (see Figure 77 and Figure 78).
ADJUSTABLE MODE OPERATION
The ADP7182 is available in a fixed output voltage and an
adjustable mode version with an output voltage that can be set
to between −1.22 V and −27 V by an external voltage divider. The
output voltage can be set according to
−VOUT = −1.22 V (1 + RFB1/RFB2)
RFB2 must be less than 120 kΩ to minimize the output voltage errors
due to the leakage current of the ADJ pin. The error voltage caused
by the ADJ pin leakage current is the parallel combination of RFB1
and RFB2 times the ADJ pin leakage current.
For example, when RFB1 = RFB2 = 120 kΩ, the output voltage is
−2.44 V and the error due to the typical ADJ pin leakage current
(10 nA) is 60 kΩ times 10 nA, or 6 mV. This example results in
an output voltage error of 0.245%.
The addition of a small capacitor (~100 pF) in parallel with
RFB1 can improve the stability of the ADP7182. Larger values of
capacitance also reduce the noise and improve PSRR (see the
Noise Reduction of the Adjustable section).
R
FB2
120k
R
FB1
120k
GND
EN ADJ
VIN VOUT
ADP7182
ON
ON
–2V
OFF 0V
2V
V
IN
= –3V V
OUT
= –2.44V
C
OUT
2.2µF
C
IN
2.2µF
10703-077
Figure 79. Setting Adjustable Output Voltage
ADP7182 Data Sheet
Rev. J | Page 22 of 31
APPLICATIONS INFORMATION
ADIsimPower DESIGN TOOL
The ADP7182 is supported by the ADIsimPower™ design tool set.
ADIsimPower is a collection of tools that produce complete power
designs optimized for a specific design goal. The tools enable
the user to generate a full schematic, bill of materials, and calculate
performance in minutes. ADIsimPower can optimize designs for
cost, area, efficiency, and devices count taking into consideration
the operating conditions and limitations of the IC and all real
external components. For more information about, and to obtain
ADIsimPower design tools, visit www.analog.com/ADIsimPower.
CAPACITOR SELECTION
Output Capacitor
The ADP7182 is designed for operation with small space-saving
ceramic capacitors; however, it functions with most commonly
used capacitors as long as care is taken with regard to the ESR
value. The ESR of the output capacitor affects the stability of the
LDO control loop. A minimum of 2.2 µF capacitance with an
ESR of 0.2 Ω or less is recommended to ensure the stability of
the ADP7182. Transient response to changes in load current is
also affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADP7182
to large changes in load current. Figure 80 shows the transient
responses for an output capacitance value of 2.2 µF.
CH1 100mA BWCH2 50mV BWM40µs A CH1 –122mA
T 10.60%
1
2
T
10703-078
V
OUT
LOAD CURRENT
Figure 80. Output Transient Response, COUT = 2.2 µF
Input Bypass Capacitor
Connecting a 2.2 µF capacitor from VIN to GND reduces the
circuit sensitivity to PCB layout, especially when long input
traces or high source impedance are encountered. When more
than 2.2 µF of output capacitance is required, increase the input
capacitance to match it.
Input and Output Capacitor Properties
As long as they meet the minimum capacitance and maximum
ESR requirements, any good quality ceramic capacitors can be
used with the ADP7182. Ceramic capacitors are manufactured
with a variety of dielectrics, each with different behavior over
temperature and applied voltage.
Capacitors must have a dielectric adequate to ensure the minimum
capacitance over the necessary temperature range and dc bias
conditions. X5R or X7R dielectrics with a voltage rating of 25 V
or 50 V are recommended. Due to their poor temperature and dc
bias characteristics, Y5V and Z5U dielectrics are not
recommended.
Figure 81 depicts the capacitance vs. voltage bias characteristics
of an 0805, 2.2 µF, 25 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is ~ ±15% over the 40°C to +85°C temperature
range and is not a function of package or voltage rating.
2.5
0
0.5
1.0
1.5
2.0
0 5 10 15 20 25 30
CAPACITANCE (µF)
DC BIAS (V)
10703-079
Figure 81. Capacitance vs. DC Bias Characteristics
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance,
and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage, which
is −3 V for this example.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is 15% for an X5R dielectric. The tolerance
of the capacitor (TOL) is 10%, and the CBIAS is 2.08 µF at a 3 V bias,
as shown in Figure 81.
Substituting these values in Equation 1 yields
CEFF = 2.08 μF × (1 − 0.15) × (1 − 0.1) = 1.59 µF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage of −3 V.
To guarantee the performance of the ADP7182, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Data Sheet ADP7182
Rev. J | Page 23 of 31
ENABLE PIN OPERATION
The ADP7182 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. When EN is at ±2 V with
respect to GND, VOUT turns on, and when EN is at 0 V, VOUT
turns off. For automatic startup, EN can be connected to VIN.
When the device is disabled, a ~220 kΩ resistor connects to the
VOUT pin, which pulls the VOUT pin up to GND.
The ADP7182 provides a dual polarity enable pin (EN) that turns
on the LDO when |VEN| 2 V. The enable voltage can be positive or
negative with respect to ground.
0
–2.0
–1.5
–1.0
–0.5
–2.0 –1.5 –1.0 –0.5 00.5 1.0 1.5
V
OUT
(V)
ENABLE VOLTAGE (V)
V
OUT
WITH RISING V
EN
V
OUT
WITH FALLING V
EN
10703-080
Figure 82. Typical EN Pin Operation
Figure 82 shows the typical hysteresis of the EN pin. This prevents
on/off oscillations that can occur due to noise on the EN pin as
it passes through the threshold points.
Figure 83 shows typical EN thresholds when the input voltage
varies from −2.7 V to 28 V.
1.0
–2.0
–1.5
–1.0
–0.5
0
0.5
–30 –26 –22 –18 –14 –10 –6 –2
ENABLE THRESHOLD (V)
INPUT VOLTAGE (V)
ENABLE+
DISABLE+
ENABLE
DISABLE–
10703-081
Figure 83. Typical EN Pin Thresholds vs. Input Voltage
Figure 84 and Figure 85 show the start-up behavior for a 5 V
output with positive and negative going enable signals.
CH1 500mV
BW
CH2 500mV
BW
M40µs A CH1 590mV
T 10.20%
1
2
T
10703-082
EN
V
OUT
Figure 84. Typical Start-Up Behavior, Positive Going Enable
CH1 500mV
BW
CH2 500mV
BW
M40µs A CH1 –580mV
T 10.20%
1
2
T
10703-083
EN
V
OUT
Figure 85. Typical Start-Up Behavior, Negative Going Enable
SOFT START
The ADP7182 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for the 5 V option
is approximately 450 µs from the time the EN active threshold is
crossed to when the output reaches 90% of the final value. As
shown in Figure 86, the start-up time is dependent on the output
voltage setting.
2
–6
–5
–4
–3
–2
–1
0
1
01000900800700600500400300200100
OUTPUT VOLTAGES (V)
TIME (µs)
V
EN
V
OUT
= –1.22V
V
OUT
= –3V
V
OUT
= –5V
10703-084
Figure 86. Typical Start-Up Behavior, Different Output Voltages
ADP7182 Data Sheet
Rev. J | Page 24 of 31
NOISE REDUCTION OF THE ADJUSTABLE ADP7182
The ultralow output noise of the fixed output ADP7182 is achieved
by keeping the LDO error amplifier in unity gain and setting the
reference voltage equal to the output voltage. This architecture does
not work for an adjustable output voltage LDO. The adjustable
output ADP7182 uses the more conventional architecture where
the reference voltage is fixed and the error amplifier gain is a function
of the output voltage. The disadvantage of the conventional LDO
architecture is that the output voltage noise is proportional to
the output voltage.
The adjustable LDO circuit can be modified slightly to reduce
the output voltage noise to levels close to that of the fixed output of
the ADP7182. The circuit shown in Figure 87 adds two additional
components to the output voltage setting resistor divider. CNR
and RNR are added in parallel with RFB1 to reduce the ac gain of
the error amplifier. RNR is chosen to be nearly equal to RFB2; this
limits the ac gain of the error amplifier to approximately 6 dB.
The actual gain is the parallel combination of RNR and RFB1 divided
by RFB2. This resistance ensures that the error amplifier always
operates at greater than unity gain.
CNR is chosen by setting the reactance of CNR equal to RFB1 RNR
at a frequency between 10 Hz and 100 Hz. This capacitance sets
the frequency where the ac gain of the error amplifier is 3 dB down
from the dc gain.
R
FB2
13kΩ
R
FB1
147kΩ
GND
EN ADJ
VIN VOUT
ADP7182
ON
ON
–2V
OFF 0V
2V
V
IN
= –16V V
OUT
= –15V
C
OUT
2.2µF C
NR
100nF
C
IN
2.2µF
R
NR
13kΩ
10703-085
Figure 87. Noise Reduction Modification to Adjustable LDO
The noise of the LDO is approximately the noise of the fixed output
LDO (typically 18 µV rms) times RFB2, divided by the parallel
combination of RNR and RFB1. Based on the component values
shown in Figure 87, the ADP7182 has the following
characteristics:
DC gain of 12.3 (21.8 dB)
3 dB roll-off frequency of 10.8 Hz
High frequency ac gain of 1.92 (5.67 dB)
Noise reduction factor of 6.41 (16.13 dB)
Measured rms noise of the adjustable LDO at 200 mA
without noise reduction of 220 µV rms
Measured rms noise of the adjustable LDO at 200 mA
with noise reduction circuit of 35 µV rms
Calculated rms noise of the adjustable LDO with noise
reduction (assuming 18 µV rms for fixed voltage option) of
34.5 µV rms
The noise of the LDO is approximately the noise of the fixed output
LDO (typically 18 µV rms) times the high frequency ac gain.
The following equation shows the calculation with the values
shown in Figure 87.
+
+/13
1/1471/13
1
1 × µV 18
(2)
Figure 88 shows the difference in noise spectral density for the
adjustable ADP7182 set to 15 V with and without the noise
reduction network. In the 100 Hz to 30 kHz frequency range,
the reduction in noise is significant.
100k
1
10
100
1k
10k
1100M10M1M100k10k1k10010
NOISE SPECTRAL DENSITY (nV Hz)
FREQUENCY (Hz)
–15V ADJ
–15V ADJ NR
10703-086
Figure 88. −15 V Adjustable ADP7182 with and without the
Noise Reduction Network (CNR and RNR)
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP7182 is protected against damage due to excessive power
dissipation by current-limit and thermal overload protection
circuits. The ADP7182 is designed to limit current when the
output load reaches −350 mA (typical). When the output load
exceeds 350 mA, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and power
dissipation) when the junction temperature starts to rise above
150°C, the output is turned off, reducing the output current to
0 mA. When the junction temperature falls below 135°C, the
output is turned on again, and the output current is restored to
the nominal value.
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP7182 limits current so that only 350 mA
is conducted into the short. If self-heating of the junction is great
enough to cause the temperature to rise above 150°C, thermal
shutdown is activated, turning off the output and reducing the
output current to 0 mA. As the junction temperature cools and
falls below 135°C, the output turns on and conducts −350 mA
into the short, again causing the junction temperature to rise
above 150°C. This thermal oscillation between 135°C and 150°C
causes a current oscillation between 350 mA and 0 mA that
continues as long as the short remains at the output.
Data Sheet ADP7182
Rev. J | Page 25 of 31
Current-limit and thermal overload protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation must be externally
limited so that the junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
In most applications, the ADP7182 does not dissipate much heat
due to the high efficiency. However, in applications with high
ambient temperature, and high supply voltage to output voltage
differential, the heat dissipated in the package is large enough that
it can cause the junction temperature of the die to exceed the
maximum junction temperature of 125°C.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is important to guarantee reliable performance over all conditions.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 3.
To guarantee reliable operation, the junction temperature of the
ADP7182 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The θJA number is dependent
on the package assembly compounds that are used, and the amount
of copper that solders the package VIN pins to the PCB.
Table 8 and Table 9 show typical θJA values of the 6- and 8-lead
and 5-lead TSOT packages for various PCB copper sizes.
Table 10 shows the typical ΨJB values of the 6- and 8-lead and
and 5-lead TSOT.
Table 8. Typical θJA Values of the LFCSP
θ
JA (°C/W)
Copper Size (mm2) 8-Lead LFCSP 6-Lead LFCSP
251175 177.8
100 135.6 138.2
500 77.3 79.8
1000 65.2 67.8
6400 51 53.5
1 Device soldered to minimum size pin traces.
Table 9. Typical θJA Values of the 5-Lead TSOT
Copper Size (mm2) θJA (°C/W)
01170
50 152
100 146
300 134
500 131
1 Device soldered to minimum size pin traces.
Table 10. Typical ΨJB Values
Model ΨJB (°C/W)
6-lead LFCSP 44.1
8-lead LFCSP 18.2
5-lead TSOT 43
The junction temperature of the ADP7182 can be calculated by
TJ = TA + (PD × θJA) (3)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VINVOUT) × ILOAD] + (VIN × IGND) (4)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can be
ignored. Therefore, the junction temperature equation simplifies to
TJ = TA + {[(VINVOUT) × ILOAD] × θJA} (5)
As shown in Equation 5, for a given ambient temperature, input-to-
output voltage differential, and continuous load current, there
exists a minimum copper size requirement for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 89
to Figure 97 show junction temperature calculations for different
ambient temperatures, power dissipation, and areas of PCB copper.
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP7182.
Adding thermal planes under the package also improves thermal
performance. However, as listed in Table 8 and Table 9, a point
of diminishing returns is reached eventually, beyond which an
increase in the copper area does not yield significant reduction
in the junction-to-ambient thermal resistance.
140
120
100
80
60
40
20
0
01.21.00.80.60.40.2
JUNCTION TEMPERATURE, T
J
(°C)
TOTAL POWER DISSIPATION (W)
6400mm
2
1000mm
2
500mm
2
100mm
2
25mm
2
JEDEC
T
J
MAX
10703-087
Figure 89. Junction Temperature vs. Total Power Dissipation for the
8-Lead LFCSP, TA = 25°C
ADP7182 Data Sheet
Rev. J | Page 26 of 31
140
120
100
80
60
40
20
0
01.21.00.80.60.40.2
JUNCTION TEMPERATURE, T
J
(°C)
TOTAL POWER DISSIPATION (W)
6400mm
2
1000mm
2
500mm
2
100mm
2
25mm
2
JEDEC
T
J
MAX
10703-088
Figure 90. Junction Temperature vs. Total Power Dissipation for the
8-Lead LFCSP, TA = 50°C
140
120
100
80
60
40
20
0
01.21.00.80.60.40.2
JUNCTION TEMPERATURE, T
J
(°C)
TOTAL POWER DISSIPATION (W)
6400mm
2
1000mm
2
500mm
2
100mm
2
25mm
2
JEDEC
T
J
MAX
10703-089
Figure 91. Junction Temperature vs. Total Power Dissipation for the
8-Lead LFCSP, TA = 85°C
10703-191
25
35
45
55
65
75
85
95
105
115
125
135
145
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
6400 mm
2
500 mm
2
25 mm
2
T
J
MAX
Figure 92. Junction Temperature vs. Total Power Dissipation for the
6-Lead LFCSP, TA = 25°C
50
60
70
80
90
100
110
120
130
140
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
10703-192
6400 mm
2
500 mm
2
25 mm
2
T
J
MAX
Figure 93. Junction Temperature vs. Total Power Dissipation for the
6-Lead LFCSP, TA = 50°C
65
75
85
95
105
115
125
135
145
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.9
0.8 1.0
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
10703-193
6400 mm
2
500 mm
2
25 mm
2
T
J
MAX
Figure 94. Junction Temperature vs. Total Power Dissipation for the
6-Lead LFCSP, TA = 85°C
140
120
100
80
60
40
20
0
01.21.00.80.60.40.2
JUNCTION TEMPERATURE, T
J
(°C)
TOTAL POWER DISSIPATION (W)
500mm
2
300mm
2
100mm
2
25mm
2
JEDEC
T
J
MAX
10703-090
Figure 95. Junction Temperature vs. Total Power Dissipation for the
5-Lead TSOT, TA = 25°C
Data Sheet ADP7182
Rev. J | Page 27 of 31
140
120
100
80
60
40
20
000.70.5 0.60.40.30.20.1
JUNCTION TEMPERATURE, T
J
C)
TOTAL POWER DISSIPATION (W)
500mm
2
300mm
2
100mm
2
25mm
2
JEDEC
T
J
MAX
10703-091
Figure 96. Junction Temperature vs. Total Power Dissipation for the
5-Lead TSOT, TA = 50°C
140
120
100
80
60
40
20
000.400.350.25 0.300.200.150.100.05
JUNCTION TEMPERATURE, T
J
C)
TOTAL POWER DISSIPATION (W)
500mm
2
300mm
2
100mm
2
25mm
2
JEDEC
T
J
MAX
10703-092
Figure 97. Junction Temperature vs. Total Power Dissipation for the
5-Lead TSOT, TA = 85°C
Thermal Characterization Parameter, ΨJB
When the board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction
temperature rise (see Figure 98 and Figure 100). Maximum
junction temperature (TJ) is calculated from the board temperature
(TB) and power dissipation (PD) using the following formula:
TJ = TB + (PD × ΨJB) (6)
The typical value of ΨJB is 18.2°C/W for the 8-lead LFCSP package,
44.1°C/W for the 6-lead LFCSP package and 43°C/W for the 5-lead
TSOT package.
140
120
100
80
60
40
20
00 75 64321
JUNCTION TEMPERATURE, T
J
C)
TOTAL POWER DISSIPATION (W)
T
B
= 25°C
T
B
= 50°C
T
B
= 85°C
T
J
MAX
10703-093
Figure 98. Junction Temperature vs. Total Power Dissipation for the
8-Lead LFCSP, TA = 85°C
10703-198
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
0
20
40
60
80
100
120
140
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
T
B
= 25°C
T
B
= 50°C
T
B
= 65°C
T
B
= 85°C
T
J
MAX
Figure 99. Junction Temperature vs. Total Power Dissipation for the
6-Lead LFCSP, TA = 85°C
140
120
100
80
60
40
20
00 75 64321
JUNCTION TEMPERATURE, T
J
C)
TOTAL POWER DISSIPATION (W)
T
B
= 25°C
T
B
= 50°C
T
B
= 85°C
T
J
MAX
10703-094
Figure 100. Junction Temperature vs. Total Power Dissipation for the
5-Lead TSOT, TA = 85°C
ADP7182 Data Sheet
Rev. J | Page 28 of 31
PCB LAYOUT CONSIDERATIONS
Place the input capacitor as close as possible to the VIN and GND
pins. Place the output capacitor as close as possible to the VOUT
and GND pins. Use of 1206 or 0805 size capacitors and resistors
achieves the smallest possible footprint solution on boards where
area is limited.
10703-100
Figure 101. Example of the 6-Lead LFCSP PCB Layout
10703-095
Figure 102. Example of the 8-Lead LFCSP PCB Layout
10703-096
Figure 103. Example of the 5-Lead TSOT PCB Layout
Data Sheet ADP7182
Rev. J | Page 29 of 31
Table 11. Recommended LDOs for Very Low Noise Operation
Device
Number
VIN
Range (V)
VOUT
Fixed (V)
VOUT
Adjust
(V)
IOUT
(mA)
IQ at
IOUT
(µA)
IGND-SD
Max
(µA)
Soft
Start PGOOD
Noise
(Fixed)
10 Hz to
100 kHz
(µV rms)
PSRR
100 kHz
(dB)
PSRR
1 MHz
(dB) Package
ADP7102
3.3 to 20
1.5 to 9
1.22 to
19
300
750
75
No
Yes
15
60
40
3 mm × 3 mm
8-lead LFCSP,
8-lead SOIC
ADP7104 3.3 to 20 1.5 to 9
1.22 to
19
500 900 75 No Yes 15 60 40
3 mm × 3 mm
8-lead LFCSP,
8-lead SOIC
ADP7105 3.3 to 20 1.8, 3.3, 5 1.22 to
19
500 900 75 Yes Yes 15 60 40 3 mm × 3 mm
8-lead LFCSP,
8-lead SOIC
ADP7118 2.7 to 20 1.2 to 5 1.2 to 19 200 160 10 Yes No 11 68 50 2 mm × 2 mm
6-lead LFCSP,
8-lead SOIC,
5-lead TSOT
ADP7142 2.7 to 40 1.2 to 5 1.2 to 39 200 160 10 Yes No 11 68 50 2 mm × 2 mm
6-lead LFCSP,
8-lead SOIC,
5-lead TSOT
ADP7182 2.7 to
−28
1.8 to
−5
1.22 to
−27
200 650 8 No No 18 45 45 2 mm × 2 mm
6-lead LFCSP,
3 mm × 3 mm
8-lead LFCSP,
5-lead TSOT
ADP7182 Data Sheet
Rev. J | Page 30 of 31
OUTLINE DIMENSIONS
1.70
1.60
1.50
0.425
0.350
0.275
TOP VIEW
6
1
4
3
0.35
0.30
0.25
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.60
0.55
0.50
1.10
1.00
0.90
0.20 REF
0.05 MAX
0.02 NOM
0.65 BSC
EXPOSED
PAD
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-06-2013-D
0.15 REF
2.10
2.00 SQ
1.90
0.20 MIN
Figure 104. 6-Lead Lead Frame Chip Scale Package [LFCSP]
2.00 mm × 2.00 mm Body and 0.55 Package Height
(CP-6-3)
Dimensions shown in millimeters
2.44
2.34
2.24
0.30
0.25
0.20
PIN 1 INDEX
AREA
0.80
0.75
0.70
1.70
1.60
1.50
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
3.10
3.00 SQ
2.90
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-W3030D-4
0.20 MIN
8
1
5
4
PKG-005136
02-10-2017-C
SEATING
PLANE
TOP VIEW
SIDE VIEW
EXPOSED
PAD
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
1
DETAIL A
(JEDEC 95)
Figure 105. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 Package Height
(CP-8-11)
Dimensions shown in millimeters
Data Sheet ADP7182
Rev. J | Page 31 of 31
100708-A
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
1.60 BSC 2.80 BSC
1.90
BSC
0.95 BSC
0.20
0.08
0.60
0.45
0.30
0.50
0.30
0.10 MAX
*1.00 MAX
*0.90 MAX
0.70 MIN
2.90 BSC
5 4
1 2 3
SEATING
PLANE
Figure 106. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Output Voltage (V)2 Package Description Package Option Branding
ADP7182ACPZ-R7 40°C to +125°C Adjustable 8-Lead LFCSP CP-8-11 LN6
ADP7182ACPZ-5.0-R7 40°C to +125°C −5 8-Lead LFCSP CP-8-11 LN9
ADP7182AUJZ-R7
40°C to +125°C
Adjustable
5-Lead TSOT
UJ-5
LN6
ADP7182AUJZ-1.8-R7 40°C to +125°C 1.8 5-Lead TSOT UJ-5 LN1
ADP7182AUJZ-2.5-R7 40°C to +125°C 2.5 5-Lead TSOT UJ-5 LN7
ADP7182AUJZ-3.0-R7 40°C to +125°C −3 5-Lead TSOT UJ-5 LN2
ADP7182AUJZ-5.0-R7 40°C to +125°C −5 5-Lead TSOT UJ-5 LN9
ADP7182ACPZN-R7 40°C to +125°C Adjustable 6-Lead LFCSP CP-6-3 LN6
ADP7182ACPZN-5.0R7 40°C to +125°C −5 6-Lead LFCSP CP-6-3 LN9
ADP7182ACPZN-2.5R7 40°C to +125°C 2.5 6-Lead LFCSP CP-6-3 LN7
ADP7182ACPZN-1.5R7 40°C to +125°C −1.5 6-Lead LFCSP CP-6-3 LQK
ADP7182ACPZN-1.2R7 40°C to +125°C 1.2 6-Lead LFCSP CP-6-3 LRE
ADP7182UJ-EVALZ Evaluation Board, TSOT
ADP7182CP-EVALZ Evaluation Board, LFCSP
1 Z = RoHS Compliant Part.
2 For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.
©20132017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10703-0-3/17(J)

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