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ADM3202,22, ADM1385 Datasheet

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Datasheet

Low Power, 3.3 V, RS-232
Line Drivers/Receivers
ADM3202/ADM3222/ADM1385
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1998–2011 Analog Devices, Inc. All rights reserved.
FEATURES
460 kbps data rate
Specified at 3.3 V
Meets EIA-232E specifications
0.1 μF charge pump capacitors
Low power shutdown (ADM3222 and ADM1385)
PDIP, SOIC_N, SOIC_W, SSOP, and TSSOP options
Upgrade for MAX3222/MAX3232 and LTC1385
ESD protection to IEC 1000-4-2 (801.2)
on RS-232 pins (ADM3202 only)
±8 kV: contact discharge
±15 kV: air gap discharge
APPLICATIONS
General-purpose RS-232 data link
Portable instruments
Printers, palmtop computers, PDAs
GENERAL DESCRIPTION
The ADM3202/ADM3222/ADM1385 transceivers are high
speed, 2-channel RS-232/V.28 interface devices that operate
from a single 3.3 V power supply. Low power consumption and
a shutdown facility (ADM3222/ADM1385) make them ideal for
battery-powered portable instruments.
The ADM3202/ADM3222/ADM1385 parts conform to the
EIA-232E and CCITT V.28 specifications and operate at data
rates up to 460 kbps.
Four external 0.1 μF charge pump capacitors are used for the
voltage doubler/inverter, permitting operation from a single
3.3 V supply.
The ADM3222 contains additional enable and shutdown
circuitry. The EN input can be used to three-state the receiver
outputs. The SD input is used to power down the charge pump
and transmitter outputs, reducing the quiescent current to less
than 0.5 μA. The receivers remain enabled during shutdown
unless disabled using EN.
The ADM1385 contains a driver disable mode and a complete
shutdown mode.
The ADM3202 is available in a 16-lead PDIP, SOIC_W, and
SOIC_N, as well as a space-saving 16-lead TSSOP. The ADM3222
is available in 18-lead PDIP and SOIC_W and in 20-lead SSOP
and TSSOP. The ADM1385 is available in a 20-lead SSOP,
which is pin-compatible with the LTC1385 CG.
FUNCTIONAL BLOCK DIAGRAMS
C1+
C2+
C1–
C2–
V
CC
V–
V+
T1
IN
T1
OUT
T2
IN
T2
OUT
R1
OUT
R1
IN
R2
OUT
R2
IN
CMOS
INPUTS
EIA/TIA-232
OUTPUTS
CMOS
OUTPUTS
EIA/TIA-232
INPUTS*
T1
T2
R1
R2
+
+
+
0.1µF
10V
0.1µF
10V
GND
ADM3202
C3
0.1µF
6.3V
+3.3
V
INPUT
+3.3V TO +6.6V
VOLTAGE
DOUBLER
+6.6V TO –6.6V
VOLTAGE
INVERTER
C5
0.1µF
+
C4
0.1µF
10V
+
*INTERNAL 5kPULL-DOWN RESISTOR
ON EACH RS-232 INPUT
00071-001
Figure 1.
C1+
C2+
C1–
C2–
V
CC
V–
V+
T1
IN
T1
OUT
T2
IN
T2
OUT
R1
OUT
R1
IN
R2
OUT
EN
R2
IN
SD
CMOS
INPUTS
EIA/TIA-232
OUTPUTS
CMOS
OUTPUTS
EIA/TIA-232
INPUTS*
T1
T2
R1
R2
+
+
+
0.1µF
10V
0.1µF
10V
GND
ADM3222
C3
0.1µF
6.3V
+3.3
V
INPUT
+3.3V TO +6.6V
VOLTAGE
DOUBLER
+6.6V TO –6.6V
VOLTAGE
INVERTER
C5
0.1µF
+
C4
0.1µF
10V
+
*INTERNAL 5kPULL-DOWN RESISTOR
ON EACH RS-232 INPUT
00071-002
Figure 2.
C1+
C2+
C1–
C2–
V
CC
V–
V+
T1
IN
T1
OUT
T2
IN
T2
OUT
R1
OUT
R1
IN
R2
OUT
DD
R2
IN
SD
CMOS
INPUTS
EIA/TIA-232
OUTPUTS
CMOS
OUTPUTS
EIA/TIA-232
INPUTS*
T1
T2
R1
R2
+
+
0.1µF
10V
0.1µF
10V
GND
ADM1385
+3.3V INPUT
+3.3V TO +6.6V
VOLTAGE
DOUBLER
+6.6V TO –6.6V
VOLTAGE
INVERTER
C5
0.1µF
+
+
+
*INTERNAL 5k PULL-DOWN RESISTOR
ON EACH RS-232 INPUT
00071-003
C3
0.1µF
10V
C4
0.1µF
10V
Figure 3.
ADM3202/ADM3222/ADM1385
Rev. E | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Pin Configurations (N, RN, RU, and RW Packages)................5
Pin Configurations (RS and RU Packages)................................5
Typical Performance Characteristics ..............................................6
General Description..........................................................................8
Circuit Description .......................................................................8
High Baud Rate..............................................................................9
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 14
REVISION HISTORY
7/11—Rev. D to Rev. E
Changes to Figure 3.......................................................................... 1
Changes to Table 2............................................................................ 4
Changes to Figure 17........................................................................ 8
Updated Outline Dimensions....................................................... 10
Changes to Ordering Guide .......................................................... 14
8/06—Rev. C to Rev. D
Changes to Table 1............................................................................ 3
Updated Outline Dimensions....................................................... 10
Changes to Ordering Guide .......................................................... 12
9/05—Rev. B to Rev. C
Updated Outline Dimensions....................................................... 10
Changes to Ordering Guide .......................................................... 12
12/01—Rev. A to Rev. B
Changes to Specifications Page....................................................... 2
ADM3202/ADM3222/ADM1385
Rev. E | Page 3 of 16
SPECIFICATIONS
VCC = 3.3 V ± 0.3 V, C1 to C4 = 0.1 μF. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DC CHARACTERISTICS
Operating Voltage Range 3.0 3.3 5.5 V
VCC Power Supply Current 1.3 3 mA No load
8 12 mA RL = 3 kΩ to GND
Shutdown Supply Current 0.01 0.5 μA
LOGIC
Input Logic Threshold Low, VINL 0.8 V TIN
Input Logic Threshold High, VINH 2.0 V TIN
CMOS Output Voltage Low, VOL 0.4 V IOUT = 1.6 mA
CMOS Output Voltage High, VOH VCC − 0.6 V IOUT = −1 mA
Logic Pull-Up Current 5 10 μA TIN = GND to VCC 1
Output Leakage Current ±10 μA Receivers disabled
RS-232 RECEIVER
EIA-232 Input Voltage Range −30 +30 V
EIA-232 Input Threshold Low 0.6 1.2 V
EIA-232 Input Threshold High 1.6 2.4 V
EIA-232 Input Hysteresis 0.4 V
EIA-232 Input Resistance 3 5 7
RS-232 TRANSMITTER
Output Voltage Swing (RS-232) ±5.0 ±5.2 V VCC = 3.3 V, all transmitter outputs loaded with 3 kΩ to ground
Output Voltage Swing (RS-562) ±3.7 V VCC = 3.0 V
Transmitter Output Resistance 300 Ω VCC = 0 V, VOUT = ±2 V
RS-232 Output Short-Circuit Current ±15 mA
Output Leakage Current ±25 μA SD = low, VOUT = 12 V
TIMING CHARACTERISTICS
Maximum Data Rate 460 kbps VCC = 3.3 V, RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF, one
Tx switching
Receiver Propagation Delay
TPHL 0.4 1 μs
TPLH 0.4 1 μs
Transmitter Propagation Delay 0.3 1.2 μs RL = 3 kΩ, CL = 1000 pF
Receiver Output Enable Time 200 ns
Receiver Output Disable Time 200 ns
Transmitter Skew 30 ns
Receiver Skew 300 ns
Transition Region Slew Rate 5.5 10 30 V/μs Measured from +3 V to −3 V or −3 V to +3 V, VCC = +3.3 V;
RL = 3 kΩ, CL = 1000 pF, TA = 25°C
1 ADM1385: Input leakage current typically −10 μA when TIN = GND.
ADM3202/ADM3222/ADM1385
Rev. E | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
VCC −0.3 V to +6 V
V+ (VCC − 0.3 V) to +14 V
V− +0.3 V to –14 V
Input Voltages
TIN −0.3 V to (V+, +0.3 V)
RIN ±30 V
Output Voltages
TOUT ±15 V
ROUT −0.3 V to (VCC + 0.3 V)
Short-Circuit Duration
TOUT Continuous
Power Dissipation (Derates 6 mW/°C
above 50°C)
450 mW
Thermal Impedance, θJA
N-16/N-18 (2-Layer Test Board) 117°C/W
RW-16/RW-18 (4-Layer Test Board) 56°C/W
R-16 (4-Layer Test Board) 81°C/W
RU-16 (4-Layer Test Board) 113°C/W
RU-20 (4-Layer Test Board) 110°C/W
RS-20 (4-Layer Test Board) 83°C/W
Operating Temperature Range
Industrial (A Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
(Soldering, 10 sec)
JEDEC industry
standard J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADM3202/ADM3222/ADM1385
Rev. E | Page 5 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS (N, R, RU, AND RW PACKAGES)
C1+ 1
V+ 2
C1– 3
C2+ 4
VCC
16
GND
15
T1OUT
14
R1IN
13
C2– 5R1OUT
12
V– 6T1IN
11
T2OUT 7T2IN
10
R2IN 8R2OUT
9
ADM3202
TOP VIEW
(Not to Scale)
00071-004
Figure 4. N, R, RU, and RW Packages Pin Configuration
EN
1
C1+
2
V+
3
C1–
4
SD
18
V
CC
17
GND
16
T1
OUT
15
C2+
5
C2–
6
V–
7
R1
IN
14
R1
OUT
13
T1
IN
12
T2
OUT 8
T2
IN
11
R2
IN 9
R2
OUT
10
ADM3222
TOP VIEW
(Not to Scale)
00071-005
Figure 5. N and RW Packages Pin Configuration
PIN CONFIGURATIONS (RS AND RU PACKAGES)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
C1+
V+
C1–
V–
C2–
C2+
EN
V
CC
GND
T1
OUT
NC
R1
OUT
R1
IN
R2
OUT
R2
IN
T2
OUT
NC
T2
IN
T1
IN
SD
ADM3222
(SSOP/TSSOP)
TOP VIEW
(Not to Scale)
NC = NO CONNECT
00071-006
Figure 6. RS and RU Packages Pin Configuration
DD
1
C1+
2
V+
3
C1–
4
SD
20
V
CC
19
GND
18
T1
OUT
17
C2+
5
C2–
6
V–
7
R1
IN
16
R1
OUT
15
T1
IN
14
T
2
OUT 8
T2
IN
13
R2
IN 9
R2
OUT
12
NC
10
NC
11
NC = NO CONNECT
ADM1385
(SSOP)
TOP VIEW
(Not to Scale)
00071-007
Figure 7. RS Package Pin Configuration
Table 3. Pin Function Descriptions
Mnemonic Description
VCC Power Supply Input (3.3 V ± 0.3 V).
V+ Internally Generated Positive Supply (+6 V nominal).
V– Internally Generated Negative Supply (−6 V nominal).
GND Ground Pin. Must be connected to 0 V.
C1+, C1– External Capacitor 1 is connected between these pins. A 0.1 μF capacitor is recommended but larger capacitors up to 47 μF
can be used.
C2+, C2– External Capacitor 2 is connected between these pins. A 0.1 μF capacitor is recommended but larger capacitors up to 47 μF
can be used.
TxIN Transmitter (Driver) Inputs. These inputs accept TTL/CMOS levels.
TxOUT Transmitter (Driver) Outputs. These are RS-232 signal levels (typically ±9 V).
RxIN Receiver Inputs. These inputs accept RS-232 signal levels. An internal 5 pull-down resistor to GND is connected on each input.
RxOUT Receiver Outputs. These are CMOS output logic levels.
EN (ADM3222 only) Receiver Enable. Active low. When low, the receiver outputs are enabled. When high, they are three-stated.
SD (ADM3222 only) Shutdown Control. Active low. When low, the charge pump is shut down and the transmitter outputs
are disabled.
SD (ADM1385 only) Shutdown Control. When low, the charge pump is shut down and all transmitters and receivers are disabled.
DD (ADM1385 only) Driver Disable. When low, the charge pump is turned off and the transmitters are disabled. The receivers
remain active.
NC No Connect.
ADM3202/ADM3222/ADM1385
Rev. E | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
LOAD CAPACITANCE (pF)
8
6
4
2
0
–2
–4
–6
–8
0 1200200 400 600 800
T
OUT
(HIGH)
T
OUT
(LOW)
Tx O/P VOLTAGE (V)
1000
00071-008
Figure 8. Transmitter Output Voltage High/Low vs.
Load Capacitance @ 460 kbps
V
CC
(V)
8
2.7 2.9 3.1 3.3 3.5
Tx O/P HIGH
Tx O/P (V)
6
4
2
0
2
4
6
8
Tx O/P LOW
00071-009
Figure 9. Transmitter Output Voltage vs. VCC
LOAD CURRENT (mA)
8
02468
Tx O/P (V)
6
4
2
0
–2
–4
–6
–8
10 12
Tx O/P LOW
Tx O/P HIGH
00071-010
Figure 10. Transmitter Output Voltage Low/High vs. Load Current
LOAD CURRENT (mA)
8
02468
V+
V+, V– (V)
6
4
2
0
–2
–4
–6
–8
V–
10 12
00071-011
Figure 11. Charge Pump V+, V− vs. Load Current
V
CC
(V)
350
2.7 2.9 3.1 3.3 3.5
IMPEDANCE ()
300
250
200
150
100
50
0
V+ (IMPEDANCE)
V– (IMPEDANCE)
00071-012
Figure 12. Charge Pump Impedance vs. VCC
LOAD CAPACITANCE (pF)
20
0 1000 2000 3000
I
CC
@ 230kbps
I
CC
(mA)
18
16
14
12
10
2
0
8
6
4
I
CC
@ 460kbps
00071-013
Figure 13. Power Supply Current vs. Load Capacitance
ADM3202/ADM3222/ADM1385
Rev. E | Page 7 of 16
1
CH 1 5.00V CH 2 5.00V M1.00µs CH1 0V
T
2
T
00071-014
Figure 14. 460 kbps Data Transmission
ADM3202/ADM3222/ADM1385
Rev. E | Page 8 of 16
GENERAL DESCRIPTION
The ADM3202/ADM3222/ADM1385 are RS-232 line drivers/
receivers. Step-up voltage converters coupled with level-shifting
transmitters and receivers allow RS-232 levels to be developed
while operating from a single 3.3 V supply.
CMOS technology is used to keep the power dissipation to an
absolute minimum, allowing maximum battery life in portable
applications.
The ADM3202/ADM3222/ADM1385 are modifications,
enhancements, and improvements of the AD230 to AD241
family and derivatives. They are essentially plug-in compatible
and do not have any materially different applications.
CIRCUIT DESCRIPTION
The internal circuitry consists of these main sections:
A charge pump voltage converter
3.3 V logic to EIA-232 transmitters
EIA-232 to 5 V logic receivers
Charge Pump DC to DC Voltage Converter
The charge pump voltage converter consists of a 200 kHz
oscillator and a switching matrix. The converter generates a
±6.6 V supply from the input 3.3 V level. This is done in two
stages by using a switched capacitor technique as illustrated in
Figure 18 and Figure 19. First, the 3.3 V input supply is doubled
to 6.6 V by using Capacitor C1 as the charge storage element.
The +6.6 V level is then inverted to generate −6.6 V using C2
as the storage element. C3 is shown connected between V+ and
VCC but is equally effective if connected between V+ and GND.
Capacitors C3 and C4 are used to reduce the output ripple.
Their values are not critical and can be increased, if desired.
Capacitor C3 is shown connected between V+ and VCC. It is
also acceptable to connect this capacitor between V+ and GND.
If desired, larger capacitors (up to 10 μF) can be used for
Capacitors C1 to C4.
C1+
C2+
C1–
C2–
V
CC
V–
V+
T1
IN
T1
OUT
T2
IN
T2
OUT
R1
OUT
R1
IN
R2
OUT
R2
IN
CMOS
INPUTS
EIA/TIA-232
OUTPUTS
CMOS
OUTPUTS
EIA/TIA-232
INPUTS*
T1
T2
R1
R2
+
+
+
0.1µF
10V
0.1µF
10V
GND
ADM3202
C3
0.1µF
6.3V
+3.3
V
INPUT
+3.3V TO +6.6V
VOLTAGE
DOUBLER
+6.6V TO –6.6V
VOLTAGE
INVERTER
C5
0.1µF
+
C4
0.1µF
10V
+
*INTERNAL 5kPULL-DOWN RESISTOR
ON EACH RS-232 INPUT
00071-015
Figure 15. ADM3202 Typical Operating Circuit
C1+
C2+
C1–
C2–
V
CC
V–
V+
T1
IN
T1
OUT
T2
IN
T2
OUT
R1
OUT
R1
IN
R2
OUT
EN
R2
IN
SD
CMOS
INPUTS
EIA/TIA-232
OUTPUTS
CMOS
OUTPUTS
EIA/TIA-232
INPUTS*
T1
T2
R1
R2
+
+
+
0.1µF
10V
0.1µF
10V
GND
ADM3222
C3
0.1µF
6.3V
+3.3
V
INPUT
+3.3V TO +6.6V
VOLTAGE
DOUBLER
+6.6V TO –6.6V
VOLTAGE
INVERTER
C5
0.1µF
+
C4
0.1µF
10V
+
*INTERNAL 5kPULL-DOWN RESISTOR
ON EACH RS-232 INPUT
00071-016
Figure 16. ADM3222 Typical Operating Circuit
C1+
C2+
C1–
C2–
V
CC
V–
V+
T1
IN
T1
OUT
T2
IN
T2
OUT
R1
OUT
R1
IN
R2
OUT
DD
R2
IN
SD
CMOS
INPUTS
EIA/TIA-232
OUTPUTS
CMOS
OUTPUTS
EIA/TIA-232
INPUTS*
T1
T2
R1
R2
+
+
0.1µF
10V
0.1µF
10V
GND
ADM1385
+3.3V INPUT
+3.3V TO +6.6V
VOLTAGE
DOUBLER
+6.6V TO –6.6V
VOLTAGE
INVERTER
C5
0.1µF
+
+
+
*INTERNAL 5k PULL-DOWN RESISTOR
ON EACH RS-232 INPUT
00071-017
C3
0.1µF
10V
C4
0.1µF
10V
Figure 17. ADM1385 Typical Operating Circuit
C1 +C3 +
S3
S4
S1
S2
INTERNAL
OSCILLATOR
V
CC
GND V
CC
V+ = 2V
CC
00071-018
Figure 18. Charge Pump Voltage Doubler
C2 +C4 +
S3
S4
S1
S2
INTERNAL
OSCILLATOR
V
+
GND V– = –(V+)
GND
FROM
VOLTAGE
DOUBLER
00071-019
Figure 19. Charge Pump Voltage Inverter
ADM3202/ADM3222/ADM1385
Rev. E | Page 9 of 16
Transmitter (Driver) Section
The drivers convert 3.3 V logic input levels into RS-232 output
levels. With VCC = 3.3 V and driving an RS-232 load, the output
voltage swing is typically ±6 V.
Receiver Section
The receivers are inverting level-shifters that accept RS-232
input levels and translate them into 3 V logic output levels. The
inputs have internal 5 kΩ, pull-down resistors to ground and are
protected against overvoltages up to ±30 V. Unconnected inputs
are pulled to 0 V by the internal 5 kΩ, pull-down resistor. This
results in a Logic 1 output level for unconnected inputs or for
inputs connected to GND.
The receivers have Schmitt-trigger inputs with a hysteresis level
of 0.4 V. This ensures error-free reception for both noisy inputs
and for inputs with slow transition times.
HIGH BAUD RATE
The ADM3202/ADM3222 feature high slew rates permitting
data transmission at rates well in excess of the EIA/RS-232E
specifications. RS-232 voltage levels are maintained at data rates
up to 460 kbps even under worst-case loading conditions. This
allows high speed data links between two terminals and is
suitable for the new generation ISDN modem standards that
require data rates of 230 kbps. The slew rate is internally
controlled to less than 30 V/μs to minimize EMI interference.
ADM3202/ADM3222/ADM1385
Rev. E | Page 10 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001-AB
073106-B
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
16
18
9
0.100 (2.54)
BSC
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 20. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16 9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
060606-A
45°
Figure 21. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
ADM3202/ADM3222/ADM1385
Rev. E | Page 11 of 16
16 9
81
PIN 1
SEATING
PLANE
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 22. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 23. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ADM3202/ADM3222/ADM1385
Rev. E | Page 12 of 16
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001
070706-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
18
19
10
0.100 (2.54)
BSC
0.920 (23.37)
0.900 (22.86)
0.880 (22.35)
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 24. 18-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-18)
Dimensions shown in inches and (millimeters)
COMPLIANT TO JEDEC STANDARDS MO-150-AE
060106-A
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 MIN
0.65 BSC
2.00 MAX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
Figure 25. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
ADM3202/ADM3222/ADM1385
Rev. E | Page 13 of 16
COMPLIANT TO JEDEC STANDARDS MO-153-AC
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC
1.20 MAX 0.20
0.09 0.75
0.60
0.45
COPLANARIT
Y
0.10
Figure 26. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AB
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
18 10
9
1
1.27
(0.0500)
BSC
11.75 (0.4626)
11.35 (0.4469)
060706-A
45°
Figure 27. 18-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-18)
Dimensions shown in millimeters and (inches)
ADM3202/ADM3222/ADM1385
Rev. E | Page 14 of 16
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADM3202AN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADM3202ANZ −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADM3202ARN −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM3202ARN-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM3202ARN-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM3202ARNZ −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM3202ARNZ-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM3202ARNZ-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADM3202ARU −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM3202ARU-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM3202ARU-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM3202ARUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM3202ARUZ-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM3202ARUZ-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADM3202ARW −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM3202ARW-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM3202ARWZ −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM3202ARWZ-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM3202ARWZ-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM3222AN −40°C to +85°C 18-Lead Plastic Dual In-Line Package [PDIP] N-18
ADM3222ANZ −40°C to +85°C 18-Lead Plastic Dual In-Line Package [PDIP] N-18
ADM3222ARS −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADM3222ARS-REEL −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADM3222ARS-REEL7 −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADM3222ARSZ −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADM3222ARSZ-REEL −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADM3222ARSZ-REEL7 −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADM3222ARU −40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADM3222ARU-REEL −40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADM3222ARU-REEL7 −40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADM3222ARUZ −40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADM3222ARUZ-REEL −40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADM3222ARUZ-REEL7 −40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADM3222ARW −40°C to +85°C 18-Lead Standard Small Outline Package [SOIC_W] RW-18
ADM3222ARW-REEL −40°C to +85°C 18-Lead Standard Small Outline Package [SOIC_W] RW-18
ADM3222ARWZ −40°C to +85°C 18-Lead Standard Small Outline Package [SOIC_W] RW-18
ADM3222ARWZ-REEL −40°C to +85°C 18-Lead Standard Small Outline Package [SOIC_W] RW-18
ADM3222ARWZ-REEL7 −40°C to +85°C 18-Lead Standard Small Outline Package [SOIC_W] RW-18
ADM1385ARS −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADM1385ARSZ −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADM1385ARSZ-REEL −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
ADM1385ARSZ-REEL7 −40°C to +85°C 20-Lead Shrink Small Outline Package [SSOP] RS-20
1 Z = RoHS Compliant Part.
ADM3202/ADM3222/ADM1385
Rev. E | Page 15 of 16
NOTES
ADM3202/ADM3222/ADM1385
Rev. E | Page 16 of 16
NOTES
©1998–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00071-0-7/11(E)

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