The internal delay line architecture has been revised to allow clock signals to be delayed by up to a full period or more. Combined with an on-chip reference delay (to offset the inherent or “step zero” delay of the device) clock phase can now be varied over the full 0-360 degree range.

• Step sizes of 0.25ns, 0.5ns, 1ns, 2ns, 5ns
• On-chip reference delay
• Configurable as delay line, pulse width modulator, or free-running oscillator
• Can delay clocks by a full period or more
• Guaranteed monotonicity
• Parallel or serial programming